CN105226098A - A kind of FinFET semiconductor device and preparation method thereof - Google Patents
A kind of FinFET semiconductor device and preparation method thereof Download PDFInfo
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- CN105226098A CN105226098A CN201510662388.6A CN201510662388A CN105226098A CN 105226098 A CN105226098 A CN 105226098A CN 201510662388 A CN201510662388 A CN 201510662388A CN 105226098 A CN105226098 A CN 105226098A
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- finfet
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- semiconductor substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000002360 preparation method Methods 0.000 title claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000003989 dielectric material Substances 0.000 claims abstract description 23
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 17
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 2
- 238000000227 grinding Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 description 6
- 238000006396 nitration reaction Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention relates to semiconductor device structure technical field, particularly relate to a kind of FinFET semiconductor device and preparation method thereof, by the Semiconductor substrate providing a preparation to have the first projection and the second projection, prepare oxide skin(coating) successively, high K gusset material layer and gate material layers, preparation comprises Semiconductor substrate, the FinFET of high-k dielectric material layer and gate material layers, the technical program has effectively prepared the grid comprising 4T-FinFET and 3T-FinFET, again two grids are combined simultaneously, effectively overcome traditional scheme and by with cmp, the grid on Fin top cannot be removed the rear problem being difficult to be integrated together by 4T-FinFET and 3T-FinFET, overcome simultaneously, by increasing by one light shield, the grid etch on the Fin top of specifying is fallen the problem brought to the alignment of photo.
Description
Technical field
The present invention relates to semiconductor device structure technical field, particularly relate to a kind of FinFET semiconductor device and forming method thereof.
Background technology
At present, have two kinds of approach by two of FinFET grids separately in prior art, a kind of is remove with the grid of cmp by Fin top, but in traditional FinFET structure, the method is difficult to 4T-FinFET and 3T-FinFET to be integrated together; Another kind method is increase by one light shield, is fallen by the grid etch on the Fin top of specifying, but the method is a huge challenge for the alignment of photo.
Therefore, condition decline 4T-FinFET and 3T-FinFET how separated at two grids of FinFET is integrated together a great problem becoming those skilled in the art and face.
Summary of the invention
In view of the above problems, the present invention proposes a kind of FinFET semiconductor device and preparation method thereof, by the Semiconductor substrate providing a preparation to have the first projection and the second projection, prepare oxide skin(coating), high K gusset material layer and gate material layers successively, preparation comprises the FinFET of Semiconductor substrate, high-k dielectric material layer and gate material layers, and this technical scheme is specially:
A kind of FinFET, wherein, described FinFET comprises:
Preparation has the semiconductor base of the first projection and the second projection;
High-k dielectric material layer, on the upper surface being positioned at described Semiconductor substrate, covers the upper surface of described Semiconductor substrate, the upper surface of the first projection and the sidewall of side surface and the second projection;
Gate material layers, is positioned on described high-k dielectric material layer, and wherein, the upper surface of described gate material layers and the upper surface of described second projection are positioned at same level.
Above-mentioned FinFET, wherein, described FinFET also comprises:
Oxide skin(coating), between described high-k dielectric material layer and described semiconductor base.
Above-mentioned FinFET, wherein, the material of described oxide skin(coating) is silica.
Above-mentioned FinFET, wherein, the material of described semiconductor base is monocrystalline silicon.
Above-mentioned FinFET, wherein, the material of described high-k dielectric material layer is HfO2.
Above-mentioned FinFET, wherein, described gate material layers material is metal.
Above-mentioned FinFET, wherein, described gate material layers material is oxide.
A preparation method for FinFET, wherein, described preparation method comprises:
Semi-conductive substrate is provided;
In Semiconductor substrate, prepare first protruding and the second projection, form semiconductor base;
In the region overlay monoxide layer except described first projection and described second projection of the upper surface of described semiconductor base;
Cover a high-k dielectric material layer in the sidewall of the sidewall of the upper surface of described oxide, described first projection and upper surface and described second projection and upper surface;
Prepare a gate material layers on the described high-k dielectric material layer removing the second protruding top, make the upper surface of the upper surface of described gate material layers and described second projection be positioned at same level.
Above-mentioned preparation method, wherein, in described method, prepares the first step that is protruding and the second projection and also comprises in Semiconductor substrate:
A depression is prepared in Semiconductor substrate;
Cover mononitride layer on described first depression and described Semiconductor substrate, the nitride layer on described first depression and described Semiconductor substrate is in same level;
Adopt chemical mechanical milling tech, make the upper surface of nitride layer in described first depression and the upper surface of described Semiconductor substrate be positioned at same level;
Cover one first mask layer on described nitride layer, and cover one second mask layer on the upper surface not comprising the first sunk part of described Semiconductor substrate;
With the first mask layer and the second mask layer for grinding, etch downwards, the Semiconductor substrate to described first mask layer exposes preset height;
Remove the nitride layer below described first mask layer, described second mask layer and described first mask layer, form first protruding and the second projection.
Above-mentioned preparation method, wherein, described nitride is silicon nitride.
Above-mentioned preparation method, wherein, in described method, the step that preparation gate material layers makes the upper surface of the upper surface of described gate material layers and described second projection be positioned at same level also comprises:
Cover a gate material layers on described high-k dielectric material layer;
Etching, removes the high K gusset material layer on described second upper convex surface and gate material layers.
Technique scheme tool has the following advantages or beneficial effect:
Pass through the technical program, effectively prepare the grid comprising 4T-FinFET and 3T-FinFET, again two grids are combined simultaneously, effectively overcome traditional scheme and by with cmp, the grid on Fin top cannot be removed the rear problem being difficult to be integrated together by 4T-FinFET and 3T-FinFET, overcome simultaneously, by increasing by one light shield, the grid etch on the Fin top of specifying is fallen the problem brought to the alignment of photo.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 is the structural representation of FinFET semiconductor device in one embodiment of the invention;
Fig. 2 is the flow chart of the method preparing FinFET in one embodiment of the invention;
Fig. 3-15 prepares the structural representation of the process of FinFET for the present invention.
Embodiment
In order to allow the personnel possessing field Conventional wisdom belonging to this invention easily implement this invention, with reference to accompanying drawing shown below, the example of this invention is described in detail.But this invention can be implemented according to different forms, is not only confined to example described herein.In order to definitely this invention is described, eliminate part irrelevant with explanation in drawing; And, in whole specification, give similar drawing symbol to similar portions.
In the whole specification of this invention, some parts and another part " connection ", not only comprise " directly connecting ", also comprise " the electrical resistance connection " that be connected by other components and parts.
In the whole specification of this invention, some parts are positioned at " top " of another parts, not only comprise the state of some parts and another parts joint, also comprise the state being also provided with another parts between two parts.
In the whole specification of this invention, certain part " comprises " certain inscape and refers to, under the prerequisite of not forbidding equipment especially, is not get rid of other inscapes, but can also comprises other inscapes.
The terms of degree " about ", " in fact " etc. that adopt in the whole specification of this invention, if prompting has manufacture and material admissible error, with regard to expression respective value or close to this numerical value; Its objective is, prevent bad personnel that the disclosure relating to exact value or absolute figure is used for improper purposes.The terms of degree that uses in the whole specification of this invention " ~ (in) stage " or " ~ stage ", be not " in order to ~ stage ".
' parts ' in this specification refer to, the unit (unit) be made up of hardware, the unit by software sharing, the unit that is made up of software and hardware.
In addition, unit can be made up of plural hardware or plural unit is made up of a hardware.In this specification, the operation implemented by terminal, device or equipment or function, a part wherein can utilize the server generation be connected with corresponding terminal, device or equipment for implementing.Equally, by operation or the function of server implementation, a part wherein also can utilize terminal, device or the equipment be connected with this server to replace implementing.Next, with reference to accompanying drawing, the example of this invention is described in detail.
Structure shown in Figure 1, the invention provides a kind of FinFET semiconductor device, and this device mainly comprises the semiconductor base 1 that preparation has the first protruding 51 and second projection 52;
High-k dielectric material layer 7, on the upper surface being positioned at Semiconductor substrate 1, covers the sidewall of the upper surface of Semiconductor substrate, the upper surface of the first projection 51 and side surface and the second projection 52.
Gate material layers 81, is positioned on high-k dielectric material layer 7, and wherein, the upper surface of gate material layers 81 and the upper surface of the second projection 52 are positioned at same level.
As a preferred embodiment of the invention, FinFET also comprises:
Oxide skin(coating) 61, between high-k dielectric material layer and semiconductor base.
As a preferred embodiment of the invention, the material of oxide skin(coating) is silica.
As a preferred embodiment of the invention, the material of semiconductor base is monocrystalline silicon.
As a preferred embodiment of the invention, the material of high-k dielectric material layer is HfO2.
As a preferred embodiment of the invention, gate material layers material can be metal, and this metal is TIN, TaN or AL.
As a preferred embodiment of the invention, gate material layers material is oxide, and first adopt the technique such as oxidation technology or original position moisture-generation process (ISSG) outside raceway groove, form oxide layer, then deposit spathic silicon is as grid.
Structure shown in Figure 2, the invention provides a kind of preparation method of FinFET semiconductor device, the method mainly comprises:
First, provide semi-conductive substrate 1, structural representation shown in Figure 3.
Preferably, the process preparing the first protruding 51 and second projection 52 comprises:
Cover the mask layer 2 of a patterning at the upper surface of a left side half side region of Semiconductor substrate 1, with mask layer 2 for mask, etching, forms the first groove, forms structural representation as shown in Figure 4.
On the upper surface of the first groove and the upper surface do not etched of Semiconductor substrate 1, cover mononitride layer 3, the upper surface of nitride 3 is the level of state, and forms structural representation shown in Figure 5.
Adopt mechanical milling tech, the upper surface of the nitride in the upper surface do not etched of described Semiconductor substrate 1 and described first groove is made to be positioned at same level, after mechanical lapping, nitration case 3 becomes the structure of nitration case 31 by original structure, forms structural representation shown in Figure 6.
Cover the mask layer 42 of a patterning on the upper surface do not etched of Semiconductor substrate, and the mask layer 41 of covering one patterning is in the upper surface of nitration case 31, forms structural representation shown in Figure 7.
With mask layer 42 for mask, Semiconductor substrate below etching mask layer 42, and with mask layer 41 for mask, the upper surface of nitration case 31 to the Semiconductor substrate 1 below etching mask layer 41, wherein, the degree of depth of the Semiconductor substrate below etching mask layer 42 is identical with the thickness of nitration case 31, is formed see the structural representation described in Fig. 8-9.
Continue to etch desired depth downwards, this desired depth is the degree of depth required for follow-up making grid, forms structural representation shown in Figure 10.
Remove mask layer 41 and mask layer 42, form the first protruding 51 and second projection 52 on a semiconductor substrate, form structural representation shown in Figure 11.
Continue, first an oxide layer 6 is covered in the upper surface of Semiconductor substrate 1 and the upper surface of the first projection and the upper surface of sidewall and the second projection and sidewall, form structural representation shown in Figure 12, continue, cover the mask layer of a patterning, the oxide layer of etching removal first convex top and partial sidewall, and second oxide layer of protruding and partial sidewall, after etching, oxide layer 6 forms the structure of oxidation layer by layer shown in 61, forms structural representation shown in Figure 13.
Continue, cover a high-k dielectric material layer 7 in the upper surface of oxide 61, the sidewall of the first projection 51 and the sidewall of upper surface and 52 second projections and upper surface, form structural representation shown in Figure 14.
Finally, cover a gate material layers 8 on described high-k dielectric material layer 7, cover with on the mask layer of patterning and gate material layers 8, with the mask layer of patterning for mask, the upper surface of etching grid material layer to the second projection 52, forms FinFET semiconductor device of the present invention shown in Figure 1.
As a kind of preferred embodiment, the material of nitride is silicon nitride.
Can find out, the embodiment of this method is the elaboration of the preparation method to the FinFET semiconductor device that the present invention sets forth, therefore, disclosed in the embodiment of FinFET semiconductor device, technical characteristic remains valid in this method embodiment, equally, also effective in the embodiment of FinFET semiconductor device of the present invention in content disclosed in the embodiment of the preparation method of FinFET semiconductor device, do not repeat them here.
In sum, the present invention proposes a kind of FinFET semiconductor device and preparation method thereof, by the Semiconductor substrate providing a preparation to have the first projection and the second projection, prepare oxide skin(coating) successively, high K gusset material layer and gate material layers, preparation comprises Semiconductor substrate, the FinFET of high-k dielectric material layer and gate material layers, the technical program effect has prepared the grid comprising 4T-FinFET and 3T-FinFET, again two grids are combined simultaneously, effectively overcome traditional scheme and by with cmp, the grid on Fin top cannot be removed the rear problem being difficult to be integrated together by 4T-FinFET and 3T-FinFET, overcome simultaneously, by increasing by one light shield, the grid etch on the Fin top of specifying is fallen the problem brought to the alignment of photo.
Foregoing this invention related description is only limited to some examples; As long as possess the Conventional wisdom of this invention art, without the need to changing the technical thought of this invention or necessary feature, just this invention can be changed to other forms.Therefore, foregoing example contains any one example of this invention, is not limited only to the form in this specification.Such as, each inscape being defined as single type dispersibles enforcement; Equally, be defined as the inscape of dispersion, also can implement with combining form.
The category of this invention is not limited to above-mentioned detailed description, patent claim described after can containing; All changes of deriving from the definition of patent claim, scope and equivalent conception or change form and include in the category of this invention.
Claims (11)
1. a FinFET, is characterized in that, described FinFET comprises:
Preparation has the semiconductor base of the first projection and the second projection;
High-k dielectric material layer, on the upper surface being positioned at described Semiconductor substrate, covers the upper surface of described Semiconductor substrate, the upper surface of the first projection and the sidewall of side surface and the second projection;
Gate material layers, is positioned on described high-k dielectric material layer, and wherein, the upper surface of described gate material layers and the upper surface of described second projection are positioned at same level.
2. FinFET as claimed in claim 1, it is characterized in that, described FinFET also comprises:
Oxide skin(coating), between described high-k dielectric material layer and described semiconductor base.
3. FinFET as claimed in claim 2, it is characterized in that, the material of described oxide skin(coating) is silica.
4. FinFET as claimed in claim 1, it is characterized in that, the material of described semiconductor base is monocrystalline silicon.
5. FinFET as claimed in claim 1, it is characterized in that, the material of described high-k dielectric material layer is HfO2.
6. FinFET as claimed in claim 1, it is characterized in that, described gate material layers material is metal.
7. FinFET as claimed in claim 1, it is characterized in that, described gate material layers material is oxide.
8. a preparation method for FinFET, is characterized in that, described preparation method comprises:
Semi-conductive substrate is provided;
In Semiconductor substrate, prepare first protruding and the second projection, form semiconductor base;
In the region overlay monoxide layer except described first projection and described second projection of the upper surface of described semiconductor base;
Cover a high-k dielectric material layer in the sidewall of the sidewall of the upper surface of described oxide, described first projection and upper surface and described second projection and upper surface;
Prepare a gate material layers on the described high-k dielectric material layer removing the second protruding top, make the upper surface of the upper surface of described gate material layers and described second projection be positioned at same level.
9. preparation method as claimed in claim 8, is characterized in that, in described method, prepares the first step that is protruding and the second projection and also comprise in Semiconductor substrate:
A depression is prepared in Semiconductor substrate;
Cover mononitride layer on described first depression and described Semiconductor substrate, the nitride layer on described first depression and described Semiconductor substrate is in same level;
Adopt chemical mechanical milling tech, make the upper surface of nitride layer in described first depression and the upper surface of described Semiconductor substrate be positioned at same level;
Cover one first mask layer on described nitride layer, and cover one second mask layer on the upper surface not comprising the first sunk part of described Semiconductor substrate;
With the first mask layer and the second mask layer for grinding, etch downwards, the Semiconductor substrate to described first mask layer exposes preset height;
Remove the nitride layer below described first mask layer, described second mask layer and described first mask layer, form first protruding and the second projection.
10. preparation method as claimed in claim 9, is characterized in that, described nitride is silicon nitride.
11. preparation methods as claimed in claim 8, is characterized in that, in described method, the step that preparation gate material layers makes the upper surface of the upper surface of described gate material layers and described second projection be positioned at same level also comprises:
Cover a gate material layers on described high-k dielectric material layer;
Etching, removes the high K gusset material layer on described second upper convex surface and gate material layers.
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| CN201510662388.6A CN105226098B (en) | 2015-10-14 | 2015-10-14 | A kind of FinFET semiconductor devices and preparation method thereof |
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| CN201510662388.6A CN105226098B (en) | 2015-10-14 | 2015-10-14 | A kind of FinFET semiconductor devices and preparation method thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070259501A1 (en) * | 2006-05-05 | 2007-11-08 | Texas Instruments Incorporated | Integrating high performance and low power multi-gate devices |
| CN103871888A (en) * | 2012-12-18 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070259501A1 (en) * | 2006-05-05 | 2007-11-08 | Texas Instruments Incorporated | Integrating high performance and low power multi-gate devices |
| CN103871888A (en) * | 2012-12-18 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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