CN105224785A - A kind of quasi-periodicity spherical oscillator and circuit - Google Patents

Abstract

The present invention relates to a kind of nonlinear system, in particular to a kind of quasi-periodicity spherical oscillator and circuit, more common oscillator is period oscillator at present, chaotic oscillator can produce period oscillator under different parameters, also quasi-periodicity and chaotic oscillator can be produced, but the system only producing quasi-periodic oscillation device is not also found, the present invention shows and proposes a kind of quasi-periodicity spherical oscillator, increase the type of oscillator, for oscillator application in the many a kind of selections newly of engineering practice.

Description

A kind of quasi-periodicity spherical oscillator and circuit

Technical field

The present invention relates to a kind of nonlinear system, particularly a kind of quasi-periodicity spherical oscillator and circuit.

Background technology

More common oscillator is period oscillator at present, chaotic oscillator can produce period oscillator under different parameters, also quasi-periodicity and chaotic oscillator can be produced, but the system only producing quasi-periodic oscillation device is not also found, the present invention shows and proposes a kind of quasi-periodicity spherical oscillator, increase the type of oscillator, for oscillator application in the many a kind of selections newly of engineering practice.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of quasi-periodicity spherical oscillator and circuit, and the present invention adopts following technological means to realize goal of the invention:

1. a quasi-periodicity spherical oscillator, is characterized in that, comprise the following steps:

(1) following nonlinear system is considered:

$\left(\begin{array}{c}\stackrel{\·}{x}\\ \stackrel{\·}{y}\\ \stackrel{\·}{z}\end{array}\right)=\left(\begin{array}{c}f\left(x,y,z\right)\\ g\left(x,y,z\right)\\ h\left(x,y,z\right)\end{array}\right)+\left(\begin{array}{c}{C}_1\\ C_2\\ C_3\end{array}\right)---i$

C in formula ₁, C ₂, C ₃for constant;

(2) JacobianMatrix (Jacobi matrix) of i formula is:

$J=\left(\begin{array}{ccc}\frac{\∂f}{\∂x}& \frac{\∂f}{\∂y}& \frac{\∂f}{\∂z}\\ \frac{\∂g}{\∂x}& \frac{\∂g}{\∂y}& \frac{\∂g}{\∂z}\\ \frac{\∂h}{\∂x}& \frac{\∂h}{\∂y}& \frac{\∂h}{\∂z}\end{array}\right)---ii$

(3) when the Jacobi matrix in ii is:

$J=\left(\begin{array}{ccc}z& a& x\\ -a& z& y\\ -2bx& -2cy& -2dz\end{array}\right)$

System i is turned into

$\left\{\begin{array}{c}\stackrel{\·}{x}=ay+xz+C_1\\ \stackrel{\·}{y}=-ax+yz+C_2\\ \stackrel{\·}{z}=-{\mathrm{bx}}^2-{\mathrm{cy}}^2-{\mathrm{dz}}^2+C_3\end{array}\right.---iii$

Work as a=10, b=1/2, c=1/2, d=1/2, C ₃=2, C ₁=C ₂when=0, system is quasi-periodicity spherical oscillator.

2, a kind of quasi-periodicity spherical pierce circuit, it is characterized in that: according to the mathematical model iii constructing analog circuit of quasi-periodicity spherical oscillator chaos system, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance and electric capacity form anti-phase totalizer and anti-phase fractional order integrator, utilize multiplier U4. multiplier U5, multiplier U6, multiplier U7 and multiplier U8 realizes multiplying, direct supply V1 is utilized to realize constant inflow, described operational amplifier U1, operational amplifier U2 adopts LF347N, described multiplier U3 and multiplier U4 adopts AD633JN,

Described operational amplifier U1 concatenation operation amplifier U2, multiplier U4 and multiplier U7, described operational amplifier U2 concatenation operation amplifier U1, multiplier U5 and multiplier U8, described operational amplifier U3 connects multiplier U4, multiplier U5 and multiplier U6, described multiplier U4 concatenation operation amplifier U1, described multiplier U5 concatenation operation amplifier U2, described multiplier U6 concatenation operation amplifier U3, described multiplier U7 concatenation operation amplifier U3, described multiplier U8 concatenation operation amplifier U3;

The 1st of described operational amplifier U1, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R12, 7th pin meets output-x, connected with the 13rd pin of operational amplifier U2 by resistance R4, connect the 3rd pin of multiplier U7, 8th pin connects and exports x, connect the 1st pin of multiplier U4, connect the 1st pin of multiplier U7, connected with the 6th pin of operational amplifier U1 by resistance R11, 9th pin is connected with the 8th pin by electric capacity C1, 13rd pin is connected with the 14th pin by resistance R9, 14th pin is connected with 9 pins by resistance R10,

The 1st of described operational amplifier U2, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R14, 7th pin meets output-y, connect the 1st pin of multiplier U8, 8th pin connects and exports y, connect the 1st pin of multiplier U5, connect the 3rd pin of multiplier U8, connected with the 13rd pin of operational amplifier U1 by resistance R2, connected with the 6th pin of operational amplifier U2 by resistance R13, 9th pin is connected with the 8th pin by electric capacity C2, 13rd pin completes is crossed resistance R5 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R3,

The 1st of described operational amplifier U3, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R20, 7th pin meets output-z, connect the 1st pin of multiplier U6, 8th pin connects and exports z, connect the 3rd pin of multiplier U4, connect the 3rd pin of multiplier U5, connect the 3rd pin of multiplier U6, connected with the 6th pin of operational amplifier U3 by resistance R19, 9th pin is connected with the 8th pin by electric capacity C3, 13rd pin completes is crossed resistance R15 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R16

One end ground connection of described direct supply V1, the other end is connected with the 13rd pin of operational amplifier U3 by resistance R8;

The equal ground connection of 2nd, 4,6 pin of described multiplier U4, the 5th pin meets VEE, and the 7th pin connects operational amplifier U1 the 13rd pin by resistance R6, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U5, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance R17, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U6, the 5th pin meets VEE, and the 7th pin connects operational amplifier U3 the 13rd pin by resistance R1, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U7, the 5th pin meets VEE, and the 7th pin connects operational amplifier U3 the 13rd pin by resistance R18, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U8, the 5th pin meets VEE, and the 7th pin connects operational amplifier U3 the 13rd pin by resistance R7, and the 8th pin meets VCC.

The invention has the beneficial effects as follows: propose a kind of quasi-periodicity spherical oscillator and circuit, add type and the kind of oscillator, for oscillator application provides a kind of selection newly in engineering practice.

Accompanying drawing explanation

Fig. 1 is the 3-D view of the spherical oscillator that the present invention proposes.

Fig. 2 is the view of the x-z plane of the spherical oscillator that the present invention proposes.

Fig. 3 is the view of the y-z plane of the spherical oscillator that the present invention proposes.

Fig. 4 is the view of the x-y plane of the spherical oscillator that the present invention proposes.

Fig. 5 is circuit structure diagram of the present invention.

Fig. 6 is the circuit connection diagram of U1 and U4 of the present invention.

Fig. 7 is the circuit connection diagram of U2 and U5 of the present invention.

Fig. 8 is the circuit connection diagram of U3 and U6 of the present invention, U7 and U8.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 8.

1. a quasi-periodicity spherical oscillator, is characterized in that, comprise the following steps:

(1) following nonlinear system is considered:

$\left(\begin{array}{c}\stackrel{\·}{x}\\ \stackrel{\·}{y}\\ \stackrel{\·}{z}\end{array}\right)=\left(\begin{array}{c}f\left(x,y,z\right)\\ g\left(x,y,z\right)\\ h\left(x,y,z\right)\end{array}\right)+\left(\begin{array}{c}{C}_1\\ C_2\\ C_3\end{array}\right)---i$

C in formula ₁, C ₂, C ₃for constant;

(2) JacobianMatrix (Jacobi matrix) of i formula is:

$J=\left(\begin{array}{ccc}\frac{\∂f}{\∂x}& \frac{\∂f}{\∂y}& \frac{\∂f}{\∂z}\\ \frac{\∂g}{\∂x}& \frac{\∂g}{\∂y}& \frac{\∂g}{\∂z}\\ \frac{\∂h}{\∂x}& \frac{\∂h}{\∂y}& \frac{\∂h}{\∂z}\end{array}\right)---ii$

(3) when the Jacobi matrix in ii is:

$J=\left(\begin{array}{ccc}z& a& x\\ -a& z& y\\ -2bx& -2cy& -2dz\end{array}\right)$

System i is turned into

$\left\{\begin{array}{c}\stackrel{\·}{x}=ay+xz+C_1\\ \stackrel{\·}{y}=-ax+yz+C_2\\ \stackrel{\·}{z}=-{\mathrm{bx}}^2-{\mathrm{cy}}^2-{\mathrm{dz}}^2+C_3\end{array}\right.---iii$

Work as a=10, b=1/2, c=1/2, d=1/2, C ₃=2, C ₁=C ₂when=0, system is quasi-periodicity spherical oscillator.

2, a kind of quasi-periodicity spherical pierce circuit, it is characterized in that: according to the mathematical model iii constructing analog circuit of quasi-periodicity spherical oscillator chaos system, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance and electric capacity form anti-phase totalizer and anti-phase fractional order integrator, utilize multiplier U4. multiplier U5, multiplier U6, multiplier U7 and multiplier U8 realizes multiplying, direct supply V1 is utilized to realize constant inflow, described operational amplifier U1, operational amplifier U2 adopts LF347N, described multiplier U3 and multiplier U4 adopts AD633JN,

Described operational amplifier U1 concatenation operation amplifier U2, multiplier U4 and multiplier U7, described operational amplifier U2 concatenation operation amplifier U1, multiplier U5 and multiplier U8, described operational amplifier U3 connects multiplier U4, multiplier U5 and multiplier U6, described multiplier U4 concatenation operation amplifier U1, described multiplier U5 concatenation operation amplifier U2, described multiplier U6 concatenation operation amplifier U3, described multiplier U7 concatenation operation amplifier U3, described multiplier U8 concatenation operation amplifier U3;

The 1st of described operational amplifier U1, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R12, 7th pin meets output-x, connected with the 13rd pin of operational amplifier U2 by resistance R4, connect the 3rd pin of multiplier U7, 8th pin connects and exports x, connect the 1st pin of multiplier U4, connect the 1st pin of multiplier U7, connected with the 6th pin of operational amplifier U1 by resistance R11, 9th pin is connected with the 8th pin by electric capacity C1, 13rd pin is connected with the 14th pin by resistance R9, 14th pin is connected with 9 pins by resistance R10,

The 1st of described operational amplifier U2, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R14, 7th pin meets output-y, connect the 1st pin of multiplier U8, 8th pin connects and exports y, connect the 1st pin of multiplier U5, connect the 3rd pin of multiplier U8, connected with the 13rd pin of operational amplifier U1 by resistance R2, connected with the 6th pin of operational amplifier U2 by resistance R13, 9th pin is connected with the 8th pin by electric capacity C2, 13rd pin completes is crossed resistance R5 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R3,

The 1st of described operational amplifier U3, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R20, 7th pin meets output-z, connect the 1st pin of multiplier U6, 8th pin connects and exports z, connect the 3rd pin of multiplier U4, connect the 3rd pin of multiplier U5, connect the 3rd pin of multiplier U6, connected with the 6th pin of operational amplifier U3 by resistance R19, 9th pin is connected with the 8th pin by electric capacity C3, 13rd pin completes is crossed resistance R15 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R16

One end ground connection of described direct supply V1, the other end is connected with the 13rd pin of operational amplifier U3 by resistance R8;

The equal ground connection of 2nd, 4,6 pin of described multiplier U4, the 5th pin meets VEE, and the 7th pin connects operational amplifier U1 the 13rd pin by resistance R6, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U5, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance R17, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U6, the 5th pin meets VEE, and the 7th pin connects operational amplifier U3 the 13rd pin by resistance R1, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U7, the 5th pin meets VEE, and the 7th pin connects operational amplifier U3 the 13rd pin by resistance R18, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U8, the 5th pin meets VEE, and the 7th pin connects operational amplifier U3 the 13rd pin by resistance R7, and the 8th pin meets VCC.

Certainly, above-mentioned explanation is not limitation of the present invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.

Claims (2)

1. a quasi-periodicity spherical oscillator, is characterized in that, comprise the following steps:

(1) following nonlinear system is considered:

$\left(\begin{array}{c}\stackrel{\·}{x}\\ \stackrel{\·}{y}\\ \stackrel{\·}{z}\end{array}\right)=\left(\begin{array}{c}f\left(x,y,z\right)\\ g\left(x,y,z\right)\\ h\left(x,y,z\right)\end{array}\right)+\left(\begin{array}{c}{C}_1\\ C_2\\ C_3\end{array}\right)---i$

C in formula ₁, C ₂, C ₃for constant;

(2) JacobianMatrix (Jacobi matrix) of i formula is:

$J=\left(\begin{array}{ccc}\frac{\∂f}{\∂x}& \frac{\∂f}{\∂y}& \frac{\∂f}{\∂z}\\ \frac{\∂g}{\∂x}& \frac{\∂g}{\∂y}& \frac{\∂g}{\∂z}\\ \frac{\∂h}{\∂x}& \frac{\∂h}{\∂y}& \frac{\∂h}{\∂z}\end{array}\right)---ii$

(3) when the Jacobi matrix in ii is:

$J=\left(\begin{array}{ccc}z& a& x\\ -a& z& y\\ -2bx& -2cy& -2dz\end{array}\right)$

System i is turned into

$\left\{\begin{array}{c}\stackrel{\·}{x}=ay+xz+C_1\\ \stackrel{\·}{y}=-ax+yz+C_2\\ \stackrel{\·}{z}=-{\mathrm{bx}}^2-{\mathrm{cy}}^2-{\mathrm{dz}}^2+C_3\end{array}\right.---iii$

Work as a=10, b=1/2, c=1/2, d=1/2, C ₃=2, C ₁=C ₂when=0, system is quasi-periodicity spherical oscillator.

2. a quasi-periodicity spherical pierce circuit, it is characterized in that: according to the mathematical model iii constructing analog circuit of quasi-periodicity spherical oscillator chaos system, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance and electric capacity form anti-phase totalizer and anti-phase fractional order integrator, utilize multiplier U4. multiplier U5, multiplier U6, multiplier U7 and multiplier U8 realizes multiplying, direct supply V1 is utilized to realize constant inflow, described operational amplifier U1, operational amplifier U2 adopts LF347N, described multiplier U3 and multiplier U4 adopts AD633JN,

Described operational amplifier U1 concatenation operation amplifier U2, multiplier U4 and multiplier U7, described operational amplifier U2 concatenation operation amplifier U1, multiplier U5 and multiplier U8, described operational amplifier U3 connects multiplier U4, multiplier U5 and multiplier U6, described multiplier U4 concatenation operation amplifier U1, described multiplier U5 concatenation operation amplifier U2, described multiplier U6 concatenation operation amplifier U3, described multiplier U7 concatenation operation amplifier U3, described multiplier U8 concatenation operation amplifier U3;

The 1st of described operational amplifier U1, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R12, 7th pin meets output-x, connected with the 13rd pin of operational amplifier U2 by resistance R4, connect the 3rd pin of multiplier U7, 8th pin connects and exports x, connect the 1st pin of multiplier U4, connect the 1st pin of multiplier U7, connected with the 6th pin of operational amplifier U1 by resistance R11, 9th pin is connected with the 8th pin by electric capacity C1, 13rd pin is connected with the 14th pin by resistance R9, 14th pin is connected with 9 pins by resistance R10,

The 1st of described operational amplifier U2, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R14, 7th pin meets output-y, connect the 1st pin of multiplier U8, 8th pin connects and exports y, connect the 1st pin of multiplier U5, connect the 3rd pin of multiplier U8, connected with the 13rd pin of operational amplifier U1 by resistance R2, connected with the 6th pin of operational amplifier U2 by resistance R13, 9th pin is connected with the 8th pin by electric capacity C2, 13rd pin completes is crossed resistance R5 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R3,

The 1st of described operational amplifier U3, 2 pins are unsettled, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin is connected with the 7th pin by resistance R20, 7th pin meets output-z, connect the 1st pin of multiplier U6, 8th pin connects and exports z, connect the 3rd pin of multiplier U4, connect the 3rd pin of multiplier U5, connect the 3rd pin of multiplier U6, connected with the 6th pin of operational amplifier U3 by resistance R19, 9th pin is connected with the 8th pin by electric capacity C3, 13rd pin completes is crossed resistance R15 and is connected with the 14th pin, 14th pin is connected with the 9th pin by resistance R16

One end ground connection of described direct supply V1, the other end is connected with the 13rd pin of operational amplifier U3 by resistance R8;

The equal ground connection of 2nd, 4,6 pin of described multiplier U4, the 5th pin meets VEE, and the 7th pin connects operational amplifier U1 the 13rd pin by resistance R6, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U5, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance R17, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U6, the 5th pin meets VEE, and the 7th pin connects operational amplifier U3 the 13rd pin by resistance R1, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U7, the 5th pin meets VEE, and the 7th pin connects operational amplifier U3 the 13rd pin by resistance R18, and the 8th pin meets VCC;

The equal ground connection of 2nd, 4,6 pin of described multiplier U8, the 5th pin meets VEE, and the 7th pin connects operational amplifier U3 the 13rd pin by resistance R7, and the 8th pin meets VCC.