CN105206294B - Semiconductor memory system - Google Patents
Semiconductor memory system Download PDFInfo
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- CN105206294B CN105206294B CN201410260200.0A CN201410260200A CN105206294B CN 105206294 B CN105206294 B CN 105206294B CN 201410260200 A CN201410260200 A CN 201410260200A CN 105206294 B CN105206294 B CN 105206294B
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Abstract
The invention provides a kind of semiconductor memory system, including multiple induction amplifiers, multigroup main data line section and multiple memory segments.Multigroup main data line section is arranged with column direction.Each memory segments include multiple memory cells, and each memory segments are coupled to main data line section corresponding to one group via induction amplifier corresponding to one, and adjacent corresponding main data line section is coupled against each other.When accessing memory data, memory data is stated by uploading to serve in multigroup corresponding main data line section of interconnection.The semiconductor memory system of the present invention can reduce coiling, and effectively reduce chip area and manufacturing expense.
Description
Technical field
The invention relates to integrated circuit, espespecially semiconductor memory system.
Background technology
Current almost all of electronic installation all can be used for data storage including certain memory.Memory is generally partly to lead
Body hardware realizes that many kinds of modern electronics use memory, and embodiment may include, but be not limited to DRAM.
Due to needing to store mass data, traditional memory will use a large amount of coilings to carry out data access.
The content of the invention
Present invention aims at a kind of semiconductor memory system is provided, will be used greatly with solving above-mentioned legacy memory
Measure the problem of coiling carries out data access.
Based on above-mentioned purpose, disclosed herein a kind of semiconductor memory system, including it is multiple induction amplifiers, multigroup
Main data line section and multiple memory segments.Multigroup main data line section is arranged with column direction.Each memory segments
Including multiple memory cells, each memory segments are coupled to master data corresponding to one group via induction amplifier corresponding to one
Line section, and adjacent corresponding main data line section are coupled against each other.When accessing memory data, by interconnection
This it is multigroup corresponding to main data line section upload to serve and state memory data.
The present invention is it is also disclosed that a kind of semiconductor memory system, including multiple I/O ports, a universe data are confluxed
Row and multiple thesaurus.The universe data bus-bar is connected to above-mentioned multiple I/O ports to access above-mentioned memory number
According to.Each thesaurus includes multiple induction amplifiers, multigroup main data line section and multiple memory segments.Multigroup master
Data wire section is arranged with column direction.Each memory segments include multiple memory cells, and each memory segments are via one
Corresponding induction amplifier is coupled to main data line section corresponding to one group, and adjacent corresponding main data line section is coupled against each other,
And one of which main data line section couples above-mentioned universe data bus-bar.When accessing memory data, by mutual
Multigroup corresponding main data line section of connection, which uploads to serve, states memory data.
The semiconductor memory system of the present invention can reduce coiling, and effectively reduce chip area and manufacturing expense.
Brief description of the drawings
Fig. 1 is to show a kind of schematic diagram of semiconductor memory 1 in the embodiment of the present invention.
Fig. 2 is to show a kind of schematic diagram of memory segments 2 in the embodiment of the present invention.
Fig. 3 is to show schematic diagram of another memory segments 3 in read operation in the embodiment of the present invention.
Fig. 4 is to show schematic diagram of another memory segments 4 in write operation in the embodiment of the present invention.
Symbol description：
1~semiconductor memory；
2nd, 3,4~memory segments；
10~DQ data contacts；
12~universe data bus-bar；
140th, 141 ..., 147~thesaurus；
1420th, 1422 ..., 1438, SA~induction amplifier；
1421st, 1423 ..., 1437, seg~memory segments；
..., 1,447 1440th, 1442~local main data line；
16~director data contact；
180th, 182,184,186, SSA~secondary induction amplifier；
190th, 192~row control line；
30th, 34~read-out amplifier；
32nd, 36~write driver；
382nd, 380~memory segments.
CSL~row control line；
MDQ/bMDQ~main data line；
MDQ0/bMDQ0、MDQ1/bMDQ1~local main data line；
Seg~memory segments.
Embodiment
It should be noted that, different embodiments or example proposed in lower disclosure, it is herein to illustrate this
The disclosed different technologies feature of invention, particular example or arrangement described by it are to simplify the present invention, so be not used to limit
The fixed present invention.In addition, may reuse identical reference numeral and symbol in different embodiments or example, these repeat to make
Reference numeral and symbol are to illustrate disclosed content, and are not used to represent between different embodiments or example
Relation.
Fig. 1 is to show a kind of schematic diagram of semiconductor memory 1 in the embodiment of the present invention, including DQ data contacts 10, one
Universe data bus-bar 12, multiple thesaurus (memory bank) 140,141 ..., 147 and director data contact 16.DQ
Data contacts 10 couple universe data bus-bar 12 and multiple thesaurus 140 arrive thesaurus 147, and multiple thesaurus 140 are to depositing
Bank 147 is also coupled to director data contact 16.
DQ data contacts 10 include multiple memory data contacts, and memory data is ingressed and egressed out by DQ data contacts 10
Semiconductor memory 1.Director data contact 16 includes multiple instruction data contacts, for receiving director data, such as write-in or
Receive instruction.Director data contact 16 couples thesaurus 140 and arrives thesaurus 147, to control thesaurus 140 to arrive thesaurus 147
Carry out digital independent, write-in or other data processings.
The each thesaurus into thesaurus 147 of thesaurus 140 includes multiple memory cells (not shown), for storing
Memory data, respectively using the bit line (bit lines) (not shown) and wordline (word lines) for representing row C and row R
(not shown) starts or closes memory cell, so in controlling memory data access.In addition, each thesaurus wraps
Multiple row is included, each column there are a pair of main data line (master data line) MDQ/bMDQ and row control line CSL (not shown).Example
Such as, each thesaurus may include 128 row.Fig. 2 shows a part for a row in Fig. 1 thesaurus.
Main data line MDQ/bMDQ is a kind of data line, is passed through by the way that secondary induction amplifier is (not shown) along row
All adjacent thesaurus in direction, for transmitting thesaurus 140 to the memory data in thesaurus 147.For example, left side
Thesaurus 140 passes through access thesaurus by main data line MDQ/bMDQ to thesaurus 143 by corresponding secondary induction amplifier
140 arrive thesaurus 147 also by data main data line MDQ/ to the memory cell in thesaurus 143, the thesaurus 144 of right side
The memory cell that bMDQ is arrived in thesaurus 147 by corresponding secondary induction amplifier through access thesaurus 144.Every master
Data wire MDQ/bMDQ transmits memory data in universe data bus-bar 12 and thesaurus 140 between thesaurus 147.Master data
Line MDQ/bMDQ is a pair of data lines MDQ and bMDQ.In certain embodiments, when memory cell leaves unused, main data line pair
Both MDQ and bMDQ are all logic " HIGH "；Logic is read when write-in memory cell logic " HIGH " or by memory cell
When " HIGH ", main data line MDQ is logic " HIGH " and main data line bMDQ is logic " LOW "；When write-in memory cell is patrolled
When collecting " LOW " or reading logic " LOW " by memory cell, main data line MDQ is logic " LOW " and main data line bMDQ is to patrol
Collect " HIGH ".
Each thesaurus is controlled by a plurality of special row control line CSL in addition, carries row control signal above, for respectively
Control the enable (enablement) of the particular column of particular memory bank or except energy (disablement).When row control signal enable
During the particular column of particular memory bank, then the memory cell in the particular column of the particular memory bank can be accessed.When row control
When signal removes the particular column of energy particular memory bank, then the memory cell in the particular column of the particular memory bank will not be deposited
Take.Each data access all only understands the particular column of one particular memory bank of enable.For example, work as row control signal enable thesaurus
During 143 the 1st row, the 1st row that thesaurus 140 to thesaurus 142, thesaurus 144 arrive thesaurus 147 all can be by its special row
Control signal removes energy.Therefore, now the memory cell of only the 1st row of thesaurus 143 can pass through main data line MDQ/bMDQ
Access.
Multiple thesaurus 140 are directly connected to universe data bus-bar to thesaurus 147 by main data line MDQ/bMDQ
12.Universe data bus-bar 12 is connected to DQ data contacts 10.All memory datas can all pass through in semiconductor memory 1
Universe data bus-bar 12 and enter line access.
In Fig. 1, left side thesaurus 140 is only distinguished to thesaurus 143 and right side thesaurus 144 to thesaurus 147
Two main data line MDQ/bMDQ are shown, the adjacent thesaurus of each one side of something has a plurality of main data line MDQ/bMDQ to pass through in implementation
Corresponding secondary induction amplifier longitudinally through.When reading data, by the storage in each memory cell in thesaurus
Device data are conveyed directly to universe data bus-bar by a plurality of main data line MDQ/bMDQ and corresponding secondary induction amplifier
12 are exported by DQ data contacts 10；When writing data, a plurality of main data line MDQ/bMDQ is passed through by universe data bus-bar 12
Each memory cell that memory data is conveyed directly in thesaurus with corresponding secondary induction amplifier stores.
Due to semiconductor memory 1 by the main data line MDQ/bMDQ through all adjacent thesaurus directly by memory
Data transmit between thesaurus and universe data bus-bar 12, thus can reduce between thesaurus and universe data bus-bar 12 around
Line and coiling area, effectively reduce the manufacturing expense of semiconductor memory.
Fig. 2 shows the schematic diagram of a memory segments 2 in the embodiment of the present invention, includes the same column of two thesaurus, its
Including multiple induction amplifiers (SA) 1420,1422 ..., 1438, multigroup main data line section, multiple memory segments
(memory segment) 1421,1423 ..., 1437, row control line (CSL) 190 and 192 and secondary induction amplifier
(SSA) 180,182,184 and 186.Wherein, multiple induction amplifiers 1420,1422 ..., 1428, multigroup main data line section,
Multiple memory segments 1421,1423 ..., 1427, secondary induction amplifier 180 and 182 and row control line 190 belong to
Half portion thesaurus；Multiple induction amplifiers 1430,1432 ..., 1438, multigroup main data line section, multiple memory segments
1431st, 1433 ..., 1437, secondary induction amplifier 184 and 186 and row control line 192 belong to lower half thesaurus.
Referring first to lower half thesaurus, main data line MDQ/bMDQ is arranged with column direction, based on the data wire on the left side
Data wire MDQ, the data wire on the right is main data line bMDQ, and main data line MDQ/bMDQ includes multigroup main data line section.Often
Group main data line section includes two local main data lines, and (diagram only illustrates corresponding using lower half main data line section as example
Local main data line 1440 arrives local main data line 1447).Thesaurus can drive (re-driver) mould with inductive mode or again
Formula operates.Under inductive mode, main data line MDQ/bMDQ is loaded with one group of differential wave；Under weight drive pattern, main data line
MDQ/bMDQ one is loaded with the data-signal for being delivered to adjacent thesaurus.Each memory segments 1431,1433 ..., 1437
Including multiple memory cells (not shown), the memory cell is used to store memory data.Each memory segments via
Induction amplifier corresponding to one is coupled to main data line section corresponding to one group, and every two groups adjacent corresponding main data line sections are mutual
Mutually couple.The main data line through all adjacent thesaurus is just formed after all adjacent main data line sections are coupled
MDQ/bMDQ, between the memory cell of each thesaurus and universe data bus-bar 12 as the data road directly transmitted
Footpath.By taking memory segments 1435 as an example, memory segments 1435 couple corresponding part by corresponding induction amplifier 1436
Main data line 1444 and 1445, and adjacent local main data line 1442,1444 and 1446 is coupled against each other, and adjacent part
Main data line 1443,1445 and 1447 is coupled against each other.When all adjacent local main data lines 1440,1442,1444 and 1446,
And the local main data line of other thesaurus be coupled after will be main data line MDQ.When all main numbers of adjacent part
Will be main data line after being coupled according to the local main data line of line 1441,1443,1445 and 1447, and other thesaurus
bMDQ.Main data line MDQ/bMDQ is used to be directly connected to universe data bus-bar 12 and is directly accessed each storage run through
Device section.
In certain embodiments, adjacent local main data line can be coupled against each other by induction amplifier.With memory areas
Exemplified by section 1435, adjacent local main data line 1442 and 1444 and 1444 and 1446 passes through the He of induction amplifier 1434 respectively
1436 are coupled against each other；And adjacent local main data line 1443 and 1445 and 1445 and 1447 passes through induction amplifier respectively
1434 and 1436 are coupled against each other.
As described in prior figures 1, each row of each thesaurus respectively have exclusive row control line, above with row control letter
Number, all memory cells on row for controlling the thesaurus respectively.When depositing for the row position for accessing Fig. 2 lower half thesaurus
, can be by all memory cells on the row position of the enable lower half thesaurus of row control line 192 during memory data, and directly lead to
Cross main data line MDQ and bMDQ and access multiple memory cells.For example, when writing lower half thesaurus data, to be write
Memory data can enter universe data bus-bar 12 by DQ data contacts 10, pass through the enable memory segments of row control line 192
1431 arrive memory segments 1437, by row control line 190 except energy memory segments 1421 arrive memory segments 1427, pass through word
Line and bit line, which start, will write memory segments 1431 to the memory cell in memory segments 1437, and by mutual coupling
The main data line MDQ and bMDQ and secondary induction amplifier 180 that the local main data line connect is formed arrive secondary induction amplifier
186 directly write above-mentioned memory data from universe data bus-bar 12 memory cell started.Deposited when reading lower half
During library data, memory segments 2 can arrive memory segments 1437 by the enable memory segments 1431 of row control line 192, lead to
Row control line 190 is crossed except energy memory segments 1421 arrive memory segments 1427, storage will be read by starting by wordline and bit line
Device section 1431 arrives the memory cell of memory segments 1437, and by being formed in the local main data line being coupled against each other
The memory cell of main data line MDQ and bMDQ and secondary induction amplifier 180 to secondary induction amplifier 186 from startup is read
Memory data, finally it is directly sent to universe data bus-bar 12 and is exported by DQ data contacts 10.
Fig. 3 is to show schematic diagram of another memory segments 3 in read operation in the embodiment of the present invention, including is read
Amplifier 30 (induction amplifier), write driver 32, read-out amplifier 34 (induction amplifier), write driver 36 and
Memory segments 380 and 382.
Read-out amplifier 30 and 34 can use inductive mode or drive (re-driver) mode operating again, and can incite somebody to action
The analog memory data of input switch to digital memory data.When use feeling answers mode operating, read-out amplifier can be from right
The memory segments answered read analog memory data via two local main data lines, and the memory data read is changed
For digital memory data, the digital memory data is transmitted from one of two local main data lines of next stage.Work as use
During weight drive pattern running, read-out amplifier only can read analog memory number from one of above-mentioned two local main data lines
According to, and the digital memory data read is strengthened or is directly sent to one of two local main data lines of next stage, or directly give
To universe data bus-bar 12.
For example, when reading data in by memory segments 382, read-out amplifier 34 is operated with inductive mode, from storage
Device section 382 is via local main data line MDQ0And bMDQ0Analog memory data are read, and the memory data read is turned
Digital memory data is changed to, and only from the local main data line MDQ of next stage1The digital memory data is transmitted by adjacent
Memory segments 380 are sent to next stage read-out amplifier 30.Read-out amplifier 30 is operated with weight drive pattern, only from local master
Data wire MDQ1Digital memory data is read, and the digital memory data read is strengthened and is directly sent to the remittance of universe data
Stream row 12.
Fig. 4 shows schematic diagram of another memory segments 4 in write operation in the embodiment of the present invention, including reads and put
Big device 30 (induction amplifier), write driver 32, read-out amplifier 34 (induction amplifier), write driver 36, Yi Jicun
Reservoir section 380 and 382.
Write driver 32 can use write mode or weight drive pattern to operate, and can be by the digital storage of input
Data switch to analog memory data.When being operated using write mode, write driver is converted to digital memory data
Analog memory data, and write memory segments by two local main data lines.When being operated using weight drive pattern, write-in
Driver only can read digital memory data, and the digital storage that will be read from one of above-mentioned two local main data lines
One of two local main data lines of next stage are strengthened or be directly sent to data.
For example, during memory segments 382 to be write data to, write driver 32 is operated with weight drive pattern, from universe
Data bus-bar 12 reads digital memory data, and only by local main data line bMDQ1Transfer data to next stage write-in
Driver 36.Write driver 36 is operated with write mode, digital memory data is converted into analog memory data, and lead to
Cross two local main data line MDQ0And bMDQ0Data are stored in corresponding memory segments 382 simultaneously.
Fig. 3 and Fig. 4 are refer to, in certain embodiments, the heavy drive pattern of read-out amplifier and write driver is not with
Same main data line MDQ and bMDQ output.Such as the heavy drive pattern of read-out amplifier is only exported using main data line MDQ；Write
The heavy drive pattern for entering driver is only exported using main data line bMDQ.
The operation of various logic section, module, unit and circuit that the present invention describes and function can utilize circuit
Hardware or embedded software code are realized that the embedded software code can be accessed and performed by a processor.
Though the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention, the technology of any this area
Personnel, without departing from the spirit and scope of the present invention, when a little change and retouching, therefore protection scope of the present invention can be done
When the scope defined depending on appended claim is defined.
Claims (7)
1. a kind of semiconductor memory system, it is characterised in that the semiconductor memory system includes：
Multiple induction amplifiers；
Multigroup main data line section, is arranged with column direction；And
Multiple memory segments, wherein each memory segments include multiple memory cells, each memory segments are via one
Corresponding induction amplifier is coupled to main data line section corresponding to one group, and the adjacent corresponding mutual coupling of main data line section
Connect；
Wherein, when accessing memory data, by being transmitted on multigroup corresponding main data line section of interconnection
The memory data；
The adjacent corresponding main data line section is coupled against each other by the intersegmental induction amplifier in adjacent memory areas；
Main data line section corresponding to every group includes two local main data lines；And
When being read, the corresponding induction amplifiers of the memory segments not being read is by from two parts
One of main data line transmits the memory data.
2. semiconductor memory system as claimed in claim 1, it is characterised in that described semiconductor memory system also wraps
Include：
Multiple write drivers；
Wherein each memory segments are coupled to main data line section corresponding to one group via write driver corresponding to one；It is described
Adjacent corresponding main data line section is coupled against each other by the intersegmental said write driver in adjacent memory areas；And
When carrying out write operation, the corresponding write drivers of the memory segments being not written into is by from two parts
Another of main data line transmits the memory data.
3. semiconductor memory system as claimed in claim 1, it is characterised in that described semiconductor memory system also wraps
Include：
Multiple I/O mouths；
One universe data bus-bar, for being connected to the multiple I/O mouth to access the memory data；
Wherein, one of which main data line section is coupled to the universe data bus-bar.
4. semiconductor memory system as claimed in claim 1, it is characterised in that described semiconductor memory system also wraps
Include：
Multiple thesaurus, wherein each thesaurus includes the multiple induction amplifier, multigroup main data line section, described
Multiple memory segments and a row control line；
Wherein, all the multiple memory segments that the row control line is run through in each thesaurus with column direction；
When accessing the memory data from one of the multiple thesaurus, its described row control line can be opened, and other
The row control line of remaining the multiple thesaurus can close.
5. a kind of semiconductor memory system, it is characterised in that the semiconductor memory system includes：
Multiple I/O mouths；
One universe data bus-bar, for being connected to the multiple I/O mouth to access memory data；
Multiple thesaurus, each thesaurus include；
Multiple induction amplifiers；
Multigroup main data line section, is arranged with column direction；And
Multiple memory segments, wherein each memory segments include multiple memory cells, each memory segments are via one
Corresponding induction amplifier is coupled to main data line section corresponding to one group, and adjacent corresponding main data line section is coupled against each other,
And one of which main data line section couples the universe data bus-bar；
Wherein, when accessing the memory data, uploaded by multigroup corresponding main data line section in interconnection
Send the memory data；
The adjacent corresponding main data line section passes through the intersegmental mutual coupling of the induction amplifier in adjacent memory areas
Connect；
Main data line section corresponding to every group includes two local main data lines；And
When being read, the corresponding induction amplifiers of the memory segments not being read is by from two parts
One of main data line transmits the memory data.
6. semiconductor memory system as claimed in claim 5, it is characterised in that described semiconductor memory system also wraps
Include：
Multiple write drivers；
Wherein described each memory segments are coupled to main data line corresponding to one group via the pair of write driver answered
Section；
The adjacent corresponding main data line section is mutual by the intersegmental said write driver in the adjacent memory areas
Coupling；And
When carrying out write operation, the corresponding write drivers of the memory segments being not written into is by from two parts
Another of main data line transmits the memory data.
7. semiconductor memory system as claimed in claim 5, it is characterised in that
Each thesaurus also includes a row control line, all the multiple storages run through with column direction in each thesaurus
Device section；And
When accessing the memory data from one of the multiple thesaurus, its described row control line can be opened, and other
The row control line of remaining the multiple thesaurus can close.
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| CN201410260200.0A CN105206294B (en) | 2014-06-12 | 2014-06-12 | Semiconductor memory system |
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|---|---|---|---|
| CN201410260200.0A CN105206294B (en) | 2014-06-12 | 2014-06-12 | Semiconductor memory system |
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| CN105206294B true CN105206294B (en) | 2018-01-05 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5949732A (en) * | 1997-09-11 | 1999-09-07 | International Business Machines Corporation | Method of structuring a multi-bank DRAM into a hierarchical column select line architecture |
| CN103680632A (en) * | 2012-08-30 | 2014-03-26 | 华邦电子股份有限公司 | Semiconductor memory device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002176153A (en) * | 2000-12-05 | 2002-06-21 | Fujitsu Ltd | Semiconductor storage device |
| KR100605600B1 (en) * | 2004-07-27 | 2006-07-28 | 주식회사 하이닉스반도체 | Semiconductor memory device |
-
2014
- 2014-06-12 CN CN201410260200.0A patent/CN105206294B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5949732A (en) * | 1997-09-11 | 1999-09-07 | International Business Machines Corporation | Method of structuring a multi-bank DRAM into a hierarchical column select line architecture |
| CN103680632A (en) * | 2012-08-30 | 2014-03-26 | 华邦电子股份有限公司 | Semiconductor memory device |
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