CN1051892C - Signal pick-up device without power supply - Google Patents
Signal pick-up device without power supply Download PDFInfo
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- CN1051892C CN1051892C CN93108705A CN93108705A CN1051892C CN 1051892 C CN1051892 C CN 1051892C CN 93108705 A CN93108705 A CN 93108705A CN 93108705 A CN93108705 A CN 93108705A CN 1051892 C CN1051892 C CN 1051892C
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Abstract
The present invention relates to a signal pick-up device without an external power supply. A mixed signal at least comprising a first signal and a second signal is used as a power supply to approximately completely pick up the first signal or the second signal, and the signal pick-up device has the function of impedance match so that the mixed signal can not be distorted when a circuit is switched on. In addition, the signal pick-up device uses the mixed signal to generate direct current signals, the external power supply is not needed, and electric power consumption can be saved.
Description
The present invention relates to a kind of signal pick-up device, particularly relate to a kind of signal pick-up device that need not additional power source.
Now aspect applications of electronic circuitry, often must use a kind of signal extracting circuit, so that a signal in the mixed signal that comprises a plurality of signals is separated output.For example in display control circuit, level and vertical synchronizing signal are mixed into mixed signal in advance and are imported by single cable sometimes, just must have this moment a demultiplexing circuit wherein level separate with vertical synchronizing signal, for this control circuit use.
Fig. 1 is the circuit diagram (about 1990-1993, this circuit generally is used for various displays on the market, for example Acer View 35A, the AcerView 7056I etc. in Acer's computer) of a known circuit.Signal 111 is the mixed signal ((H+V)-SYNC) of display horizontal-drive signal (H-SYNC) and vertical synchronizing signal (V-SYNC).See also the sequential chart of Fig. 2, wherein signal 211 and 212 is respectively original level and vertical synchronizing signal.Signal 111 input exclusive-OR gate G1, because of another input remains on 0, so its output signal 112 is identical with signal 111, but this signal 112 has the magnitude of voltage of TTL (transistor-transistor logic circuit), and actuating force is strengthened.G1 also separates signal 111 and resistance capacitance subsequently on the other hand, to avoid signal 111 distortions.Signal 112 causes signal 113 as shown in Figure 2 after the low-pass filtering of resistance-capacitance circuit R11, R12 and C11.Signal 113 is the low frequency envelope of signal 112, and is approaching with vertical synchronizing signal 212.Because of signal 113 through discharging and recharging and resistance and condensance load dividing potential drop, its rise time and fall time are all long than signal 212, amplitude also reduces simultaneously, so need an exclusive-OR gate G2, the input of this G2 also remains 0, therefore, G2 output end signal 114 is identical with the binary bit value of signal 113, but signal 114 has had the magnitude of voltage of TTL, and preferable rising and fall time are arranged, and is almost identical with signal 212.G1 and G2 be available or door replacement at this, no matter but use any logical circuit, additional power source supply (Vcc is generally 5V) all need be arranged, promptly must consume extra electric energy.
The object of the present invention is to provide a kind of signal pick-up device, the power supply supply that this device need not add, thus can save power consumption.
For achieving the above object, the invention provides a kind of no additional power source formula signal pick-up device, it comprises:
One filter has first input end, and this filter first input end is thus imported a mixed signal to produce a filtering signal, and described mixed signal comprises at least one first signal and a secondary signal;
One signal amplifying apparatus has second input, and this signal amplifying apparatus second input is thus imported described filtering signal and this filtering signal is amplified, to produce an amplifying signal;
One direct current device for generating voltage has the 3rd input, and this direct voltage generation device the 3rd input is thus imported described mixed signal, to produce a direct current voltage signal, uses for described signal amplifying apparatus;
One output device has four-input terminal, and this output device four-input terminal is thus imported described amplifying signal, is the described first signal amplified output signal to produce one.
No additional power source formula signal pick-up device of the present invention is described by an embodiment below in conjunction with accompanying drawing.In the accompanying drawing
Fig. 1 is the line map of known signal pick-up device;
Fig. 2 is the sequential chart of the known circuit of Fig. 1;
Fig. 3 does not have the line map of additional power source formula signal pick-up device one embodiment for the present invention;
Fig. 4 is the sequential chart of Fig. 3 circuit.
Fig. 3 illustrates the line map of a preferred embodiment of the present invention.System 30 one is applied to isolate the device of vertical synchronizing signal.See also the sequential chart of Fig. 4.Signal 111 in signal 311 and the prior art shown in Figure 1 is all (H+V)-SYNC signal.High resistance R31 and C31 form a low-pass filter circuit, so signal 312 is the envelope than the vertical signal of low frequency.Positive-negative-positive bipolar transistor Q5, resistance R 36 and capacitor C 32 form a direct current voltage generation circuit.The emitter acknowledge(ment) signal 311 of Q5, in signal 311 conducting and make the C32 charging during for high voltage, signal 314 is a direct current voltage, use in the time of can working for positive-negative-positive bipolar transistor Q1.Resistance R 36 is coupled between the base stage and ground of Q5, flows through the electric current of Q5 emitter and collector with restriction, reduces signal 311 distortions as far as possible.Signal 312 is connected to the base stage of positive-negative-positive bipolar transistor Q1, forms signal 315 at its collector electrode after the anti-phase amplification of Q1.Signal 315 is received the base stage of PNP transistor Q2 again, and Q2 is an emitter follower at this, in order to strengthen the actuating force of signal 315.PNP transistor Q3 and NPN transistor Q4 form an output-stage circuit.At signal 315 when low, Q2 and Q3 conducting, signal 311 electric currents just charge into capacitor C 33 through Q3, this moment, Q4 was obstructed and Q3 is saturated, so C33 can be charged to approximately with the same peak value of signal 311 and keep this value.When signal 315 rises to high voltage, all obstructed and Q4 conducting of Q2, Q3, this moment, C33 promptly was discharged to ground by Q4, and can be put into 0 volt.Signal 317 promptly forms the pulse as former vertical synchronizing signal thus.The configuration of Q3 and Q4 can be described as the dynamic type impedance matching circuit.The base stage of Q3 is received on the delay circuit of being made up of resistance R 37 and capacitor C 34 in addition, and elongated the turn-on time of Q3, and promptly the closing speed of Q3 slows down, to reduce signal 311 distortions.Resistance R 32, R33, R34 and R35 all make bias voltage and use.
Present embodiment does not need any power supply that adds, and only needs signal 311 to get final product work greater than a particular value (being about the potential difference of two diodes at this, promptly 1.4 volts).The input of each coupled signal 311 all has high impedance (being little electric current) in addition, therefore can make the distortion level of original signal 311 reduce to minimum.Because the output stage of dynamic type impedance matching is arranged, the vertical synchronizing signal of taking-up more is tending towards complete square wave simultaneously.
Below only explained the present invention, but persons skilled in the art can be made a little modifications within the scope of the present invention, so all should be within protection range of the present invention with an embodiment.
Claims (8)
1. no additional power source formula signal pick-up device is characterized in that comprising:
One filter has first input end, and this filter first input end is thus imported a mixed signal to produce a filtering signal, and described mixed signal comprises at least one first signal and a secondary signal;
One signal amplifying apparatus has second input, and this signal amplifying apparatus second input is thus imported described filtering signal and this filtering signal is amplified, to produce an amplifying signal;
One direct current device for generating voltage has the 3rd input, and this direct voltage generation device the 3rd input is thus imported described mixed signal, to produce a direct current voltage signal, uses for described signal amplifying apparatus;
One output device has four-input terminal, and this output device four-input terminal is thus imported described amplifying signal, is the described first signal amplified output signal to produce one.
2. signal pick-up device as claimed in claim 1, it is characterized in that, described output device also has the 5th input to import described mixed signal, the 5th input has high input impedance during for high voltage at described amplifying signal, and has low input impedance during for low-voltage at this amplifying signal.
3. signal pick-up device as claimed in claim 1 or 2 is characterized in that, described output device comprises a positive-negative-positive bipolar transistor and a NPN type two-stage transistor.
4. signal pick-up device as claimed in claim 1 or 2 is characterized in that, described first input end and the 3rd input all have high input impedance.
5. signal pick-up device as claimed in claim 1 or 2 is characterized in that, described filter is a resistance-capacitance circuit.
6. signal pick-up device as claimed in claim 1 or 2 is characterized in that, described mixed signal comprises a horizontal-drive signal and a vertical synchronizing signal.
7. signal pick-up device as claimed in claim 1 or 2 is characterized in that, the horizontal-drive signal of described first signal for using for display, and the vertical synchronizing signal of described secondary signal for using for this display.
8. signal pick-up device as claimed in claim 1 or 2 is characterized in that the amplitude of described mixed signal is greater than 1.4 volts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN93108705A CN1051892C (en) | 1993-07-20 | 1993-07-20 | Signal pick-up device without power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN93108705A CN1051892C (en) | 1993-07-20 | 1993-07-20 | Signal pick-up device without power supply |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1097916A CN1097916A (en) | 1995-01-25 |
| CN1051892C true CN1051892C (en) | 2000-04-26 |
Family
ID=4987274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN93108705A Expired - Fee Related CN1051892C (en) | 1993-07-20 | 1993-07-20 | Signal pick-up device without power supply |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1051892C (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4491146A (en) * | 1982-09-22 | 1985-01-01 | Groen Division/Dover Corporation | Liquid level control |
-
1993
- 1993-07-20 CN CN93108705A patent/CN1051892C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4491146A (en) * | 1982-09-22 | 1985-01-01 | Groen Division/Dover Corporation | Liquid level control |
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| Publication number | Publication date |
|---|---|
| CN1097916A (en) | 1995-01-25 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20000426 Termination date: 20100720 |