CN1051879C

CN1051879C - Double-layered polycrystal CMOS hybrid digital-analog integrated circuit and its manufacture

Info

Publication number: CN1051879C
Application number: CN97106765A
Authority: CN
Inventors: 王剑峰; 葛蔚明; 陈学良
Original assignee: Shanghai Institute of Metallurgy of CAS
Current assignee: Shanghai Institute of Optics and Fine Mechanics of CAS
Priority date: 1997-12-08
Filing date: 1997-12-08
Publication date: 2000-04-26
Anticipated expiration: 2017-12-08
Also published as: CN1190257A

Abstract

The present invention relates to a double-layer polycrystal CMOS digital-analog hybrid integrated circuit and a manufacturing method thereof. On the basis of a common CMOS process, a digital circuit and an analog circuit are simultaneously integrated on an integrated circuit by double-layer polysilicon to manufacture a resistor with desired resistance and an upper electrode of a capacitor. Thus, the double-layer polycrystal CMOS digital-analog hybrid integrated circuit of the present invention comprises a semiconductor substrate which is basically in a first conduction type, and a part of surface is provided with some surface layers in a second conduction type. Some channels are arranged on the surface in the first conduction type, and are MOS transistors in the second conduction type. Some thick insulating objects are used for covering the local surface of the semiconductor substrate, and resistors and capacitors are arranged on the thick insulating objects.

Description

Double level polysilicon CMOS hybrid digital-analog integrated circuit and manufacture method thereof

The present invention relates to a kind of digital-analog mixed CMOS integrated circuit and manufacture method thereof.

The development of very large scale integration technology can be integrated into increasing system digits circuit function on the integrated circuit, and the analog circuit function of system also is integrated on the integrated circuit simultaneously.Hybrid digital-analog integrated circuit is more and more causing people's attention.The CMOS integrated circuit technique is indubitable as the milestone of integrated circuit technique development, and it also has digital circuit and the simultaneously integrated potentiality of analog circuit.But common the sort of single level polysilicon CMOS integrated circuit fabrication process also is not suitable for making the digital-analog mixed CMOS integrated circuit.At " LSI プロセス engineering " the 215th page to 219 pages described single level polysilicon CMOS integrated circuit fabrication process of a book of writing by left Gao Zhengjun, publishing by Japanese オ-system publishing house; because can't make the resistance of electric capacity and resistance can not arbitrarily set as required; therefore; can't make Digital Analog Hybrid Circuits; this just makes present taking: between digital integrated circuit and analog circuit; use mould/number conversion circuit or D/A switch circuit transition; the sort circuit combining form often is difficult to satisfy the requirement of user to system reliability and confidentiality.

The purpose of this invention is to provide a kind of hybrid digital-analog integrated circuit easy to implement and manufacture method.

Technical solution of the present invention is the method with the manufacturing employing of resistance and electric capacity and CMOS (Complementary Metal Oxide Semiconductor) (CMOS) integrated circuit fabrication process compatibility, be integrated on the integrated circuit simultaneously, it is method of the present invention, comprise and prepare single level polysilicon with standard CMOS process earlier, be characterized in through ground floor polysilicon photoetching corrosion, form standard CMOS process P ditch MOS transistor and the grid of N ditch MOS transistor and the bottom electrode of polysilicon capacitance, and the method with the low temperature gas deposition deposits second layer polysilicon again behind the process polysilicon oxidation, this second layer polysilicon forms the top electrode of polysilicon resistance and polysilicon capacitance simultaneously after the ion of twice various dose injects.

In the method for the present invention, the preparation of polysilicon resistance is to carry out boron fluoride (BF in the polysilicon of low-pressure chemical vapor deposition ₂ ⁺) the ion injection, after in the diffusion furnace nitrogen atmosphere, annealing, through what be accomplished behind the photoetching corrosion.

And all being polysilicon by low-pressure chemical vapor deposition, the upper/lower electrode of polysilicon capacitance constitutes.Upper/lower electrode all passes through phosphonium ion and injects, and prepares after through photoetching corrosion after annealing in the diffusion furnace nitrogen atmosphere to obtain.

The Digital Analog Hybrid Circuits of making according to the inventive method of the present invention comprises semiconductor chip; this substrate is first conductivity type basically; the superficial layer that some second conductivity types are only arranged at part surface; it is the MOS transistor of second conductivity type that some raceway grooves are arranged on the surface of first conductivity type; the surface of semiconductor chip part has some thick insulants to cover, and is characterized in that resistance and electric capacity are arranged on this insulant.

Further, in the circuit of the present invention, the grid of described capacitor lower electrode and MOS transistor is by being made by second layer polysilicon with made and described electric capacity top electrode of one deck polycrystalline silicon material and resistance, and to go into dosage different and different according to the requirement of conductivity but it oozes pragma.

Advantage of the present invention is: 1, the method for use and common CMOS standard technology compatibility is prepared into double level polysilicon CMOS hybrid digital-analog integrated circuit, and technical maturity is easy to implement; 2, reduce the complexity of system and the parts number that is adopted; 3, improve the reliability and the confidentiality of system.

Accompanying drawing of the present invention is simply described as follows:

Fig. 1 is the process flow diagram of the inventive method.

Fig. 2 is a circuit diagram of the present invention.

Now provide a better embodiment of the present invention according to Fig. 1 and Fig. 2.

See also shown in Figure 1, preparation technology of the present invention roughly comprised for 38 steps, and its flow process is followed successively by: P trap oxidation 1, P trap photoetching 2, the P trap injects 3, the P trap advances 4, base oxygen 5, LPCVD silica 6, active area photoetching 7, photoetching 8 is injected in the field, the field injects 9, field oxidation 10, remove silica 11, pre-grid oxygen 12, raceway groove photoetching 13, raceway groove injects 14, gate oxidation 15, polysilicon 1 deposition 16, polysilicon 1 photoetching 17, polysilicon 1 oxidation 18, N+ photoetching 19, N+ injects 20, N+ advances 21, P+ photoetching 22, P+ injects 23, the source is leaked and is reoxidized 24, polysilicon II deposition 25, polysilicon resistance injects 26, polysilicon resistance photoetching 27, polysilicon II injects 28, polysilicon II annealing 29, polysilicon II photoetching 30, BPSG deposition 31, fairlead photoetching 32, metal deposition 33, metal lithographic 34, alloying 35, deposit passivation layer 36, pressure head photoetching 37 and test 38.

Characteristics of the present invention are in polysilicon 1 photoetching 17, have not only prepared the grid of digital circuit part, but also have prepared the bottom electrode of artificial circuit part electric capacity.And in polysilicon II deposition 25 to 30 technologies, prepared the top electrode of artificial circuit part resistance and electric capacity again with the method for the ion injection of twice various dose.So just with double level polysilicon digital circuit and analog circuit are being integrated on the integrated circuit simultaneously on the former technology basis, are making the CMOS integrated circuit that digital-to-analogue is mixed.

Main technologic parameters

Silicon chip substrate resistivity 4-7 Ω cm

P trap oxide layer 4300A

P trap sheet resistance 2.5K Ω/

Base oxygen 550A

Silicon nitride 1500A

Field oxygen 7000A

Pre-grid oxygen 450A

Gate oxidation 350A

Polysilicon 1 thickness 4500A

Polysilicon 1 sheet resistance 25 Ω/

Polysilicon 1 oxide layer 600A

Polysilicon 2 thickness 4500A

Polysilicon 2 high resistant sheet resistance 4K Ω/

Polysilicon 2 top electrode sheet resistances 25 Ω/

N+ sheet resistance 40 Ω/

P+ sheet resistance 90 Ω/

NSG/BPSG 2000A/7000A

Al-Si 10000A

Enhancement mode P ditch metal-oxide-semiconductor V _TP-0.70 ± 0.10V BV 〉=14V

Enhancement mode N ditch metal-oxide-semiconductor V _TN-0.70 ± 0.10V BV 〉=14V

Depletion type N ditch metal-oxide-semiconductor 1V _TND1-0.15 ± 0.10V

Depletion type N ditch metal-oxide-semiconductor 2V _TND2-0.30 ± 0.10V

Depletion type N ditch metal-oxide-semiconductor 3V _TND3-0.45 ± 0.10V

Polysilicon capacitance 5.76 * 10 ^-4PF/ μ m ²BF 〉=30V

See also shown in Figure 2, the substrate 41 that CMOS integrated circuit of the present invention has a silicon or other semi-conducting material to constitute, this substrate (claiming substrate again) is first conductivity type, it in the present embodiment n type, the superficial layer 42 of some second conductivity types (being the p type in this enforcement) is only arranged at part surface, and these superficial layers are commonly referred to trap 42.Some zone is first conductivity type (a n type) on surface of semiconductor chip 43 like this, then is second conductivity type (P type) in other zones.It is metal-oxide semiconductor (MOS) (MOS) transistor 44 (being P ditch MOS transistor in this example) of second conductivity type that some raceway grooves are arranged on the surface of first conductivity type, and the second conductivity type surface (surface of trap) has some raceway grooves is metal-oxide semiconductor (MOS) (MOS) transistor 45 (being N ditch MOS transistor in the present embodiment) of first conductivity type.On the surface 43 of semiconductor chip 41, some zone is covered by thicker silica 46, and these thicker silica are commonly referred to field oxide; Some zone is covered by thin silica 47, and these thin gate oxides are commonly referred to gate oxide.In gate oxide region (being called active region again), N ditch MOS transistor and P ditch MOS transistor have been prepared.These MOS transistor have source electrode 48, drain electrode 49 and grid 50.In the present embodiment, the source electrode of N trench transistor and drain electrode are to prepare on the surface 43 of trap 42, and the P trench transistor is that directly preparation is on semiconductor chip 41 and surface 43.The grid of N trench transistor and P trench transistor all is to constitute with low-pressure chemical vapor deposition (LPCVD) method deposit spathic silicon.Double level polysilicon electric capacity 51 and polysilicon resistance 42 on thicker silica (field oxide), have been prepared.Polysilicon capacitance 51 is made of bottom electrode 53, layer insulation thing 54 and top electrode 55.The grid 50 of the bottom electrode 53 of polysilicon capacitance 51 and

MOS transistor

44,45 is to use with the polysilicon of one deck LPCVD method deposition to make, and its conduction type also identical with resistivity (polysilicon is the n type in the present embodiment), therefore to being best in the integrated circuit production technology.The layer insulation thing 54 of polysilicon capacitance 51 can be by the silica of polysilicon through generating after the peroxidating, also can be that the composite construction of silicon oxide/silicon nitride/silicon oxide constitutes.The top electrode 55 of polysilicon capacitance 51 and polysilicon resistance 52 are made with the polysilicon of another layer (second layer) LPCVD method deposition, but its conduction type is different with resistivity.Wherein the top electrode 55 of polysilicon capacitance 51 is polysilicons of making n type low-resistivity with the method high dose notes phosphorus of ion injection, identical with the bottom electrode 53 of the grid 50 of above-mentioned MOS transistor and polysilicon capacitance 51, polysilicon resistance 52 then is to inject boron fluoride and make P type high resistance polysilicon and constitute with the suitable dosage of method that ion injects, the implantation dosage of boron fluoride during then by integrated circuit (IC) design the resistance value of desired polysilicon resistance 52 determined.The later dielectric deposition and the work of metal line can no longer be described in detail here by the known method manufacturing of the general professional in present technique field.

So just commonly (with double level polysilicon digital circuit and analog circuit are integrated on the integrated circuit simultaneously on the CMOS technology basis, have made the CMOS integrated circuit that digital-to-analogue is mixed former.

Claims

1, a kind of manufacture method of double level polysilicon CMOS hybrid digital-analog integrated circuit; comprise and prepare single level polysilicon with standard CMOS process earlier; it is characterized in that through ground floor polysilicon photoetching corrosion; form standard CMOS process P ditch MOS transistor and the grid of N ditch MOS transistor and the bottom electrode of polysilicon capacitance; and through behind the polysilicon oxidation; method with the low temperature gas deposition deposits second layer polysilicon again; this second layer polysilicon forms the top electrode of polysilicon resistance and polysilicon capacitance simultaneously after the ion of twice various dose injects.

2, the manufacture method of double level polysilicon CMOS hybrid digital-analog integrated circuit according to claim 1, the preparation that it is characterized in that polysilicon resistance are to carry out boron fluoride BF in the polysilicon of low-pressure chemical vapor deposition ₂ ⁺Ion injects, and after annealing in the diffusion furnace nitrogen atmosphere, finishes through behind the photoetching corrosion.

3, the manufacture method of double level polysilicon CMOS hybrid digital-analog integrated circuit according to claim 1; the upper and lower electrode that it is characterized in that polysilicon capacitance all is that the polysilicon by low-pressure chemical vapor deposition constitutes; upper and lower electrode all passes through phosphonium ion and injects; after in the diffusion furnace nitrogen atmosphere, annealing, finish through behind the photoetching corrosion.

4, the double level polysilicon CMOS hybrid digital-analog integrated circuit made of a kind of double level polysilicon CMOS hybrid digital-analog integrated circuit manufacture method according to claim 1; comprise semiconductor chip; this substrate is first conductivity type basically; the superficial layer that some second conductivity types are only arranged at part surface; it is the MOS transistor of second conductivity type that some raceway grooves are arranged on the surface of first conductivity type; the surface of semiconductor chip part has some thick insulants to cover, and it is characterized in that resistance and electric capacity are arranged on this insulant.

5, double level polysilicon CMOS hybrid digital-analog integrated circuit according to claim 4 is characterized in that, the grid of described capacitor lower electrode and MOS transistor is by made with one deck polycrystalline silicon material.

6, double level polysilicon CMOS hybrid digital-analog integrated circuit according to claim 4 is characterized in that, described electric capacity top electrode and resistance are made by second layer polysilicon, and to go into dosage different and different according to the requirement of conductivity but it oozes pragma.