CN109994427B - Low-temperature coefficient polycrystalline resistor module compatible with CMOS (complementary metal oxide semiconductor) process and integration method thereof - Google Patents
Low-temperature coefficient polycrystalline resistor module compatible with CMOS (complementary metal oxide semiconductor) process and integration method thereof Download PDFInfo
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Abstract
The invention discloses a low-temperature coefficient polycrystalline resistor module compatible with a double-gate oxide high-low voltage CMOS (complementary metal oxide semiconductor) process and an integration method thereof. The integration steps are as follows: 1) and forming a thick gate oxide layer and a thin gate oxide layer. 2) The silicon oxynitride layer is deposited using a low pressure chemical vapor deposition process. The resistor module mainly comprises a substrate, a trap, a field oxide layer, a polycrystalline resistor layer, a dielectric layer, a thick gate oxide layer, a thin gate oxide layer and a polycrystalline silicon gate. The invention realizes the solution of integrating the high-resistance N-type polycrystalline resistor and the low-value P-type polycrystalline resistor module on a double-gate oxide high-low voltage compatible CMOS process platform, not only plays a role of a protective layer for the polycrystalline resistor through the omega or pi-type dielectric layer, but also more importantly reduces the injection dosage of the high-value polycrystalline resistor by 30 percent, improves the injection process window of the low-temperature coefficient less than or equal to 200 ppm/DEG C low-value resistor, and improves the consistency and the yield of the polycrystalline resistor.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a low-temperature coefficient polycrystalline resistor module compatible with a dual-gate oxide high-low voltage CMOS (complementary metal oxide semiconductor) process and an integration method thereof.
Background
In the field of semiconductor device manufacturing, analog integrated circuits are gradually developed towards high speed and high precision, and the direct integration of polysilicon high-resistance thin film resistors into the circuits is an important task for increasing the integration level and reducing the volume of large-scale integrated circuits. However, since the resistance of the polysilicon high-resistance thin film resistor is easily affected by temperature and voltage, it is difficult to precisely control the absolute value thereof. The parasitic effect is very obvious, and the requirement of precise control is difficult to achieve in the process.
In analog integrated circuits, there are many materials currently used to fabricate resistors, from silicon diffused resistors fabricated by conventional Bipolar and MOS processes to laser trimmable thin film metal resistors, depending on the application. Wherein the metal film resistor has the optimal matching performance, the best temperature coefficient and the best voltage coefficient. However, the composition of the metal thin film resistor is very important, and only a few companies have mastered the optimum metal component distribution ratio. On the other hand, polysilicon materials have been widely used in the semiconductor industry, and the superior performance of polysilicon thin film resistors with temperature coefficients close to zero has attracted general interest in the industry through the research on the processes of polysilicon thin film deposition, injection, annealing and the like. With the development of semiconductor technology, the characteristics and economic benefits of the structure of the polycrystalline resistor compatible with the CMOS technology are better than those of other types of resistors, so that the polycrystalline resistor is more and more widely applied to the design of analog integrated circuits.
Disclosure of Invention
The present invention is directed to solving the problems of the prior art.
The technical scheme adopted for realizing the purpose of the invention is that the integration method of the low-temperature coefficient polycrystalline resistor module compatible with the double-gate oxide high-low voltage CMOS process mainly comprises the following steps:
1) forming a well on the surface of the substrate, forming a field oxide layer with n angstrom meters on the surface of the well, and forming a gate oxide layer on the surface of the well in a region which is not covered by the field oxide layer. Forming a shielding protective layer on the surface of the area uncovered by the field oxide layer; and removing the shielding protective layer before forming a gate oxide layer in the area uncovered by the field oxide layer. n is [4500,6000 ]. n is a natural number.
2) And forming a polycrystalline resistance layer of m angstrom meters on the surface of the field oxide layer by using a low-pressure chemical vapor deposition method, thereby generating the high-value resistance. The high value resistor has a sheet resistance value of R1. And m is 1600,2000. R1 ═ 2700ohm/sqr,4300 ohm/sqr. m and R1 are natural numbers.
Before the polycrystalline resistor layer is formed, the shielding protection layer and the field oxide layer are cleaned.
3) And etching the polycrystalline resistance layer by using a dry etching process so as to generate the resistance polycrystalline strip.
4) And growing a l angstrom oxide layer on the resistance polycrystalline strip by utilizing a thermal oxidation process, and marking the l angstrom oxide layer as a first dielectric layer. And depositing a low-pressure chemical deposition silicon nitride layer with h angstrom thickness on the resistance polycrystalline strip, and marking the silicon nitride layer as a second dielectric layer. l ═ 80,100. h ═ 250,350. l and h are natural numbers.
5) And completing the photoetching injection pre-process of the source electrode and the drain electrode of the double-gate oxide high-low voltage CMOS, and selecting a polycrystalline resistance area, a high-voltage device active area, a medium-voltage device active area and a low-voltage device active area which need low temperature coefficients.
6) And respectively forming thick gate oxide layers in the active region of the high-voltage device and the active region of the medium-voltage device. And forming a thin gate oxide layer in an active area of the low-voltage device.
7) And depositing a second polycrystalline silicon layer on the surfaces of the thick gate oxide layer, the thin gate oxide layer and the second dielectric layer, and etching the second polycrystalline silicon layer, so that the gate oxide layer and the polycrystalline silicon on the surface of the gate oxide layer form a polycrystalline silicon gate of the MOS tube, and selecting a doped source drain region of the MOS tube.
And cleaning the oxide layer on the resistor polycrystalline strip before forming the second dielectric layer.
8) And during the PMOS source-drain doping process, a photoetching injection process is adopted, P-type impurities are doped in the selected low-temperature coefficient resistor region, a rapid annealing process is adopted to activate the MOS device and inject the impurities into the polycrystalline resistor, and the film stress is eliminated, so that the low-value resistor is generated. The low-value resistor has a square resistance value of R2 and a temperature coefficient of T. R2 ═ 500ohm/sqr,700 ohm/sqr. T is less than or equal to 200 ppm/DEG C. R2 is a natural number.
9) And depositing a silicon oxynitride layer by using a low-pressure chemical vapor deposition method, and marking the silicon oxynitride layer as a third dielectric layer. And depositing the USG low-dielectric-coefficient filling film layer by using a PECVD method.
10) And (3) finishing the planarization processing of the film layer by adopting a Chemical Mechanical Polishing (CMP) process, and then finishing the processing of the contact hole of the device by adopting a dry etching process.
11) And finishing the filling processing of the contact hole of the device by adopting a tungsten sputtering process and a tungsten chemical mechanical planarization process. Sputtering an aluminum-silicon-copper film layer and finishing the etching processing of the metal connecting line.
The polycrystalline resistor module is integrated by utilizing an integration method that a double-gate oxide high-low voltage CMOS process is compatible with a low-temperature coefficient polycrystalline resistor module, and mainly comprises a substrate, a well, a field oxide layer, a polycrystalline resistor layer, a dielectric layer, a thick gate oxide layer, a thin gate oxide layer and a polycrystalline silicon gate.
The substrate is located at the bottom. The well is formed on the surface of the substrate.
The field oxide layer is formed on the surface of the well.
The field oxide layer includes a high voltage device region, a medium voltage device region, and a low voltage device region.
The high voltage device region and the medium voltage device region have a thick gate oxide layer.
The low voltage device region has a thin gate oxide.
The polycrystalline resistance layer is formed on the surface of the field oxide layer.
The dielectric layer is formed on the surface of the polycrystalline resistance layer.
And a polysilicon gate of the MOS tube is constructed on the thick gate oxide layer and the thin gate oxide layer.
The technical effect of the present invention is undoubted. The invention solves the problems that the existing high-value resistor and low-value polycrystalline resistor are compatible, the long-term stability of the low-temperature coefficient polycrystalline resistor is poor, the appearance and the size of the polycrystalline resistor are unstable, and a polycrystalline resistor strip is easy to pass through when a contact hole is etched and connected. The invention solves the problem of compatibility of high-value and low-value resistors by simultaneously generating the high-resistance N-type polycrystalline resistor and the low-value P-type polycrystalline resistor on the field oxide layer of the double-gate oxide high-voltage and low-voltage compatible CMOS process.
The invention forms the low-value polycrystalline resistor with excellent temperature coefficient by complementary doping, and the polycrystalline resistor has excellent long-term stability.
According to the invention, before the polycrystalline resistor layer and the dielectric layer are sequentially formed on the surface of the selected field oxide layer upwards, the shielding protective layer is formed on the surface of the area which is not covered by the field oxide layer, so that the well can be prevented from being polluted in the forming process of the polycrystalline resistor layer and the dielectric layer. In addition, after the polycrystalline resistor layer and the dielectric layer are formed, the shielding protective layer is removed, and then the gate oxide layer of the polycrystalline silicon gate for the high-voltage and low-voltage CMOS device is formed, so that the manufacturing yield of the polycrystalline silicon gate can be improved.
According to the invention, the polycrystalline silicon resistor layer is subjected to oxidation treatment, and the polycrystalline silicon oxide layer formed after the oxidation treatment is used as the first dielectric layer, so that the matching stress with the second dielectric layer is reduced, and the quality factor of the polycrystalline resistor is effectively improved.
The invention not only plays a role of a protective layer for the polycrystalline resistor through the omega or pi type dielectric layer on the surface of the polycrystalline resistor layer, but also more importantly reduces the injection dosage of high-value polycrystalline by 30 percent and improves the injection process window of low-value resistor with the low temperature coefficient less than or equal to 200 ppm/DEG C. In addition, the invention reduces the process fluctuation of the polycrystalline resistance and improves the consistency and the yield of the polycrystalline resistance.
Drawings
FIG. 1 is a cross-sectional view of a shield oxide layer grown after completion of well implant, anneal, field oxidation, etc. conventional CMOS processes;
FIG. 2 is a cross-sectional view of a completed first polycrystalline thin film resistor layer deposition;
FIG. 3 is a cross-sectional view of the polycrystalline resistor layer after completion of the photolithographic etching;
FIG. 4 is a cross-sectional view of a structure of a poly-resistor omega-type protection layer formed after completing the photo-etching of the poly-oxide layer and the second dielectric layer;
FIG. 5 is a cross-sectional view after completing the growth of the thick gate oxide layer required for the high voltage device;
FIG. 6 is a cross-sectional view of the growth of a thin gate oxide after the completion of stripping the thick gate oxide;
FIG. 7 is a cross-sectional view of a gate poly sidewall protection layer formed after a gate poly sidewall dielectric layer is etched back;
FIG. 8 is a cross-sectional view after completion of MOS transistor source drain implant;
FIG. 9 is a cross-sectional view of the contact hole after global planarization is complete and after etching;
FIG. 10 is a schematic structural diagram of a dual poly resistor structure integrated with a dual gate oxide high and low voltage compatible CMOS process according to an embodiment of the present invention, namely embodiment 2;
FIG. 11 is a cross-sectional view of the completed first and second dielectric layers deposited on the first polysilicon layer in example 2;
FIG. 12 is a cross-sectional view of example 2 after etching of the first polycrystalline resistive layer and the overlying dielectric layer is completed;
FIG. 13 is a cross-sectional view of example 2 showing the formation of a poly-resistive π -type protection structure.
Detailed Description
The present invention is further illustrated by the following examples, but it should not be construed that the scope of the above-described subject matter is limited to the following examples. Various substitutions and alterations can be made without departing from the technical idea of the invention and the scope of the invention is covered by the present invention according to the common technical knowledge and the conventional means in the field.
Example 1:
the integration method of the low-temperature coefficient polycrystalline resistor module compatible with the dual-gate oxide high-low voltage CMOS process mainly comprises the following steps:
1) a trap is formed on the surface of the substrate, a field oxide layer with the thickness of 5000 angstroms is formed on the surface of the trap, and a gate oxide layer is formed on the surface of the trap in a region which is not covered by the field oxide layer.
And forming a shielding protective layer on the surface of the area uncovered by the field oxide layer. And removing the shielding protective layer before forming a gate oxide layer in the area uncovered by the field oxide layer. And forming a polycrystalline resistance layer of 1800 angstrom meters on the surface of the field oxide layer by using a low-pressure chemical vapor deposition method, and injecting N-type phosphorus elements into the polycrystalline silicon layer by adopting a common injection mode, thereby generating the high-value resistance. The block resistance value of the high-value resistor is 3600 ohm/sqr. And forming a shielding protection layer on the surface of the active region and the field oxide layer, wherein the shielding protection layer can be a thermal oxide layer.
The MOS transistor can be divided into an NMOS transistor and a PMOS transistor, so that the structure in the embodiment of the invention can comprise a polycrystalline resistor integrated with the NMOS transistor, a polycrystalline resistor integrated with the PMOS transistor or a polycrystalline resistor integrated with both the NMOS transistor and the PMOS transistor. When the poly resistor is integrated with the NMOS transistor, the well in this step is referred to as a P-well. When the poly resistor is integrated with the PMOS transistor, the well in this step is referred to as an N-well. When the polycrystalline resistor is integrated with the NMOS transistor and the PMOS transistor at the same time, the well in the step is a general name of an N well and a P well.
2) And etching the polysilicon layer by adopting a photoetching process and an etching process such as a dry polycrystalline etching machine, wherein the polysilicon material at other positions except the polysilicon material formed on the surface of the selected field oxide layer is etched, so that the polysilicon remained on the surface of the selected field oxide layer forms a polycrystalline resistor strip with the required size.
Before the polycrystalline resistor layer is formed, the shielding protection layer and the field oxide layer are cleaned.
3) And growing a 100 angstrom oxide layer on the resistance polycrystalline strip by using a thermal oxidation process, and marking the oxide layer as a first dielectric layer. And cleaning the surfaces of the field oxide layer and the shielding protective layer before deposition in a conventional mode, and then depositing a low-pressure chemical deposition silicon nitride layer with the thickness of 300 angstroms on the resistance polycrystalline strip, wherein the silicon nitride layer is marked as a second dielectric layer.
And cleaning the surface of the deposited polycrystalline silicon layer before oxidation in a conventional mode, and after cleaning, oxidizing the surface of the polycrystalline silicon layer in a furnace tube thermal oxidation mode to form a polycrystalline silicon oxide layer, wherein the oxidation temperature during oxidation treatment can be 850 +/-5 ℃, the oxidation atmosphere is dry oxygen, and the polycrystalline silicon oxide layer formed after oxidation treatment can be a silicon dioxide layer, and the thickness of the polycrystalline silicon oxide layer can be 100 angstroms. And cleaning the polycrystalline silicon oxide layer before deposition in a conventional mode, and depositing a second dielectric material layer on the surface of the polycrystalline silicon oxide layer by adopting a vertical furnace tube chemical vapor deposition process after cleaning, wherein the deposition temperature in the deposition process can be 760 +/-5 ℃, the second dielectric material layer can be a silicon nitride layer, and the thickness of the second dielectric material layer can be 300 angstrom. The invention can avoid doping impurity in the process of oxidizing the polysilicon layer by cleaning the surface of the polysilicon layer before oxidation. By cleaning before deposition before depositing the second dielectric material layer, doping of impurities into the second dielectric material layer in the deposition process can be avoided.
Finally, referring to fig. 4, the polysilicon oxide layer and the second dielectric material layer are etched by using a photolithography process and an etching process such as a dry silicon nitride etching machine, except for the oxidized polysilicon and the second dielectric material sequentially formed on the surface of the selected field oxide layer, the oxidized polysilicon and the second dielectric material at other positions are etched away, so that an omega-shaped protective layer is formed on the polysilicon remaining on the surface of the selected field oxide layer, the oxidized polysilicon formed on the surface of the polysilicon forms a first dielectric layer of the double poly capacitor, and the second dielectric material formed on the surface of the first dielectric layer forms a second dielectric layer of the polysilicon resistor. Thus, a polycrystalline resistor layer and a dielectric layer composed of a first dielectric layer and a second dielectric layer are sequentially formed on the surface of the selected field oxide layer. Particularly, the first dielectric layer and the second dielectric layer of the polycrystalline resistor layer can be compatible with the dielectric layer in the double-polysilicon capacitor integrated by the double-gate oxide high-low voltage compatible CMOS process, and the first dielectric layer and the second dielectric layer can be deposited by adopting a single process.
It should be noted that in this embodiment, after the polysilicon layer is doped, photolithography and etching processes are used to etch away the polysilicon material at other positions except above the selected field oxide layer, but those skilled in the art may also choose the following method, see fig. 11-12, after the polysilicon layer, the oxide polysilicon layer and the second dielectric layer are formed, photolithography and etching processes are used to process the material. For example, after the polysilicon layer is formed and doped, the polysilicon layer, the oxidized polysilicon layer and the second dielectric layer are etched by photolithography and etching processes, and except for the polysilicon on the surface of the selected field oxide layer, the polysilicon, the oxidized polysilicon layer and the second dielectric layer are all etched away.
According to the invention, the polycrystalline resistor layer is cleaned before deposition before the polycrystalline resistor layer is deposited on the surfaces of the field oxide layer and the shielding protection layer, so that impurities doped in the polycrystalline resistor layer in the deposition process can be avoided, and phosphorus is injected into the polycrystalline silicon layer, thus the conductivity of the polycrystalline silicon layer can be improved, and the high-value N-type polycrystalline resistor doping is completed.
4) And completing the photoetching injection pre-process of the source electrode and the drain electrode of the double-gate oxide high-low voltage CMOS, and selecting a required polycrystalline resistor area, a high-voltage device active area, a medium-voltage device active area and a low-voltage device active area.
5) And respectively forming thick gate oxide layers in the active region of the high-voltage device and the active region of the medium-voltage device. And stripping the thick gate oxide layer in the selected low-voltage device area uncovered by the field oxide layer, and then forming a thin gate oxide layer.
And depositing a second polysilicon layer on the surfaces of the thick gate oxide layer, the thin gate oxide layer and the dielectric layer so that the polysilicon formed on the surface of the gate oxide layer and the gate oxide layer form a polysilicon gate of the MOS tube.
And etching the polysilicon layer by adopting photoetching and etching processes such as a dry-method polysilicon etching machine, wherein the polysilicon on the surfaces of other positions except the polysilicon in the selected area is etched, and the polysilicon remained on the surface of the gate oxide layer and the gate oxide layer form a polysilicon gate of the MOS tube. The grid polycrystalline etching adopts end point detection, and the selection ratio of the polycrystalline silicon to the grid oxide layer is improved by increasing the oxygen concentration of etching gas during the process of over-etching the oxide layer. Therefore, the source and drain regions of the MOS transistor can be prevented from excessively damaging silicon, and the polycrystalline resistor layer on the field oxide layer can be prevented from being excessively etched through the protection of the second dielectric layer and the first dielectric layer.
6) And depositing a second polycrystalline silicon layer on the surfaces of the thick gate oxide layer, the thin gate oxide layer and the second dielectric layer, and etching the second polycrystalline silicon layer, so that the gate oxide layer and the polycrystalline silicon on the surface of the gate oxide layer form a polycrystalline silicon gate of the MOS tube, and selecting a doped source drain region of the MOS tube.
7) And during the PMOS source-drain doping process, a photoetching injection process is adopted, P-type impurities are doped in the selected low-temperature coefficient resistor region, a rapid annealing process is adopted to activate the MOS device and inject the impurities into the polycrystalline resistor, and the film stress is eliminated, so that the low-value resistor is generated. The square resistance value of the low-value resistor is recorded as 600ohm/sqr, the temperature coefficient is recorded as T, and the T is 200 ppm/DEG C.
And etching the second dielectric layer by adopting a dry etching process to form the omega-shaped silicon nitride dielectric layer.
Firstly, forming a lightly doped source drain region by adopting photoetching and ion implantation processes. In the figure, the mark indicates that the content of ions is low, two layers of thin films which are the same as the materials of the first dielectric layer and the second dielectric layer are deposited, and the two layers of thin films are etched in an anisotropic mode to form side walls located on two sides of the polycrystalline resistor layer of the polycrystalline silicon gate and the field oxide layer.
Referring to fig. 8, a heavily doped source/drain region of the PMOS transistor and a low-temperature coefficient low-value polycrystalline resistor region are formed by photolithography and ion implantation. In the figure, the "+" in the mark indicates that the content of ions is high, and then rapid annealing treatment is carried out, so that the doped source and drain regions of the PMOS tube can be formed.
Referring to fig. 9, a third dielectric layer is deposited by a low pressure chemical vapor deposition growth process, and then the third dielectric layer is planarized by a global chemical mechanical process, and etched by photolithography and etching processes to form a contact hole for depositing metal, and then tungsten metal is deposited in the contact hole. And sputtering aluminum silicon copper after finishing chemical mechanical planarization of the metal tungsten, and forming a metal connecting line in a required area by adopting a photoetching process.
After the third dielectric layer is flattened by a chemical mechanical process, when a contact hole for depositing metal is manufactured, the depth of the contact hole is from 4000 to 14000 angstroms, the thickness of the polycrystalline film with the low temperature coefficient is limited to a certain extent at present, if the deposition of the polycrystalline resistance layer is arranged after the deposition and the etching of grid polycrystal, the polycrystalline resistance layer is easy to be over-etched during the etching of the contact hole due to the fact that the polycrystalline resistance layer is thin, and the performance fluctuation of the polycrystalline resistance is caused. If the third dielectric layer is subjected to the conventional reflow process to complete the planarization, the window of the subsequent contact hole photoetching exposure process is smaller, and finally the performance of the device fluctuates. Therefore, when the polycrystalline resistor module is integrated with the double-gate oxide high-low voltage compatible CMOS process, the polycrystalline resistor layer is deposited before gate polycrystalline deposition and etching, and the polycrystalline silicon resistor film layer is prevented from being over-etched.
Because the first dielectric layer is formed by a deposition process generally at present and is limited by the deposition process, the thickness of the formed first dielectric layer is still larger, the invention can reduce the thickness of the first dielectric layer, reduce the consumption of the polycrystalline resistance film and effectively improve the quality factor by oxidizing the polycrystalline resistance film and taking a compact polycrystalline silicon oxidation layer formed after the oxidation treatment as the first dielectric layer.
8) The silicon oxynitride layer is deposited using a low pressure chemical vapor deposition process. And depositing the USG low-dielectric-coefficient filling film layer by using a PECVD method.
9) And (3) finishing the planarization processing of the film layer by adopting a Chemical Mechanical Polishing (CMP) process, and then finishing the processing of the contact hole of the device by adopting a dry etching process.
10) And finishing the filling processing of the contact hole of the device by adopting a tungsten sputtering process and a tungsten chemical mechanical planarization process. Sputtering an aluminum-silicon-copper film layer and finishing the etching processing of the metal connecting line.
The invention completes the manufacture of the high-value N-type polycrystalline resistor and the low-value low-temperature coefficient P-type polycrystalline resistor while manufacturing the double-gate oxide high-low voltage compatible CMOS device. The invention forms the omega-type or pi-type polysilicon resistor layer protective film layer through the layout processing of the first dielectric layer and the second dielectric layer, and particularly points out that the polysilicon resistor layer protective film layer can be compatible with the dielectric layer in the double-polysilicon capacitor integrated by the double-gate oxygen high-low voltage compatible CMOS process, and can also finish the deposition of the first dielectric layer and the second dielectric layer by adopting a single process, thereby avoiding the influence of the processes such as oxidation, etching, stripping and the like on the geometric dimension of the polysilicon resistor film and further improving the electrical property of the polysilicon resistor. In addition, the boron-phosphorus hole trap is formed by complementary doping and fluorine impurities are doped, so that the combination quantity of hydrogen ions and dangling bonds in silicon can be reduced, the stability of the resistivity of the polycrystalline film can be improved, and the P-type polycrystalline resistor with low temperature coefficient and excellent electrical property is obtained.
Example 2:
referring to fig. 10 to 13, the method for integrating the low temperature coefficient poly-resistor module compatible with the dual gate oxide high and low voltage CMOS process mainly includes the following steps:
1) a well is formed on the surface of the substrate, a field oxide layer of 5000 angstrom meters is formed on the surface of the well, and a shielding protective layer is formed in the area outside the field oxide layer.
2) A polycrystalline resistance layer of 1800 angstrom meters is formed on the surface of the field oxide layer by using a low pressure chemical vapor deposition method, thereby generating a high value resistance. The block resistance value of the high-value resistor is 3600 ohm/sqr.
Before the polycrystalline resistor layer is formed, the shielding protection layer and the field oxide layer are cleaned.
3) And etching the polycrystalline resistance layer by using a dry etching process so as to generate the resistance polycrystalline strip.
4) And growing a 100 angstrom oxide layer on the resistance polycrystalline strip by using a thermal oxidation process, and marking the oxide layer as a first dielectric layer. A low pressure chemically deposited silicon nitride layer, designated as the second dielectric layer, was deposited on the resistive poly strip to a thickness of 300 angstroms.
5) And completing the photoetching injection pre-process of the source electrode and the drain electrode of the double-gate oxide high-low voltage CMOS, and selecting a polycrystalline resistance area, a high-voltage device active area, a medium-voltage device active area and a low-voltage device active area which need low temperature coefficients.
6) And respectively forming thick gate oxide layers in the active region of the high-voltage device and the active region of the medium-voltage device. And forming a thin gate oxide layer in an active area of the low-voltage device.
7) And depositing a second polycrystalline silicon layer on the surfaces of the thick gate oxide layer, the thin gate oxide layer and the second dielectric layer, and etching the second polycrystalline silicon layer, so that the gate oxide layer and the polycrystalline silicon on the surface of the gate oxide layer form a polycrystalline silicon gate of the MOS tube, and selecting a doped source drain region of the MOS tube.
And cleaning the oxide layer on the resistor polycrystalline strip before forming the second dielectric layer.
8) And during the PMOS source-drain doping process, a photoetching injection process is adopted, P-type impurities are doped in the selected low-temperature coefficient resistor region, a rapid annealing process is adopted to activate the MOS device and inject the impurities into the polycrystalline resistor, and the film stress is eliminated, so that the low-value resistor is generated. The square resistance value of the low-value resistor is recorded as 600ohm/sqr, the temperature coefficient is recorded as T, and T is less than or equal to 200 ppm/DEG C.
And etching the second dielectric layer by adopting a dry etching process to form the omega-shaped or pi-shaped silicon nitride dielectric layer.
Referring to fig. 13, a poly-resistive pi-type protection layer may be implemented.
9) And depositing a silicon oxynitride layer by using a low-pressure chemical vapor deposition method, and marking the silicon oxynitride layer as a third dielectric layer. And depositing the USG low-dielectric-coefficient filling film layer by using a PECVD method.
10) And (3) finishing the planarization processing of the film layer by adopting a Chemical Mechanical Polishing (CMP) process, and then finishing the processing of the contact hole of the device by adopting a dry etching process.
11) And finishing the filling processing of the contact hole of the device by adopting a tungsten sputtering process and a tungsten chemical mechanical planarization process. Sputtering an aluminum-silicon-copper film layer and finishing the etching processing of the metal connecting line.
Example 3:
the polycrystalline resistor module is integrated by utilizing an integration method that a double-gate oxide high-low voltage CMOS process is compatible with a low-temperature coefficient polycrystalline resistor module, and mainly comprises a substrate, a well, a field oxide layer, a polycrystalline resistor layer, a dielectric layer, a thick gate oxide layer, a thin gate oxide layer and a polycrystalline silicon gate.
The substrate is located at the bottom. The well is formed on the surface of the substrate.
The field oxide layer is formed on the surface of the well.
The field oxide layer includes a high voltage device region, a medium voltage device region, and a low voltage device region.
The high voltage device region and the medium voltage device region have a thick gate oxide layer.
The low voltage device region has a thin gate oxide.
The polycrystalline resistance layer is formed on the surface of the field oxide layer.
The dielectric layer is formed on the surface of the polycrystalline resistance layer.
And a polysilicon gate of the MOS tube is constructed on the thick gate oxide layer and the thin gate oxide layer.
Example 4:
the integration method of the low-temperature coefficient polycrystalline resistor module compatible with the dual-gate oxide high-low voltage CMOS process mainly comprises the following steps:
1) forming a trap on the surface of the substrate, and forming a field oxide layer on the surface of the trap.
In this embodiment, referring to fig. 1, a well is formed on a surface of a substrate, a field oxide layer is formed on a surface of the well, and a shielding protection layer is formed on a surface of an active region and the field oxide layer, where the shielding protection layer may be a thermal oxide layer. It should be noted that, since the MOS transistor can be divided into an NMOS transistor and a PMOS transistor, the structure in the embodiment of the present invention may include a poly resistor integrated with the NMOS transistor, a poly resistor integrated with the PMOS transistor, or a poly resistor integrated with both the NMOS transistor and the PMOS transistor. When the polycrystalline resistor is integrated with the NMOS tube, the trap in the step is a P trap, when the polycrystalline resistor is integrated with the PMOS tube, the trap in the step is an N trap, when the double-polycrystalline capacitor is simultaneously integrated with the NMOS tube and the PMOS tube, and the trap in the step is a general name of the N trap and the P trap. In all the drawings of the present invention, the polycrystalline resistor is integrated with the NMOS transistor and the PMOS transistor at the same time, and those skilled in the art can understand the composition and manufacturing method of another structure through the description of the embodiments and the drawings.
2) And sequentially forming a polycrystalline resistor layer and a dielectric layer on the surface of the selected field oxide layer.
In this embodiment, first, referring to fig. 2, the surfaces of the field oxide layer and the shielding protection layer are cleaned before deposition in a conventional manner, after the cleaning is completed, a polycrystalline resistance layer is deposited on the surfaces of the field oxide layer and the shielding protection layer, i.e., above the well, and phosphorus with a medium dose is injected, where the thickness of the polycrystalline silicon layer may be 1800 angstroms. According to the invention, the polycrystalline resistor layer is cleaned before deposition before the polycrystalline resistor layer is deposited on the surfaces of the field oxide layer and the shielding protection layer, so that impurities doped in the polycrystalline resistor layer in the deposition process can be avoided, and phosphorus is injected into the polycrystalline silicon layer, thus the conductivity of the polycrystalline silicon layer can be improved, and the high-value N-type polycrystalline resistor doping is completed.
3) Referring to fig. 3, the polysilicon layer is etched by using a photolithography process and an etching process such as a dry poly etcher, and the polysilicon material at other positions except for the polysilicon material formed on the surface of the selected field oxide layer is etched, so that the polysilicon remaining on the surface of the selected field oxide layer forms a poly resistor strip.
And cleaning the surface of the deposited polycrystalline silicon layer before oxidation in a conventional mode, and after cleaning, oxidizing the surface of the polycrystalline silicon layer in a furnace tube thermal oxidation mode to form a polycrystalline silicon oxide layer, wherein the oxidation temperature during oxidation treatment can be 850 +/-5 ℃, the oxidation atmosphere is dry oxygen, and the polycrystalline silicon oxide layer formed after oxidation treatment can be a silicon dioxide layer, and the thickness of the polycrystalline silicon oxide layer can be 100 angstroms. And cleaning the polycrystalline silicon oxide layer before deposition in a conventional mode, and depositing a second dielectric material layer on the surface of the polycrystalline silicon oxide layer by adopting a vertical furnace tube chemical vapor deposition process after cleaning, wherein the deposition temperature in the deposition process can be 760 +/-5 ℃, the second dielectric material layer can be a silicon nitride layer, and the thickness of the second dielectric material layer can be 300 angstrom. The invention can avoid doping impurity in the process of oxidizing the polysilicon layer by cleaning the surface of the polysilicon layer before oxidation. By cleaning before deposition before depositing the second dielectric material layer, doping of impurities into the second dielectric material layer in the deposition process can be avoided.
4) Referring to fig. 4, the polysilicon oxide layer and the second dielectric material layer are etched by using a photolithography process and an etching process such as a dry silicon nitride etcher, except for the oxidized polysilicon and the second dielectric material sequentially formed on the surface of the selected field oxide layer, the oxidized polysilicon and the second dielectric material at other positions are etched away, so that an omega-shaped protective layer is formed on the polysilicon remaining on the surface of the selected field oxide layer, the oxidized polysilicon formed on the surface of the polysilicon forms a first dielectric layer of the double-poly capacitor, and the second dielectric material formed on the surface of the first dielectric layer forms a second dielectric layer of the polysilicon resistor. Thus, a polycrystalline resistor layer and a dielectric layer composed of a first dielectric layer and a second dielectric layer are sequentially formed on the surface of the selected field oxide layer. Particularly, the first dielectric layer and the second dielectric layer of the polycrystalline resistor layer can be compatible with the dielectric layer in the double-polysilicon capacitor integrated by the double-gate oxide high-low voltage compatible CMOS process, and the first dielectric layer and the second dielectric layer can be deposited by adopting a single process.
It should be noted that in this embodiment, after the polysilicon layer is doped, photolithography and etching processes are used to etch away the polysilicon material at other positions except above the selected field oxide layer, but those skilled in the art may also choose the following method, see fig. 11-12, after the polysilicon layer, the oxide polysilicon layer and the second dielectric layer are formed, photolithography and etching processes are used to process the material. For example, after the polysilicon layer is formed and doped, the polysilicon layer, the oxidized polysilicon layer and the second dielectric layer are etched by photolithography and etching processes, and except for the polysilicon on the surface of the selected field oxide layer, the polysilicon, the oxidized polysilicon layer and the second dielectric layer are all etched away.
5) Referring to fig. 5, a thick gate oxide is formed in the high and medium voltage device regions not covered by the selected field oxide. Referring to fig. 6, a stripped gate oxide is formed in the low-voltage device region uncovered by the selected field oxide, and then a thin gate oxide is formed, and then a second polysilicon layer is deposited on the surfaces of the thick gate oxide, the thin gate oxide and the dielectric layer, so that polysilicon formed on the surface of the gate oxide and the gate oxide form a polysilicon gate of the transistor.
And etching the polysilicon layer by using photoetching and etching processes such as a dry-method polysilicon etching machine, wherein the polysilicon on the surfaces of other positions except the polysilicon in the selected area is etched, and the polysilicon remained on the surface of the gate oxide layer and the gate oxide layer form the polysilicon gate of the tube. The grid polycrystalline etching adopts end point detection, and the selection ratio of the polycrystalline silicon to the grid oxide layer is improved by increasing the oxygen concentration of etching gas during the process of over-etching the oxide layer. Therefore, the source and drain regions of the MOS transistor can be prevented from excessively damaging silicon, and the polycrystalline resistor layer on the field oxide layer can be prevented from being excessively etched through the protection of the second dielectric layer and the first dielectric layer.
In this embodiment, referring to fig. 7, a lightly doped source/drain region is formed by photolithography and ion implantation. In the figure, the mark indicates that the content of ions is low, two layers of thin films which are the same as the materials of the first dielectric layer and the second dielectric layer are deposited, and the two layers of thin films are etched in an anisotropic mode to form side walls located on two sides of the polycrystalline resistor layer of the polycrystalline silicon gate and the field oxide layer. With respect to another protection manner of the polycrystalline resistor layer described above, referring to fig. 13, a polycrystalline resistor pi-type protection layer may be implemented.
Referring to fig. 8, a heavily doped source/drain region of the PMOS transistor and a low-temperature coefficient low-value polycrystalline resistor region are formed by photolithography and ion implantation. In the figure, the "+" in the mark indicates that the content of ions is high, and then rapid annealing treatment is carried out, so that the doped source and drain regions of the PMOS tube can be formed.
Referring to fig. 9, a third dielectric layer is deposited by a low pressure chemical vapor deposition growth process, and then the third dielectric layer is planarized by a global chemical mechanical process, and etched by photolithography and etching processes to form a contact hole for depositing metal, and then tungsten metal is deposited in the contact hole. And sputtering aluminum silicon copper after finishing chemical mechanical planarization of the metal tungsten, and forming a metal connecting line in a required area by adopting a photoetching process.
After the third dielectric layer is flattened by a chemical mechanical process, when a contact hole for depositing metal is manufactured, the depth of the contact hole is from 4000 to 14000 angstroms, the thickness of the polycrystalline film with a low temperature coefficient is limited at present, if the polycrystalline resistance layer deposition is arranged after the gate polycrystalline deposition and etching, the polycrystalline resistance layer is easy to over-etch during the contact hole etching due to the fact that the polycrystalline resistance layer is thin, and therefore the polycrystalline resistance performance fluctuation is caused. If the third dielectric layer is subjected to the conventional reflow process to complete the planarization, the window of the subsequent contact hole photoetching exposure process is smaller, and finally the performance of the device fluctuates. Therefore, when the polycrystalline resistor module is integrated with the double-gate oxide high-low voltage compatible CMOS process, the polycrystalline resistor layer is deposited before gate polycrystalline deposition and etching, and the polycrystalline silicon resistor film layer is prevented from being over-etched.
Because the first dielectric layer is formed by a deposition process generally at present and is limited by the deposition process, the thickness of the formed first dielectric layer is still larger, the invention can reduce the thickness of the first dielectric layer and effectively improve the quality factor by oxidizing the polycrystalline silicon resistor film and taking a compact polycrystalline silicon oxide layer formed after the oxidation treatment as the first dielectric layer.
According to the embodiment, the manufacturing of the high-value N-type polycrystalline resistor and the low-value low-temperature-coefficient P-type polycrystalline resistor is completed while the double-gate-oxide high-voltage and low-voltage compatible CMOS device is manufactured. The invention forms the omega-type or pi-type polysilicon resistor layer protective film layer through the layout processing of the first dielectric layer and the second dielectric layer, and particularly points out that the polysilicon resistor layer protective film layer can be compatible with the dielectric layer in the double-polysilicon capacitor integrated by the double-gate oxygen high-low voltage compatible CMOS process, and can also finish the deposition of the first dielectric layer and the second dielectric layer by adopting a single process, thereby avoiding the influence of the processes such as oxidation, etching, stripping and the like on the geometric dimension of the polysilicon resistor film and further improving the electrical property of the polysilicon resistor. In addition, the boron-phosphorus hole trap is formed by complementary doping and fluorine impurities are doped, so that the combination quantity of hydrogen ions and dangling bonds in silicon can be reduced, the stability of the resistivity of the polycrystalline film can be improved, and the P-type polycrystalline resistor with low temperature coefficient and excellent electrical property is obtained.
Example 5:
the integration method of the low-temperature coefficient polycrystalline resistor module compatible with the dual-gate oxide high-low voltage CMOS process mainly comprises the following steps:
1) a well is formed in the substrate surface.
2) And forming a field oxide layer on the surface of the well.
3) And depositing a polycrystalline resistance film layer on the surface of the selected field oxide layer upwards.
4) After phosphorus impurities are injected by adopting an injection process, a polycrystalline resistor strip is generated on the surface of the selected field oxide layer by photoetching and etching processes.
Preferably, the polycrystalline resistor, the first dielectric layer and the second dielectric layer are sequentially formed on the surface of the selected field oxide layer. And etching the polycrystalline resistor strip and the top surface protection layer in the selected region by using a polycrystalline resistor photoetching plate. And forming polycrystalline resistor side wall protection by utilizing a subsequent gate polycrystalline side wall back-etching process, and combining the polycrystalline resistor side wall protection with a polycrystalline resistor top layer protection medium to finally form the pi-shaped polycrystalline resistor protection layer. The thickness of the first dielectric layer is 100 angstroms and the thickness of the second dielectric layer is 300 angstroms.
5) And generating an oxide layer on the polycrystalline resistor by adopting an oxidation process.
6) And depositing a dielectric silicon nitride layer by adopting a low-pressure chemical vapor deposition process, and then generating an omega-shaped protective layer on the polycrystalline resistor layer by adopting a photoetching process.
7) A thick gate oxide layer is formed in the selected high and medium voltage device active region.
8) And stripping the thick gate oxide in the selected active region of the low-voltage device to generate a thin gate oxide layer.
9) And depositing a gate polycrystalline film layer, and doping and injecting to meet the requirement of gate polycrystalline resistance. And etching the grid polycrystal in the selected active region of the MOS device to form a doped source drain region of the MOS tube.
10) And during the PMOS source-drain doping process, doping P-type impurities into the selected low-temperature coefficient resistor region by adopting a photoetching injection process.
11) And activating the MOS device and injecting impurities into the polycrystalline resistor by adopting a rapid annealing process.
12) And depositing a silicon oxynitride layer and a USG low-dielectric-coefficient filling film layer by adopting a low-pressure chemical vapor deposition method and PECVD (plasma enhanced chemical vapor deposition).
13) And (3) finishing the planarization processing of the film layer by adopting a Chemical Mechanical Polishing (CMP) process, and then finishing the processing of the contact hole of the device by adopting a dry etching process.
14) And (3) completing the filling processing of the device contact hole by adopting a tungsten sputtering process and a tungsten chemical mechanical planarization process, and then sputtering an aluminum-silicon-copper film layer and completing the photoetching processing of the metal connecting line.
Example 6:
the polycrystalline resistor module comprises a substrate, a well is formed on the surface of the substrate, a field oxide layer is formed on the surface of the well, a polycrystalline resistor layer and a dielectric layer are sequentially formed on the surface of a selected field oxide layer, a thick gate oxide layer is formed in selected high-voltage and medium-voltage device areas, a thin gate oxide layer is formed in selected low-voltage device areas, a polycrystalline silicon gate of an MOS (metal oxide semiconductor) tube is formed on the gate oxide layer, and finally a high-low voltage compatible MOS device is formed.
Example 7
The integration method of the low-temperature coefficient polycrystalline resistor module compatible with the dual-gate oxide high-low voltage CMOS process mainly comprises the following steps:
1) depositing a polycrystalline layer of 1800 angstroms by low pressure chemical vapor deposition on a 5000 angstroms field oxide layer. Firstly, N-type phosphorus is selected for injection doping, and then a rapid annealing process is adopted to activate injected impurities to eliminate polycrystalline deposition stress, so that a high-value resistor with a square resistance value of 3600ohm/sqr is generated.
2) And generating the resistance polycrystalline strip with the required size by adopting a dry etching process.
The dry etching process with the high selection ratio of the oxide layer to the silicon layer can avoid punch-through of the polycrystalline resistor strips caused by over-etching of the polycrystalline resistor layer.
3) Firstly, a 100-angstrom oxide layer grows on a polycrystalline resistor strip of S2 by adopting a thermal oxidation process, a low-pressure chemical deposition silicon nitride layer with the thickness of 300 angstrom is deposited after cleaning, and an omega-shaped silicon nitride dielectric layer is formed by adopting a dry etching process.
The thermal oxidation layer and the low-pressure chemical vapor deposition method are adopted to deposit the silicon nitride layer to generate the omega-shaped structure, the consumption of resistance polycrystalline layers caused by the oxidation of thick gate oxide and thin gate oxide which are compatible with CMOS in high and low pressure can be prevented from being caused by the polycrystalline strips, the influence of the wet method for stripping the thick gate oxide layer on the polycrystalline resistance layer is avoided, and the process stability of the geometrical size of the polycrystalline resistance is improved.
The thermal oxidation layer and the low-pressure chemical vapor deposition method are adopted to deposit the silicon nitride layer to generate an omega-shaped protection structure, so that penetration of hydrogen atoms and other impurities is prevented, and the electrical property stability of the polycrystalline strip is improved.
4) The main process steps of the normal dual-gate oxide high-low voltage CMOS source and drain photoetching injection pre-process are thick gate oxide oxidation, low-voltage area oxide layer stripping, thin gate oxide oxidation, gate polycrystal deposition, gate polycrystal doping, gate polycrystal etching, gate polycrystal side wall layer back etching and the like.
5) In the double-gate oxygen high-low pressure CMOS source and drain photoetching injection process, P-type source and drain photoetching injection and a rapid annealing process are utilized to activate doped impurities in a polycrystalline resistor area needing a low temperature coefficient to eliminate film stress, and a low-value resistor with a square resistance value of 600ohm/sqr and a temperature coefficient of 200 ppm/DEG C is generated.
6) Then, a silicon oxynitride layer is deposited by a low-pressure chemical vapor deposition method and a USG low-dielectric-coefficient filling film layer is deposited by PECVD.
7) And (3) finishing the planarization processing of the film layer by adopting a Chemical Mechanical Polishing (CMP) process, and then finishing the processing of the contact hole of the device by adopting a dry etching process.
And the chemical mechanical polishing CMP process is adopted to complete the planarization of the film layer, improve the photoetching exposure process condition window of the CT layer and improve the consistency of the contact holes of the polycrystalline strip CT.
8) And (3) completing the filling processing of the device contact hole by adopting a tungsten sputtering process and a tungsten chemical mechanical planarization process, and then sputtering an aluminum-silicon-copper film layer and completing the etching processing of the metal connecting line.
Claims (8)
1. The integration method of the low-temperature coefficient polycrystalline resistor module compatible with the dual-gate oxide high-low voltage CMOS process is characterized by comprising the following steps of:
1) forming a well on the surface of the substrate, forming an n-angstrom field oxide layer on the surface of the well, and forming a gate oxide layer on the surface of the well in a region which is not covered by the field oxide layer; n is a natural number;
2) forming a polycrystalline resistor layer of m angstrom meters on the surface of the field oxide layer by using a low-pressure chemical vapor deposition method, and generating a high-value resistor in a common injection mode; the square resistance value of the high-value resistor is R1; m and R1 are natural numbers;
3) etching the polycrystalline resistance layer by using a dry etching process so as to generate a resistance polycrystalline strip;
4) growing a l angstrom oxide layer on the resistance polycrystalline strip by using a thermal oxidation process, and marking the l angstrom oxide layer as a first dielectric layer; depositing a low-pressure chemical deposition silicon nitride layer with h angstrom thickness on the resistance polycrystalline strip, and marking the silicon nitride layer as a second dielectric layer; l and h are natural numbers;
5) completing the photoetching injection pre-process of a source electrode and a drain electrode of a double-gate oxide high-low voltage CMOS, and selecting a polycrystalline resistor area, a high-voltage device active area, a medium-voltage device active area and a low-voltage device active area which need low temperature coefficients;
6) respectively forming thick gate oxide layers in the active area of the high-voltage device and the active area of the medium-voltage device; forming a thin gate oxide layer in an active area of a low-voltage device;
7) depositing a second polycrystalline silicon layer on the surfaces of the thick gate oxide layer, the thin gate oxide layer and the second dielectric layer, and etching the second polycrystalline silicon layer, so that the gate oxide layer and the polycrystalline silicon on the surface of the gate oxide layer form a polycrystalline silicon gate of the MOS tube, and selecting a doped source drain region of the MOS tube;
8) completing the photoetching injection of a double-gate oxide high-low voltage CMOS source electrode and a drain electrode in a doped source drain region of the MOS tube, namely doping impurities in a selected low-temperature coefficient resistor region, activating the doped impurities by utilizing the photoetching injection and rapid annealing process of the source electrode and the drain electrode of the MOS tube, and eliminating the stress of a film so as to generate a low-value resistor; the square resistance value of the low-value resistor is R2, and the temperature coefficient is T; r2 is a natural number;
9) depositing a silicon oxynitride layer by using a low-pressure chemical vapor deposition method, and marking the silicon oxynitride layer as a third dielectric layer; depositing a USG low dielectric coefficient filling film layer by using a PECVD method;
10) the chemical mechanical polishing CMP process is adopted to finish the planarization processing of the film layer, and then the dry etching process is adopted to finish the processing of the contact hole of the device;
11) completing the filling processing of the contact hole of the device by adopting a tungsten sputtering process and a tungsten chemical mechanical planarization process; sputtering an aluminum-silicon-copper film layer and finishing the etching processing of the metal connecting line.
2. The method of claim 1, wherein the method comprises the steps of: the impurities are P-type impurities or N-type impurities.
3. The method of claim 1 or 2, wherein the method further comprises the step of: forming a shielding protective layer on the surface of the area uncovered by the field oxide layer; and removing the shielding protective layer before forming a gate oxide layer in the area uncovered by the field oxide layer.
4. The method of claim 1, wherein the method comprises the steps of: before the polycrystalline resistor layer is formed, the shielding protection layer and the field oxide layer are cleaned.
5. The method of claim 1, wherein the method comprises the steps of: and cleaning the oxide layer on the resistor polycrystalline strip before forming the second dielectric layer.
6. The method of claim 1, wherein the method comprises the steps of: and etching the second dielectric layer by adopting a dry etching process to form the omega-shaped or pi-shaped silicon nitride dielectric layer.
7. The method of claim 1, wherein the method comprises the steps of: n ═ 4500,6000; m ═ 1500,2000; l ═ 80,100; h ═ 250,350; r1 ═ 2700,4300; r2 ═ 500,700; t is less than or equal to 200.
8. The integrated polycrystalline resistor module obtained by the integration method of the double-gate oxide high-low voltage CMOS process compatible low-temperature coefficient polycrystalline resistor module according to any one of claims 1 to 7, which is characterized by comprising a substrate, a well, a field oxide layer, a polycrystalline resistor layer, a dielectric layer, a thick gate oxide layer, a thin gate oxide layer and a polycrystalline silicon gate;
the substrate is positioned at the bottom; the trap is formed on the surface of the substrate;
the field oxide layer is formed on the surface of the trap;
the field oxide layer comprises a high-voltage device region, a medium-voltage device region and a low-voltage device region;
the high-voltage device region and the medium-voltage device region are provided with thick gate oxide layers;
a thin gate oxide layer is arranged in the low-voltage device area;
the polycrystalline resistance layer is formed on the surface of the field oxide layer;
the dielectric layer is formed on the surface of the polycrystalline resistance layer;
and a polysilicon gate of the MOS tube is constructed on the thick gate oxide layer and the thin gate oxide layer.
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| CN113380799B (en) * | 2021-05-28 | 2022-06-14 | 重庆中科渝芯电子有限公司 | Low dislocation density high reliability high and low voltage CMOS self-aligned double-well process and device |
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| CN1051879C (en) * | 1997-12-08 | 2000-04-26 | 中国科学院上海冶金研究所 | Double-layered polycrystal CMOS hybrid digital-analog integrated circuit and its manufacture |
| JP4976624B2 (en) * | 2000-09-01 | 2012-07-18 | セイコーインスツル株式会社 | Complementary MOS semiconductor device and manufacturing method thereof |
| JP4865152B2 (en) * | 2001-06-19 | 2012-02-01 | セイコーインスツル株式会社 | Manufacturing method of semiconductor device |
| US8580631B2 (en) * | 2010-10-25 | 2013-11-12 | Texas Instruments Incorporated | High sheet resistor in CMOS flow |
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