CN105185721B - A kind of process that pin grid array is made on ceramic substrate - Google Patents

A kind of process that pin grid array is made on ceramic substrate Download PDF

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CN105185721B
CN105185721B CN201510493261.6A CN201510493261A CN105185721B CN 105185721 B CN105185721 B CN 105185721B CN 201510493261 A CN201510493261 A CN 201510493261A CN 105185721 B CN105185721 B CN 105185721B
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pga
eutectic
type lead
pin type
substrates
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CN105185721A (en
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周冬莲
王啸
何中伟
金龙
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No 214 Institute of China North Industries Group Corp
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China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)

Abstract

The invention discloses a kind of process that pin grid array is made on ceramic substrate, comprise the following steps：PGA substrates are made using thick film film forming or LTCC；Using Au base eutectic solder pieces as pin type lead welding material；From gilding can be cut down as pin type lead material；The welding of pin type lead and PGA substrates is realized using Vacuum Eutectic soldering method.The method of the present invention, technique is simple, and flexibly, material cost is relatively low, is adapted to be pilot processing；Weld layer bonding strength is high；Weld layer resistance, thermal resistance all very littles, good conductivity, heat conduction are fast；Good environmental adaptability, mechanical resistant fatigue and cool-hot fatigue, creep resistant, long-term reliability are high.

Description

A kind of process that pin grid array is made on ceramic substrate
Technical field
The present invention relates to the process for making pin grid array, more particularly to one kind to make pin grid array on ceramic substrate Process.
Background technology
Pin grid array（PGA）Encapsulation technology is a branch of microelectronic packaging technology, and traditional chip package is periphery Pin configuration, PGA encapsulation is face battle array pin configuration.Its advantage is：
1）There is more I/O numbers and lower lead-in inductance, the electric capacity and dry sound of signal than conventional package；
2）Integrated air-tight packaging structure can be realized, there is high reliability, be usually used in highly reliable and high-end field.
At present, PGA package leads preparation method is realized using Au parent metal cream materials and belt soldering oven in industry.Its hand The similar conventional SMT techniques of section.Shortcoming is：
1）The Au parent metal cream material sources of goods are in short supply, and market purchasing is difficult；
2）Au parent metals cream is adapted to typical products in mass production processing, too high for small batch Product processing, material cost；
3）Belt soldering oven welding surroundings control difficulty is high, and welding interval is grown, and welding quality is difficult to meet to require.Therefore, Up to the present, PGA leads reliability is still the difficult problems that industry technology personnel need to solve.
The content of the invention
The technical problems to be solved by the invention are the defects of overcoming prior art, there is provided one kind makes on ceramic substrate The process of pin grid array.
In order to solve the above technical problems, the present invention provides a kind of process that pin grid array is made on ceramic substrate, It is characterized in that comprise the following steps：
PGA substrates are made using thick film film forming or LTCC；
Using Au base eutectic solder pieces as pin type lead welding material；
From gilding can be cut down as pin type lead material；
The welding of pin type lead and PGA substrates is realized using Vacuum Eutectic soldering method.
PGA substrates are substrate for film deposition or ltcc substrate.
Pad is also welded with PGA substrates, welding step is as follows：
a1）Welding zone solder sheet being placed into by the method for manually or automatically bonding die on PGA substrates；
a2）A ceramic tabletting in pressure in solder sheet；
a3）PGA substrates and ceramic tabletting with solder sheet are together placed into the heating plate in Vacuum Eutectic brazier, PGA substrates contact the heating plate of Vacuum Eutectic brazier；
a4）Welded according to the eutectic welding curve of setting, one layer of eutectic solder is formed on the pad of PGA substrates Layer.
The welding step of pin type lead and PGA substrates is as follows：
b1）Pin type lead is sequentially inserted into the lead guide hole that array arranges in graphite locating slot；
b2）The PGA substrates press-in of upper eutectic solder layer is plugged in the graphite locating slot of pin type lead, on PGA substrates Pad withstand the ailhead of each pin type lead correspondingly, form weld assembly；
b3）Weld assembly is placed in the heating plate in Vacuum Eutectic brazier, PGA real estates and contact heater plate；
b4）In graphite top surface plus pressurization briquetting；
5）Welded according to the eutectic welding curve of setting, pin type lead is welded on PGA substrates.
The eutectic welding curve includes following several stages：
1. stage time t1~t2：Under room temperature environment, vacuumize, inflated with nitrogen；
2. stage time t2~t5：Temperature T3 is warming up to 45 DEG C/min speed, and after being vacuumized since temperature T2 Again plus formic acid；Wherein, T3>T2>Room temperature；
3. stage time t5~t6：60s~90s is incubated under temperature T3；
4. stage time t6~t7：Temperature T4, T4 are warming up to 45 DEG C/min speed>T3；
5. stage time t7~t8：In temperature T4 and fill 60s~120s is incubated under formic acid environment；
6. stage time t8~t9：Vacuumize and be incubated 60s~120s；
7. stage time t9~t10：Inflated with nitrogen, it is cooled to room temperature.
Temperature T2=150 DEG C~170 DEG C.
Temperature T3=solder sheet eutectic point-(20 DEG C~30 DEG C).
It is characterized in that temperature T4=solder eutectic point+(30 DEG C~50 DEG C).
The beneficial effect that the present invention is reached：
1）Technique is simple, and flexibly, material cost is relatively low, is adapted to be pilot processing；
2) weld layer bonding strength is high；
3) weld layer resistance, thermal resistance all very littles, good conductivity, heat conduction are fast；
4) good environmental adaptability, mechanical resistant fatigue and cool-hot fatigue, creep resistant, long-term reliability are high.
Brief description of the drawings
Fig. 1 is the process chart of the present invention；
Fig. 2 is technological operation schematic diagram；
Fig. 3 is eutectic welding curve map；
Fig. 4 is eutectic welding clamp schematic diagram.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following examples are only used for clearly illustrating the present invention Technical scheme, and can not be limited the scope of the invention with this.
1 technical scheme, as shown in figure 1,
1) burnt altogether using thick film film forming or low-temp ceramics（LTCC）Make PGA substrate for film deposition；
2）Using Au base eutectic solder pieces（Weld tabs）As pin type lead welding material；
3）From gilding can be cut down as pin type lead material；
4）Realize that pin type lead welds with PGA substrate for film deposition using Vacuum Eutectic soldering method.
2 key process parameters and control of material
2.1 PGA substrate manufacture techniques
PGA substrates are substrate for film deposition either ltcc substrates.
Substrate for film deposition defines：By the upper screen mesh of mask to print plate, thick film ink is equably deposited into 96%Al2O3 On substrate, then sintered by peak temperature for 850 DEG C of environment and form the thick film substrate with certain thickness and shape.
Ltcc substrate defines：By the upper screen mesh of mask to print plate, thick film ink is equably deposited into ceramic chips On, then by the ceramic chips of multilayered printed figure by the processes such as lamination, lamination, sintering formation ltcc substrate.
a）Material
1）Substrate：96% Al2O3Ceramics, thickness are >=1.0mm；Or Dupont951 greens（Or the suitable green of performance）, More than 10 layers.
2）PGA pad conductors：The thick film conductor paste of DUPONT-5081/5082 or suitable performances；Or DUPONT- Chemical plating applies Ni/Pd/Au on 6118 conductors.
b）Substrate size
1）Thickness（t1）≥1.0mm；
2) length（L1）≥10.0mm；
3）Width（W1）≥10.0mm.
c）PGA pad sizes
1）Pad pitch：2.54mm；
2）Pad diameter：1.8mm~2.0mm；
3）Mask open：1.4mm~1.8mm.
d）Technological parameter
1）DUPONT-5081/5082 sinters thickness >=50 μm；
2）DUPONT-6118 sinters thickness >=15 μm；
3）Electroless Plating Ni/Pd/Au thickness：4μm/0.1μm/0.1μm.
2.2 Vacuum Eutectic Weldings
Technological operation illustrates（See Fig. 2）
a）The pre- upper solder of PGA pads
1）Preformed soldering is placed into PGA welding zones by the method for manually or automatically bonding die（PGA welding zones can also upper one Thin layer paste soldering flux）；
2）Ceramic tabletting in pressure（Purpose is fixed weld tabs and pressurization）；
3）By in the horizontal positioned brazier to Vacuum Eutectic of weldment（PGA substrates contact eutectic furnace heating plate）；
4）Set eutectic welding curve（Fig. 3）, start to weld, pad formed on PGA substrates.
b）PGA leads eutectic welds
1）Pin type lead is sequentially inserted into the lead guide hole that array arranges in graphite locating slot；
2）The PGA substrates of first-class solder are pressed into the graphite locating slot for being plugged pin type lead, the weldering on PGA substrates Disk withstands the ailhead of each pin type lead correspondingly, forms weld assembly；
3）Weld assembly is lain in a horizontal plane in Vacuum Eutectic brazier heating plate, PGA real estates and contact heater plate；
4）In graphite locating slot top surface plus pressurization briquetting, it is pressed on PGA substrates；
5）Set eutectic welding curve（Fig. 3）, start to weld, pin type lead be welded on PGA substrates.
c）Technological parameter
1）Weld curve（See Fig. 3）；
1. t1~t2 stages：Under room temperature environment, vacuumize for 2~3 times, 1~2 inflated with nitrogen N2；
2. t2~t5 stages：T3 is warming up to 45 DEG C/min speed, vacuumized since T2, then adds formic acid HCOOH；And T3>T2>Room temperature；It is preferred that T3=solder eutectic point-(20 DEG C~30 DEG C), T2=150 DEG C~170 DEG C；
3. t5~t6 stages：60s~90s is incubated at a temperature of T3；
4. t6~t7 stages：T4T4 is warming up to 45 DEG C/min speed>T3；It is preferred that T4=solder eutectic point+(30 DEG C~50 DEG C)；
5. t7~t8 stages：60s~120s is incubated at a temperature of T4；
6. t8~t9 stages：Vacuumize and be incubated 60s~120s；
7. t9~t10 stages：Inflated with nitrogen N2, is cooled to room temperature.
2）Pressurization：
1. the pre- upper solder stage：0.2gf/mm2~0.3gf/mm2；
2. lead welds the stage：0.4gf/mm2~0.6gf/mm2。
2.3 pin type leads
a）Material：Kovar alloy（4J29）, surface plating Ni/Au.
b）Size：, main diameter is 0.45 ± 0.05mm；1.0 ± 0.05mm of diameter of ailhead, height 0.25 ± 0.05mm；Pin type total lead length t1（The mm of the mm of t1=6.0~9.0）.
c）Plating applies：Ni/Au, 2.8 μm~8.9 μm/0.1 μm~0.5 μm.
2.4 Au base preformed solder pieces
a）Material：Au80Sn20 or Au88Ge12；
b）Size：It is identical with pad mask opening size；
c）Thickness：50 μm~100 μm.
2.5 eutectic welding clamps（See Fig. 4）
a）Material：High purity graphite；
b）Size：
1）Graphite block thickness（t2）：T2=8.0mm~10.0mm；
2）Clamping slot depth（t3）：t3=t1+（0.1mm~0.3mm）
3）Position flute length（L2）：L2=L1+0.1mm
4）Position groove width（W2）：W2=W1+0.1mm
5）Lead guide hole diameter：0.6mm~0.7mm；
6）Lead guide hole depth：Through whole graphite block thickness.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, without departing from the technical principles of the invention, some improvement and deformation can also be made, these are improved and deformation Also it should be regarded as protection scope of the present invention.

Claims (7)

1. a kind of process that pin grid array is made on ceramic substrate, it is characterized in that, comprise the following steps：
PGA substrates are made using thick film film forming or LTCC；
Using Au base eutectic solder pieces as pin type lead welding material；
From gilding can be cut down as pin type lead material；
The welding of pin type lead and PGA substrates is realized using Vacuum Eutectic soldering method；
Pad is also welded with PGA substrates, welding step is as follows：
a1）Welding zone solder sheet being placed into by the method for manually or automatically bonding die on PGA substrates；
a2）A ceramic tabletting in pressure in solder sheet；
a3）PGA substrates and ceramic tabletting with solder sheet are together placed into the heating plate in Vacuum Eutectic brazier, PGA bases Plate contacts the heating plate of Vacuum Eutectic brazier；
a4）Welded according to the eutectic welding curve of setting, one layer of eutectic solder layer is formed on the pad of PGA substrates.
2. the process according to claim 1 that pin grid array is made on ceramic substrate, it is characterized in that, PGA substrates For substrate for film deposition or ltcc substrate.
3. the process according to claim 1 that pin grid array is made on ceramic substrate, it is characterized in that, pin type lead It is as follows with the welding step of PGA substrates：
b1）Pin type lead is sequentially inserted into the lead guide hole that array arranges in graphite locating slot；
b2）The PGA substrates press-in of upper eutectic solder layer is plugged in the graphite locating slot of pin type lead, the weldering on PGA substrates Disk withstands the ailhead of each pin type lead correspondingly, forms weld assembly；
b3）Weld assembly is placed in the heating plate in Vacuum Eutectic brazier, PGA real estates and contact heater plate；
b4）In graphite top surface plus pressurization briquetting；
5）Welded according to the eutectic welding curve of setting, pin type lead is welded on PGA substrates.
4. the process that pin grid array is made on ceramic substrate according to claim 1 or 3, it is characterized in that, it is described Eutectic welding curve includes following several stages：
1. stage time t1~t2：Under room temperature environment, vacuumize, inflated with nitrogen；
2. stage time t2~t5：Temperature T3 is warming up to 45 DEG C/min speed, and added again after being vacuumized since temperature T2 Formic acid；Wherein, T3>T2>Room temperature；
3. stage time t5~t6：60s~90s is incubated under temperature T3；
4. stage time t6~t7：Temperature T4, T4 are warming up to 45 DEG C/min speed>T3；
5. stage time t7~t8：In temperature T4 and fill 60s~120s is incubated under formic acid environment；
6. stage time t8~t9：Vacuumize and be incubated 60s~120s；
7. stage time t9~t10：Inflated with nitrogen, it is cooled to room temperature.
5. the process according to claim 4 that pin grid array is made on ceramic substrate, it is characterized in that, temperature T2= 150 DEG C~170 DEG C.
6. the process according to claim 4 that pin grid array is made on ceramic substrate, it is characterized in that, temperature T3= Solder sheet eutectic point-(20 DEG C~30 DEG C).
7. the process according to claim 4 that pin grid array is made on ceramic substrate, it is characterized in that, temperature T4= Solder eutectic point+(30 DEG C~50 DEG C).
CN201510493261.6A 2015-08-13 2015-08-13 A kind of process that pin grid array is made on ceramic substrate Active CN105185721B (en)

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CN109877439A (en) * 2019-04-04 2019-06-14 中国电子科技集团公司第五十八研究所 A kind of outer lead shaping jig and welding method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097334A (en) * 2009-12-14 2011-06-15 日本特殊陶业株式会社 Manufacture method for wiring board and stitch arrangement device
CN102151927A (en) * 2010-12-16 2011-08-17 无锡中微高科电子有限公司 Welding method for welding columns of encapsulated integrated circuit (IC)

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KR100216844B1 (en) * 1996-12-27 1999-09-01 김규현 Chip scale package of structure of pin grid array type and method manufacture
CN102064159B (en) * 2010-11-05 2013-09-18 中国兵器工业集团第二一四研究所苏州研发中心 Multi-module packaged component
US8952540B2 (en) * 2011-06-30 2015-02-10 Intel Corporation In situ-built pin-grid arrays for coreless substrates, and methods of making same
CN103456699B (en) * 2013-09-29 2016-03-30 中国兵器工业集团第二一四研究所苏州研发中心 Integrated circuit package structure and method for packing thereof
CN103489847B (en) * 2013-10-11 2016-05-18 中国电子科技集团公司第四十三研究所 A kind of PGA/BGA three-dimensional structure for components and parts assembling and preparation method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097334A (en) * 2009-12-14 2011-06-15 日本特殊陶业株式会社 Manufacture method for wiring board and stitch arrangement device
CN102151927A (en) * 2010-12-16 2011-08-17 无锡中微高科电子有限公司 Welding method for welding columns of encapsulated integrated circuit (IC)

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