CN105185721A - Technological method for making pin grid array on ceramic substrate - Google Patents

Technological method for making pin grid array on ceramic substrate Download PDF

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Publication number
CN105185721A
CN105185721A CN201510493261.6A CN201510493261A CN105185721A CN 105185721 A CN105185721 A CN 105185721A CN 201510493261 A CN201510493261 A CN 201510493261A CN 105185721 A CN105185721 A CN 105185721A
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Prior art keywords
substrate
pga
eutectic
welding
grid array
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CN201510493261.6A
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Chinese (zh)
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CN105185721B (en
Inventor
周冬莲
王啸
何中伟
金龙
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Huadong Photoelectric Integrated Device Research Institute
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China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors

Abstract

The invention discloses a technological method for making a pin grid array on a ceramic substrate, comprising the steps as follows: making a PGA substrate with thick film forming or low-temperature co-firing ceramic; adopting Au-based eutectic solder pieces as a pin lead welding material; selecting a kovar gold-plated material as a pin lead material; and welding a pin lead to the PGA substrate through a vacuum eutectic welding method. The method of the invention is simple in process and flexible, lowers the cost of materials, and is suitable for processing a small batch of products. The connecting strength of a welding layer is high. The resistance and thermal resistance of the welding layer are small, the electrical conductivity is good, and heat conduction is fast. The welding layer is highly adaptable to the environment, is resistant to mechanical fatigue and cold and hot fatigue and resistant to creep, and has high long-term reliability.

Description

A kind of process making pin grid array on ceramic substrate
Technical field
The present invention relates to the process making pin grid array, particularly relate to a kind of process making pin grid array on ceramic substrate.
Background technology
Pin grid array (PGA) encapsulation technology is a branch of microelectronic packaging technology, and traditional chip package is perimeter leads structure, and PGA encapsulation is face battle array pin configuration.Its advantage is:
1) than conventional package, there is more I/O number and the dry sound of lower lead-in inductance, electric capacity and signal;
2) integrated air-tight packaging structure can be realized, there is high reliability, be usually used in highly reliable and high-end field.
At present, in industry, PGA package lead manufacture method adopts Au parent metal cream material and belt soldering oven to realize.The SMT technique of the similar routine of its means.Shortcoming is:
1) the Au parent metal cream material source of goods is in short supply, market purchasing difficulty;
2) Au parent metal cream is applicable to typical products in mass production processing, and for small batch Product processing, material cost is too high;
3) belt soldering oven welding surroundings control difficulty is high, and welding cycle is long, and welding quality is difficult to meet the demands.Therefore, up to the present, PGA lead-in wire reliability is still the difficult problems that industry technology personnel need to solve.
Summary of the invention
Technical problem to be solved by this invention is the defect overcoming prior art, provides a kind of process making pin grid array on ceramic substrate.
For solving the problems of the technologies described above, the invention provides a kind of process making pin grid array on ceramic substrate, it is characterized in that, comprise the following steps:
Thick film film forming or LTCC is adopted to make PGA substrate;
Adopt Au base eutectic solder sheet as pin type wire bonds material;
Select and can cut down gilding as pin type lead material;
Vacuum Eutectic soldering method is adopted to realize welding of pin type lead-in wire and PGA substrate.
PGA substrate is substrate for film deposition or ltcc substrate.
PGA substrate is also welded with pad, and welding step is as follows:
A1) solder sheet is placed into the welding zone on PGA substrate by method that is manual or bonding die automatically;
A2) in solder sheet, press a ceramic compressing tablet;
A3) be together placed on the heating plate in Vacuum Eutectic brazier with the PGA substrate of solder sheet and ceramic compressing tablet, the heating plate of PGA substrate contacts Vacuum Eutectic brazier;
A4) weld according to the eutectic welding curve arranged, the pad of PGA substrate is formed one deck eutectic solder layer.
Pin type lead-in wire is as follows with the welding step of PGA substrate:
B1) pin type lead-in wire is inserted in the lead-in wire guide hole of arrayed in graphite location notch successively;
B2) be plugged in the graphite location notch of pin type lead-in wire by the PGA substrate press-in of going up eutectic solder layer, the pad on PGA substrate withstands the ailhead of each pin type lead-in wire correspondingly, forms weld assembly;
B3) be placed on by weld assembly on the heating plate in Vacuum Eutectic brazier, PGA real estate contacts with heating plate;
B4) pressurization briquetting is added at graphite end face;
5) weld according to the eutectic welding curve arranged, make pin type wire bonds on PGA substrate.
Described eutectic welding curve comprises following several stages:
1. time t1 ~ t2 stage: under room temperature environment, to vacuumize, inflated with nitrogen;
2. time t2 ~ t5 stage: with the ramp of 45 DEG C/min to temperature T3, and add formic acid again after vacuumizing from temperature T2; Wherein, T3>T2> room temperature;
3. time t5 ~ t6 stage: be incubated 60s ~ 90s under temperature T3;
4. time t6 ~ t7 stage: with the ramp of 45 DEG C/min to temperature T4, T4>T3;
5. time t7 ~ t8 stage: be incubated 60s ~ 120s at temperature T4 with under filling formic acid environment;
6. time t8 ~ t9 stage: vacuumize and be incubated 60s ~ 120s;
7. time t9 ~ t10 stage: inflated with nitrogen, is cooled to room temperature.
Temperature T2=150 DEG C ~ 170 DEG C.
Temperature T3=solder sheet eutectic point-(20 DEG C ~ 30 DEG C).
It is characterized in that, temperature T4=solder eutectic point+(30 DEG C ~ 50 DEG C).
The beneficial effect that the present invention reaches:
1) technique is simple, and flexibly, material cost is lower, is applicable to pilot processing;
2) weld layer bonding strength is high;
3) weld layer resistance, thermal resistance are all very little, and good conductivity, heat conduction are fast;
4) good environmental adaptability, mechanical resistant fatigue and cool-hot fatigue, creep resistant, long-term reliability is high.
Accompanying drawing explanation
Fig. 1 is process chart of the present invention;
Fig. 2 is technological operation schematic diagram;
Fig. 3 is eutectic welding curve chart;
Fig. 4 is eutectic welding clamp schematic diagram.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.Following examples only for technical scheme of the present invention is clearly described, and can not limit the scope of the invention with this.
1 technical scheme, as shown in Figure 1,
1) adopt thick film film forming or low-temp ceramics to burn (LTCC) altogether and make PGA substrate for film deposition;
2) adopt Au base eutectic solder sheet (weld tabs) as pin type wire bonds material;
3) select and can cut down gilding as pin type lead material;
4) adopt Vacuum Eutectic soldering method to realize pin type lead-in wire to weld with PGA substrate for film deposition.
2 key process parameters and control of material
2.1PGA substrate manufacture technique
PGA substrate is substrate for film deposition or ltcc substrate.
Substrate for film deposition defines: by the upper screen mesh of mask to print plate, thick film ink is deposited to 96%Al equably 2o 3on substrate, then be that 850 DEG C of environment sintering form the thick film substrate with certain thickness and shape through peak temperature.
Ltcc substrate defines: by the upper screen mesh of mask to print plate, deposited on ceramic chips equably by thick film ink, then the ceramic chips of multilayered printed figure is formed ltcc substrate through operations such as lamination, lamination, sintering.
A) material
1) substrate: 96%Al 2o 3pottery, thickness is>=1.0mm; Or, Dupont951 green (or the suitable green of performance), more than 10 layers.
2) thick film conductor paste of PGA pad conductor: DUPONT-5081/5082 or suitable performance; Or chemical plating is coated with Ni/Pd/Au on DUPONT-6118 conductor.
B) substrate size
1) thickness (t1) >=1.0mm;
2) length (L1) >=10.0mm;
3) width (W1) >=10.0mm.
C) PGA pad size
1) pad pitch: 2.54mm;
2) pad diameter: 1.8mm ~ 2.0mm;
3) mask open: 1.4mm ~ 1.8mm.
D) technological parameter
1) DUPONT-5081/5082 sinters thickness >=50 μm;
2) DUPONT-6118 sinters thickness >=15 μm;
3) Electroless Plating Ni/Pd/Au thickness: 4 μm/0.1 μm/0.1 μm.
2.2 Vacuum Eutectic Weldings
Technological operation diagram (see figure 2)
A) PGA pad goes up solder in advance
1) preformed soldering is placed into PGA welding zone (PGA welding zone also can above skim paste soldering flux) by method that is manual or bonding die automatically;
2) ceramic compressing tablet (object is fixing weld tabs and pressurization) is pressed;
3) by weldment horizontal positioned to (PGA substrate contacts eutectic furnace heating plate) in Vacuum Eutectic brazier;
4) set eutectic welding curve (Fig. 3), start welding, PGA substrate forms pad.
B) PGA lead-in wire eutectic welding
1) pin type lead-in wire is inserted in the lead-in wire guide hole of arrayed in graphite location notch successively;
2) be pressed into by the PGA substrate of first-class solder in the graphite location notch being plugged pin type lead-in wire, the pad on PGA substrate withstands the ailhead of each pin type lead-in wire correspondingly, forms weld assembly;
3) lain in a horizontal plane in by weld assembly on Vacuum Eutectic brazier heating plate, PGA real estate contacts with heating plate;
4) add pressurization briquetting at graphite location notch end face, be pressed on PGA substrate;
5) set eutectic welding curve (Fig. 3), start welding, by pin type wire bonds on PGA substrate.
C) technological parameter
1) curve (see figure 3) is welded;
1. in t1 ~ t2 stage: under room temperature environment, to vacuumize for 2 ~ 3 times, 1 ~ 2 inflated with nitrogen N 2;
2. ~ t5 stage: with the ramp of 45 DEG C/min to T3, vacuumize from T2, then add formic acid HCOOH; And T3>T2> room temperature; Preferably, T3=solder eutectic point-(20 DEG C ~ 30 DEG C), T2=150 DEG C ~ 170 DEG C;
3. t5 ~ t6 stage: be incubated 60s ~ 90s at T3 temperature;
4. t6 ~ t7 stage: with the ramp of 45 DEG C/min to T4T4>T3; Preferably, T4=solder eutectic point+(30 DEG C ~ 50 DEG C);
5. t7 ~ t8 stage: be incubated 60s ~ 120s at T4 temperature;
6. t8 ~ t9 stage: vacuumize and be incubated 60s ~ 120s;
7. t9 ~ t10 stage: inflated with nitrogen N2, is cooled to room temperature.
2) pressurize:
1. the solder stage is gone up in advance: 0.2gf/mm 2~ 0.3gf/mm 2;
2. wire bonds stage: 0.4gf/mm 2~ 0.6gf/mm 2.
2.3 pin type lead-in wires
A) material: kovar alloy (4J29), plated surface Ni/Au.
B) size:, main diameter is 0.45 ± 0.05mm; Diameter 1.0 ± the 0.05mm of ailhead, height 0.25 ± 0.05mm; Pin type total lead length t1(t1=6.0mm ~ 9.0mm).
C) plating is coated with: Ni/Au, 2.8 μm ~ 8.9 μm/0.1 μm ~ 0.5 μm.
2.4Au base preformed solder sheet
A) material: Au80Sn20 or Au88Ge12;
B) size: identical with pad mask opening size;
C) thickness: 50 μm ~ 100 μm.
2.5 eutectic welding clamp (see figure 4)s
A) material: high purity graphite;
B) size:
1) graphite block thickness (t2): t2=8.0mm ~ 10.0mm;
2) clamping slot depth (t3): t3=t1+(0.1mm ~ 0.3mm)
3) flute length (L2) is located: L2=L1+0.1mm
4) groove width (W2) is located: W2=W1+0.1mm
5) go between guide hole diameter: 0.6mm ~ 0.7mm;
6) go between the guide hole degree of depth: run through whole graphite block thickness.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the technology of the present invention principle; can also make some improvement and distortion, these improve and distortion also should be considered as protection scope of the present invention.

Claims (8)

1. on ceramic substrate, make a process for pin grid array, it is characterized in that, comprise the following steps:
Thick film film forming or LTCC is adopted to make PGA substrate;
Adopt Au base eutectic solder sheet as pin type wire bonds material;
Select and can cut down gilding as pin type lead material;
Vacuum Eutectic soldering method is adopted to realize welding of pin type lead-in wire and PGA substrate.
2. the process making pin grid array on ceramic substrate according to claim 1, is characterized in that, PGA substrate is substrate for film deposition or ltcc substrate.
3. the process making pin grid array on ceramic substrate according to claim 1, is characterized in that, PGA substrate is also welded with pad, and welding step is as follows:
A1) solder sheet is placed into the welding zone on PGA substrate by method that is manual or bonding die automatically;
A2) in solder sheet, press a ceramic compressing tablet;
A3) be together placed on the heating plate in Vacuum Eutectic brazier with the PGA substrate of solder sheet and ceramic compressing tablet, the heating plate of PGA substrate contacts Vacuum Eutectic brazier;
A4) weld according to the eutectic welding curve arranged, the pad of PGA substrate is formed one deck eutectic solder layer.
4. the process making pin grid array on ceramic substrate according to claim 3, is characterized in that, pin type lead-in wire is as follows with the welding step of PGA substrate:
B1) pin type lead-in wire is inserted in the lead-in wire guide hole of arrayed in graphite location notch successively;
B2) be plugged in the graphite location notch of pin type lead-in wire by the PGA substrate press-in of going up eutectic solder layer, the pad on PGA substrate withstands the ailhead of each pin type lead-in wire correspondingly, forms weld assembly;
B3) be placed on by weld assembly on the heating plate in Vacuum Eutectic brazier, PGA real estate contacts with heating plate;
B4) pressurization briquetting is added at graphite end face;
5) weld according to the eutectic welding curve arranged, make pin type wire bonds on PGA substrate.
5. the process making pin grid array on ceramic substrate according to claim 3 or 4, is characterized in that, described eutectic welding curve comprises following several stages:
1. time t1 ~ t2 stage: under room temperature environment, to vacuumize, inflated with nitrogen;
2. time t2 ~ t5 stage: with the ramp of 45 DEG C/min to temperature T3, and add formic acid again after vacuumizing from temperature T2; Wherein, T3>T2> room temperature;
3. time t5 ~ t6 stage: be incubated 60s ~ 90s under temperature T3;
4. time t6 ~ t7 stage: with the ramp of 45 DEG C/min to temperature T4, T4>T3;
5. time t7 ~ t8 stage: be incubated 60s ~ 120s at temperature T4 with under filling formic acid environment;
6. time t8 ~ t9 stage: vacuumize and be incubated 60s ~ 120s;
7. time t9 ~ t10 stage: inflated with nitrogen, is cooled to room temperature.
6. the process making pin grid array on ceramic substrate according to claim 5, is characterized in that, temperature T2=150 DEG C ~ 170 DEG C.
7. the process making pin grid array on ceramic substrate according to claim 5, is characterized in that, temperature T3=solder sheet eutectic point-(20 DEG C ~ 30 DEG C).
8. the process making pin grid array on ceramic substrate according to claim 5, is characterized in that, temperature T4=solder eutectic point+(30 DEG C ~ 50 DEG C).
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109877439A (en) * 2019-04-04 2019-06-14 中国电子科技集团公司第五十八研究所 A kind of outer lead shaping jig and welding method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100216844B1 (en) * 1996-12-27 1999-09-01 김규현 Chip scale package of structure of pin grid array type and method manufacture
CN102064159A (en) * 2010-11-05 2011-05-18 中国兵器工业集团第二一四研究所苏州研发中心 Multi-module packaged component
CN102097334A (en) * 2009-12-14 2011-06-15 日本特殊陶业株式会社 Manufacture method for wiring board and stitch arrangement device
CN102151927A (en) * 2010-12-16 2011-08-17 无锡中微高科电子有限公司 Welding method for welding columns of encapsulated integrated circuit (IC)
CN103456699A (en) * 2013-09-29 2013-12-18 中国兵器工业集团第二一四研究所苏州研发中心 Integrated circuit packaging structure and packaging method thereof
CN103489847A (en) * 2013-10-11 2014-01-01 中国电子科技集团公司第四十三研究所 PGA/BGA (Pin Grid Array/Ball Grid Array) three-dimensional structure for assembling components and production method thereof
CN103620766A (en) * 2011-06-30 2014-03-05 英特尔公司 In situ-built pin-grid arrays for coreless substrates, and methods of making same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100216844B1 (en) * 1996-12-27 1999-09-01 김규현 Chip scale package of structure of pin grid array type and method manufacture
CN102097334A (en) * 2009-12-14 2011-06-15 日本特殊陶业株式会社 Manufacture method for wiring board and stitch arrangement device
CN102064159A (en) * 2010-11-05 2011-05-18 中国兵器工业集团第二一四研究所苏州研发中心 Multi-module packaged component
CN102151927A (en) * 2010-12-16 2011-08-17 无锡中微高科电子有限公司 Welding method for welding columns of encapsulated integrated circuit (IC)
CN103620766A (en) * 2011-06-30 2014-03-05 英特尔公司 In situ-built pin-grid arrays for coreless substrates, and methods of making same
CN103456699A (en) * 2013-09-29 2013-12-18 中国兵器工业集团第二一四研究所苏州研发中心 Integrated circuit packaging structure and packaging method thereof
CN103489847A (en) * 2013-10-11 2014-01-01 中国电子科技集团公司第四十三研究所 PGA/BGA (Pin Grid Array/Ball Grid Array) three-dimensional structure for assembling components and production method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109877439A (en) * 2019-04-04 2019-06-14 中国电子科技集团公司第五十八研究所 A kind of outer lead shaping jig and welding method

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