CN105161441A - Testing structure and method for optical correction of ion implantation in complementary metal oxide semiconductor (CMOS) device - Google Patents
Testing structure and method for optical correction of ion implantation in complementary metal oxide semiconductor (CMOS) device Download PDFInfo
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Abstract
The invention provides testing structure and method for optical correction of ion implantation in a complementary metal oxide semiconductor (CMOS) device. The prototype of a CMOS device wafer structure is reserved; the effects, for example, the size, the shape, the pattern density and the surrounding environment, on an ion implantation layer due to the CMOS environment can be really simulated; meanwhile, the electrical properties of the ion implantation layer can be tested through various test pins to relatively intuitively validate the optimization effect of the optical correction on the ion implantation layer, namely the effects on the isolation capability of the ion implantation layer due to the optical correction are monitored; and the adverse effects on optical correction of the ion implantation layer due to the pattern density of the domain are avoided.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of test structure for the correction of cmos device ion implantation optics and method.
Background technology
CMOS (Complementary Metal Oxide Semiconductor) (ComplementaryMetalOxideSemiconductor, CMOS) is the basis of modern semiconductors integrated circuit technique, the most elementary cell of composition digital integrated circuit.CMOS is a kind of organic assembling of nmos pass transistor and PMOS transistor, forms logical device, when its advantage is only there is logic state transition, just big current can be produced, and under stable logic state, only have minimum electric current to pass through, therefore, it is possible to significantly reduce the power consumption of logical circuit.
In CMOS manufacture process, ion implantation technology plays an important role, and performance, reliability etc. for device have conclusive impact.The main application of ion implantation comprise CMOS trap formation, adjusting thresholds injects, field is injected, source and drain is injected, isolation injection, material modification injection, the injection of SOI buried regions etc.Along with device size micro, need the performance controlling each device more accurately, increase gradually the technological requirement of ion implantation, the step of ion implantation increases thereupon, for ultra-shallow junctions inject and with layer repeatedly ion implantation become current main trend and challenge.
Ion implanted layer photoetching process is mainly used in the mask plate providing ion implantation, even if with photoresist as the shelter of ion implanted layer, make to carry out with photoresist covering the region of sheltering and wafer not needing ion implantation, meanwhile, the photoresist needed on the region of ion implantation is got rid of in development.Along with the continuous reduction of technology node, , ion implanted layer litho pattern live width critical size is more and more less, characteristic size is close to being even less than the optical wavelength used in photoetching process, the impact of the optical approach effect that the finite resolving power of optical system causes, figure on the mask plate caused is transferring to generation figure deviation after on wafer, special part of being mutually close at figure, due to optical interference and diffraction obvious, figure deviation can be relatively larger, such as in line segment top and figure corner, live width changes, corner sphering, the distortion such as line length shortening and deviation more obvious, directly affect device performance and product yield.In order to eliminate this error and impact, needing the optical approach effect correction (OpticalProximityCorrection, OPC) carrying out in advance to light mask pattern, making up optical approach effect.OPC is by revising on mask plate the figure that will be formed, and the figure deformation made up in photoetching process makes the figure transferred on wafer substantially meet with expection figure.
The method of traditional on-line monitoring ion implanted layer mask plate OPC correction effect is the critical size by monitoring the ion implantation plot structure in revised mask plate patterns, monitor the forecasting accuracy error of optical approach effect revision program to ion implantation layer pattern, when the forecasting inaccuracy of optical approach effect revision program is true, in time optical approach effect revision program parameter is adjusted, thus ensure OPC correction effect.But, along with the live width of ion implanted region is more and more less, spacing between the characteristic size (CD) of the mask plate patterns of ion implantation self and figure is constantly reduced, make the monitoring error of the critical size in mask plate patterns increasing, the requirement that the cmos device finally causing the method for this traditional on-line monitoring optics correction effect can not meet smaller szie manufactures.
Summary of the invention
The object of the present invention is to provide a kind of test structure for the correction of cmos device ion implantation optics and method, the effect of optimization of optics correction can be verified by electrology characteristic test result.
For solving the problem, the present invention proposes a kind of test structure for the correction of cmos device ion implantation optics, process structure basis, cmos device front road is formed, described cmos device front road process structure comprises formation NMOS tube active area in the substrate, PMOS active area, N-type ion implanted layer, P type ion implanted layer, described test structure comprises: first test pin of drawing from NMOS tube active area, from the second test pin that P type ion implanted layer is drawn, 3rd test pin of drawing from PMOS active area, and from the 4th test pin that N-type ion implanted layer is drawn, when testing the isolating power of described P type ion implanted layer, the first test pin connects positive potential, the 4th test pin connecting to neutral current potential, and when testing the isolating power of described N-type ion implanted layer, the 3rd test pin connects negative potential, the second test pin connecting to neutral current potential.
Further, the ion implantation of described N-type ion implanted layer is that the trap of N-type ion injects, adjusting thresholds injects, field is injected, source and drain is injected, isolation is injected, material modification injects or SOI buried regions injects, the ion implantation of described P type ion implanted layer be P type ion trap injects, adjusting thresholds injects, field is injected, source and drain is injected, isolation is injected, material modification injects or SOI buried regions injects.
Further, described cmos device is SRAM, and described cmos device is SRAM, and described NMOS tube active area comprises the active area of pull-down NMOS pipe and the active area of transmission gate NMOS tube, and described PMOS active area comprises the active area of pull-up PMOS.
Further, the first test pin, the second test pin, the 3rd test pin and each test pin of the 4th test pin are all drawn by through hole and metal lead wire.
The present invention also proposes a kind of method of testing for the correction of cmos device ion implantation optics, comprising:
There is provided the cmos device that has a front road process structure, described front road process structure comprises formation NMOS tube active area in the substrate, PMOS active area, N-type ion implanted layer, P type ion implanted layer;
Draw the first test pin from described NMOS tube active area, from the second test pin that described P type ion implanted layer is drawn, draw the 3rd test pin from described PMOS active area, draw the 4th test pin from described N-type ion implanted layer;
Optics correction is carried out to ion implanted layer corresponding in described cmos device, optics correction is optimized simultaneously, comprise: the first test pin is connect positive potential, 4th test pin connecting to neutral current potential, monitor the isolating power of described P type ion implanted layer, to be optimized the optics correction of described P type ion implanted layer; And/or the 3rd test pin is connect negative potential, and the second test pin connecting to neutral current potential, monitors the isolating power of described N-type ion implanted layer, to be optimized the optics correction of described N-type ion implanted layer.
Further, if the leakage current between the first test pin and the 4th test pin is less than the first set point, then the forecasting accuracy of the optics correction of described P type ion implanted layer reaches technological requirement; If the leakage current between the second test pin and the 3rd test pin is less than the second set point, then the prediction of the optics correction of described N-type ion implanted layer accurately reaches technological requirement.
Further, the ion implantation of described N-type ion implanted layer is that the trap of N-type ion injects, adjusting thresholds injects, field is injected, source and drain is injected, isolation is injected, material modification injects or SOI buried regions injects, the ion implantation of described P type ion implanted layer be P type ion trap injects, adjusting thresholds injects, field is injected, source and drain is injected, isolation is injected, material modification injects or SOI buried regions injects.
Further, described cmos device is SRAM, described cmos device is SRAM, described NMOS tube active area comprises the active area of pull-down NMOS pipe and the active area of transmission gate NMOS tube, described PMOS active area comprises the active area of pull-up PMOS, described N-type ion implanted layer is N trap, and described P type sheath is P trap.
Further, the first test pin, the second test pin, the 3rd test pin and each test pin of the 4th test pin are all drawn by through hole and metal lead wire.
Compared with prior art, test structure for the correction of cmos device ion implantation optics provided by the invention and method, remain the prototype of cmos device crystal circle structure, can truly analog cmos environment on the impact of ion implanted layer, such as: size, shape, pattern density, surrounding enviroment etc., the electrology characteristic of test ion implanted layer can be carried out by each test pin simultaneously, carry out to verify more intuitively the effect of optimization of optics correction to ion implanted layer, namely optics correction is monitored on the impact of the isolating power of ion implanted layer, avoid the pattern density of domain to the adverse effect of ion implanted layer optics correction.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the test structure for the correction of SRAM device ion implantation optics of the specific embodiment of the invention;
Fig. 2 is the flow chart of the method for testing for the correction of SRAM device ion implantation optics of the specific embodiment of the invention.
Embodiment
For making object of the present invention, feature becomes apparent, and be further described, but the present invention can realize by different forms, should just not be confined to described embodiment below in conjunction with accompanying drawing to the specific embodiment of the present invention.
Core concept of the present invention is, on the basis of original element layout, add test pin, the method for applied electricity characteristic test carrys out the effect of the optics correction of element layout, carries out the unfavorable factor of critical size collection when avoiding device feature size very little.Below for SRAM device, describe technical scheme of the present invention and effect in detail.
Please refer to Fig. 1, the present invention proposes a kind of test structure for the correction of SRAM device ion implantation optics, remain the level of the front road process structure of former SRAM device array domain: NMOS tube active area, PMOS active area, polysilicon gate, N-type ion implanted layer, P type ion implanted layer grade, this architecture basics increases test pin to carry out electrical testing.The SRAM (i.e. static random access memory) of the present embodiment is CMOS static random asccess memory, its array comprises multiple nmos pass transistor and PMOS transistor, such as pull-up PMOS transistor, pulldown NMOS transistor and two transmission gate nmos pass transistors etc., can preserve the memory of data in energising situation.SRAM have low-power consumption, data access speed fast and with the advantage such as CMOS logic process is compatible, be widely used in various electronic device.
Please continue to refer to Fig. 1, in described test structure, in the SRAM of Fig. 1, each NMOS tube active area 101 (comprising the active area of transmission gate nmos pass transistor 102 and pulldown NMOS transistor 103) leads to the first test pin by through hole and metal wire, is designated as pin1; The exit 106 of the P type ion implanted layer 105 in SRAM leads to the second test pin by through hole and metal wire, be designated as pin2, PMOS active area in SRAM 109 active area of 104 (comprise pull up transistor) leads to the 3rd test pin by through hole and metal wire, be designated as pin3, the exit 108 of the N-type ion implanted layer 107 in SRAM leads to the 4th test pin by through hole and metal wire, is designated as pin4.When surveying the isolating power of P type ion implanted layer, to pin1 positive potential, pin4 connecting to neutral current potential; When surveying N-type ion implanted layer isolating power, pin3 connects negative potential, pin2 connecting to neutral current potential.Follow-uply according to electrical data such as the leakage currents between pin1 and pin4, pin2 and pin3, the optics correction of ion implanted layer can be optimized, to optimize the effect of ion implantation further.When P type ion implanted layer 106 be P trap, N-type ion implanted layer 108 for N trap time, the isolating power of P trap can be judged according to the leakage current between pin1 and pin4, judge the isolating power of N trap according to the leakage current between pin2 and pin3.
This test structure remains the prototype of the active area of SRAM structure, grid polycrystalline silicon, ion implanted layer, SRAM environment can be simulated more really, such as: size, shape, pattern density, surrounding enviroment etc., eliminate the impact of the image density of mask plate, simulate the isolating power of SRAM intermediate ion implanted layer exactly; Optics correction optimization for ion implanted layer provides electrical data as the foundation of checking, more intuitively, to find optimum optical optimization scheme, finally realizes more small size SRAM device; And apply the isolating power monitoring that this test structure can realize N-type ion implanted layer and P type ion implanted layer simultaneously, save area, can be used for the optics correction effect verifying trap implanted layer, adjusting thresholds implanted layer, field implanted layer, source and drain implanted layer, isolation implanted layer, material modification implanted layer or SOI buried regions implanted layer Plasma inpouring layer.
The test structure for the correction of SRAM device ion implantation optics of the present embodiment, can be extended for the test structure of other cmos device ion implantation optics corrections.Test structure for the correction of cmos device ion implantation optics comprises: formed on process structure basis, cmos device front road, described cmos device front road process structure comprises formation NMOS tube active area in the substrate, PMOS active area, N-type ion implanted layer, P type ion implanted layer, described test structure comprises: the first test pin from the extraction of NMOS tube active area, the second test pin from the extraction of P type ion implanted layer, the 3rd test pin of drawing from PMOS active area, and from the 4th test pin that N-type ion implanted layer is drawn; When testing the isolating power of described P type ion implanted layer, the first test pin connects positive potential, the 4th test pin connecting to neutral current potential, and when testing the isolating power of described N-type ion implanted layer, the 3rd test pin connects negative potential, the second test pin connecting to neutral current potential.Wherein, the ion implantation of described N-type ion implanted layer is that the trap of N-type ion injects, adjusting thresholds injects, field is injected, source and drain is injected, isolation is injected, material modification injects or SOI buried regions injects, the ion implantation of described P type ion implanted layer be P type ion trap injects, adjusting thresholds injects, field is injected, source and drain is injected, isolation is injected, material modification injects or SOI buried regions injects.
Refer to Fig. 2, the present embodiment also provides a kind of method of testing for the correction of SRAM device well region injection optics, comprises the following steps:
S1, one SRAM device array domain is provided, described SRAM device array domain has NMOS tube active area, PMOS active area, N trap, P trap and the N-type ion implanted layer except N trap (N-type ion trap inject formed), P type ion implanted layer Deng Qian road process structure level except P trap (P type ion trap is injected and formed), and each active area and well region are irregular polygon;
S2, revise described SRAM device array domain, to add test structure: draw the first test pin from described NMOS tube active area, from the second test pin that described P trap is drawn, the 3rd test pin is drawn from described PMOS active area, draw the 4th test pin from described N trap, described test structure comprises first to fourth test pin, and wherein the extraction of each test pin realizes mainly through through hole and metal lead wire;
S3, make SRAM device according to the amended SRAM device array domain with described test structure, described SRAM device comprises and has NMOS tube active area, PMOS active area, N-type ion implanted layer, P type ion implanted layer, N trap and P Jing Dengqian road process structure;
S4, carries out optics correction to the ion implanted layer of described SRAM device, and the effect of test and optimizing optical correction, comprise: the first test pin is connect positive potential, 4th test pin connecting to neutral current potential, monitors the isolating power of described P trap, to be optimized the optics correction of described P trap; And/or the 3rd test pin is connect negative potential, and the second test pin connecting to neutral current potential, monitors the isolating power of described N trap, to be optimized the optics correction of described N trap.
Wherein, S1 to S4 all can pass through software simulating in steps.Step S1 to S2 is by IC Layout software simulating, the simulation softward that step S3 to S4 is manufactured by semiconductor device, the simulation process of step S3 comprises: make mask according to the amended SRAM device array domain with described test structure, its pattern can define Semiconductor substrate is formed NMOS tube, PMOS active area and each ion implanted layer of comprising in the active area of well region, source/drain region etc., with described mask plate for mask, semi-conductive substrate is coated with photoresist, exposure, development, the existing front road techniques such as etching, by the design transfer of this mask in this Semiconductor substrate, form NMOS tube active area, PMOS active area and active area isolation etc., various ion implantation is carried out to described Semiconductor substrate, the trap comprising N-type ion and/or P type ion injects, adjusting thresholds injects, field is injected, source and drain is injected, isolation is injected, material modification injects or SOI buried regions injects Plasma inpouring, form each required ion implanted layer thus, comprise the trap implanted layer of N-type ion and/or P type ion, adjusting thresholds implanted layer, field implanted layer, source and drain implanted layer, isolation implanted layer, material modification implanted layer or SOI buried regions implanted layer etc., final formation SRAM device, described SRAM device comprises and has NMOS tube active area, PMOS active area, N-type ion implanted layer, P type ion implanted layer Deng Qian road process structure, in step S4, if the leakage current between the first test pin and the 4th test pin is less than the first set point, then the forecasting accuracy of the optics correction of described P trap reaches technological requirement, without the need to suboptimization again, otherwise, then need amendment optics corrected parameter, again monitor, if the leakage current between the second test pin and the 3rd test pin is less than the second set point, then the prediction of the optics correction of described N trap accurately reaches technological requirement, without the need to optimizing, otherwise, then need amendment optics corrected parameter, again monitor.Namely the isolating power of described P trap and N trap can again be monitored after every suboptimization, with suboptimization again to the optics correction of ion implanted layer, until the injection effect of ion implanted layer meets requirement on devices.In other embodiments, according to device performance requirements, also only single monitoring can be carried out to the isolating power of P trap or N trap.To the on-line monitoring of the optics correction of P trap and N trap in step S4, realized by the electrical data of monitoring between corresponding test pin, the isolating power of P trap and N trap is given more intuitively by these electrical data, avoid the impact of image density on well region isolating power, thus give expression to the effect of the optics amendment scheme of P trap and N trap more intuitively, to be adjusted to best optics amendment scheme intuitively, remove the obstacles for realizing small size SRAM.
The method of testing for the P trap of SRAM device and the optics correction of N trap of the present embodiment can be extend to other N-type ion implantations of SRAM device and the optics correction test of P type ion implanted layer, as halo ion implanted layer, the LDD ion implanted layer Plasma inpouring layer of source-drain area.
The method of testing of the present embodiment is not limited to SRAM device, may extend to the test of the optics correction of the ion implanted layer of any cmos device, particularly:
There is provided the cmos device that has a front road process structure, described front road process structure comprises formation NMOS tube active area in the substrate, PMOS active area, N-type ion implanted layer, P type ion implanted layer;
Draw the first test pin from described NMOS tube active area, from the second test pin that described P type ion implanted layer is drawn, draw the 3rd test pin from described PMOS active area, draw the 4th test pin from described N-type ion implanted layer;
Optics correction is carried out to ion implanted layer corresponding in described cmos device, optics correction is optimized simultaneously, comprise: the first test pin is connect positive potential, 4th test pin connecting to neutral current potential, monitor the isolating power of described P type ion implanted layer, to be optimized the optics correction of described P type ion implanted layer; And/or the 3rd test pin is connect negative potential, and the second test pin connecting to neutral current potential, monitors the isolating power of described N-type ion implanted layer, to be optimized the optics correction of described N-type ion implanted layer.
Further, if the leakage current between the first test pin and the 4th test pin is less than the first set point, then the forecasting accuracy of the optics correction of described P type ion implanted layer reaches technological requirement; If the leakage current between the second test pin and the 3rd test pin is less than the second set point, then the prediction of the optics correction of described N-type ion implanted layer accurately reaches technological requirement.
In sum, method of testing of the present invention, remain the prototype of the active area of cmos device front road process structure, grid polycrystalline silicon, ion implanted layer, can more real analog cmos device environment, such as: size, shape, pattern density, surrounding enviroment etc., eliminate the impact of the image density of mask plate, exactly the isolating power of analog cmos device intermediate ion implanted layer; Optics correction optimization for ion implanted layer provides electrical data as the foundation of checking, more intuitively, to find optimum optical optimization scheme, finally realizes more small size cmos device; And apply the isolating power monitoring that this test structure can realize N-type ion implanted layer and P type ion implanted layer simultaneously, save area, can be used for the optics correction effect verifying trap implanted layer, adjusting thresholds implanted layer, field implanted layer, source and drain implanted layer, isolation implanted layer, material modification implanted layer or SOI buried regions implanted layer Plasma inpouring layer.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. the test structure for the correction of cmos device ion implantation optics, process structure basis, cmos device front road is formed, described cmos device front road process structure comprises formation NMOS tube active area in the substrate, PMOS active area, N-type ion implanted layer, P type ion implanted layer, it is characterized in that, described test structure comprises: first test pin of drawing from NMOS tube active area, from the second test pin that P type ion implanted layer is drawn, 3rd test pin of drawing from PMOS active area, and from the 4th test pin that N-type ion implanted layer is drawn, when testing the isolating power of described P type ion implanted layer, the first test pin connects positive potential, the 4th test pin connecting to neutral current potential, and when testing the isolating power of described N-type ion implanted layer, the 3rd test pin connects negative potential, the second test pin connecting to neutral current potential.
2. test structure as claimed in claim 1, is characterized in that, the ion implantation of described N-type ion implanted layer is the trap injection of N-type ion, adjusting thresholds injection, field injection, source and drain injection, isolation injection, material modification injection or the injection of SOI buried regions; The ion implantation of described P type ion implanted layer is that the trap of P type ion injects, adjusting thresholds injects, field is injected, source and drain is injected, isolation is injected, material modification injects or SOI buried regions injects.
3. test structure as claimed in claim 1, it is characterized in that, described cmos device is SRAM, and described NMOS tube active area comprises the active area of pull-down NMOS pipe and the active area of transmission gate NMOS tube, and described PMOS active area comprises the active area of pull-up PMOS.
4. test structure as claimed in claim 3, it is characterized in that, described N-type ion implanted layer is N trap, and described P type sheath is P trap.
5. test structure as claimed in claim 1, is characterized in that, the first test pin, the second test pin, the 3rd test pin and each test pin of the 4th test pin are all drawn by through hole and metal lead wire.
6., for a method of testing for cmos device ion implantation optics correction, it is characterized in that, comprise the following steps:
There is provided the cmos device that has a front road process structure, described front road process structure comprises formation NMOS tube active area in the substrate, PMOS active area, N-type ion implanted layer, P type ion implanted layer;
Draw the first test pin from described NMOS tube active area, from the second test pin that described P type ion implanted layer is drawn, draw the 3rd test pin from described PMOS active area, draw the 4th test pin from described N-type ion implanted layer;
Optics correction is carried out to ion implanted layer corresponding in described cmos device, optics correction is optimized simultaneously, comprise: the first test pin is connect positive potential, 4th test pin connecting to neutral current potential, monitor the isolating power of described P type ion implanted layer, to be optimized the optics correction of described P type ion implanted layer; And/or the 3rd test pin is connect negative potential, and the second test pin connecting to neutral current potential, monitors the isolating power of described N-type ion implanted layer, to be optimized the optics correction of described N-type ion implanted layer.
7. method of testing as claimed in claim 6, it is characterized in that, if the leakage current between the first test pin and the 4th test pin is less than the first set point, then the forecasting accuracy of the optics correction of described P type ion implanted layer reaches technological requirement; If the leakage current between the second test pin and the 3rd test pin is less than the second set point, then the prediction of the optics correction of described N-type ion implanted layer accurately reaches technological requirement.
8. method of testing as claimed in claim 6, it is characterized in that, the ion implantation of described N-type ion implanted layer is that the trap of N-type ion injects, adjusting thresholds injects, field is injected, source and drain is injected, isolation is injected, material modification injects or SOI buried regions injects, the ion implantation of described P type ion implanted layer be P type ion trap injects, adjusting thresholds injects, field is injected, source and drain is injected, isolation is injected, material modification injects or SOI buried regions injects.
9. method of testing as claimed in claim 6, it is characterized in that, described cmos device is SRAM, described NMOS tube active area comprises the active area of pull-down NMOS pipe and the active area of transmission gate NMOS tube, described PMOS active area comprises the active area of pull-up PMOS, described N-type ion implanted layer is N trap, and described P type sheath is P trap.
10. method of testing as claimed in claim 6, is characterized in that, the first test pin, the second test pin, the 3rd test pin and each test pin of the 4th test pin are all drawn by through hole and metal lead wire.
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