CN105159613A - Emmc control system and access method of emmc control system - Google Patents
Emmc control system and access method of emmc control system Download PDFInfo
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- CN105159613A CN105159613A CN201510565879.9A CN201510565879A CN105159613A CN 105159613 A CN105159613 A CN 105159613A CN 201510565879 A CN201510565879 A CN 201510565879A CN 105159613 A CN105159613 A CN 105159613A
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Abstract
The invention provides an emmc (Embeded Multi Media Card) control system. A mode register, an equipment ID (identification) register and an interface sending unit are arranged in an emmc controller; the interface sending unit is connected with two emmc particles through the same clock wire; the two emmc particles are also connected with the interace sending unit through a command wire and two groups of data wires; the mode register is used for configuring the control quantity of the external emmc particles; in the double-emmc-particle mode, the two emmc particles share a signal of a clock wire; and the equipment ID register is used for configuring a sending address of a certain time of communication to be either of the two emmc particles, so that the signal can be sent to the concrete emmc particle through the corresponding command wire, or the data is read/written through the corresponding data wire. Therefore the goal of simultaneously using the two emmc particles for parallel access is achieved on the premise of not increasing the number of the controller; and the user experience is improved.
Description
Technical field
The present invention relates to a kind of emmc control system and access method thereof.
Background technology
At present along with user's improving constantly mobile device memory space requirements, just need to use more jumbo emmc particle.But on the market substantially not more than the emmc particle of 128GB, if so client needs to use the storage space more than 128GB, so just need to meet two panels emmc.According to agreement, an emmc controller can connect two panels emmc particle, and every sheet emmc particle distributes different addresses, is switched the card needing communication by address selection order.Clearly, if there is two methods program to need to access two data simultaneously, these two data are distributed on two different emmc particles the drawback of this mode just, so can only communicate with one of them emmc particle at single moment controller.So cause the reading data that must have an application program to can not get timely response, this application process card is caused to pause.In order to address this is that and satisfied display demand, the emmc controller that the present invention designs a kind of Discrete control solves these problems.
Summary of the invention
One of the technical problem to be solved in the present invention, is the emmc control system providing a kind of segmentation to access, and under not increasing the prerequisite of controller number, can compatibility make system use the concurrent access of two emmc particles simultaneously, improves Consumer's Experience.
One of the technical problem to be solved in the present invention is achieved in that a kind of emmc control system, comprise an emmc controller and two emmc particles, mode register, device id register and interface transmitting element is provided with in this emmc controller, described mode register and device id register are all connected described interface transmitting element, this interface transmitting element connects two emmc particles respectively by same clock line, and these two emmc particles are also connected this interface transmitting element respectively by an order wire with two groups of data lines; Described mode register is for configuring controlling the size of external emmc particle, if be configured to " two emmc particle pattern ", then these two emmc particles share the signal of described clock line; Which in described two emmc particles described device id register be for configuring the transmission address of certain communication, to be sent to concrete emmc particle by corresponding order wire, or reads and writes data through corresponding data line group.
The technical problem to be solved in the present invention two, is the segmentation access method providing a kind of emmc control system, under not increasing the prerequisite of controller number, can compatibility make system use the concurrent access of two emmc particles simultaneously, improves Consumer's Experience.
Two of the technical problem to be solved in the present invention is achieved in that a kind of access method of emmc control system, described emmc control system comprises an emmc controller and two emmc particles, mode register, device id register and interface transmitting element is provided with in this emmc controller, described mode register and device id register are all connected described interface transmitting element, this interface transmitting element connects two emmc particles respectively by same clock line, and these two emmc particles are also connected this interface transmitting element respectively by an order wire with two groups of data lines; Described method controls the quantity of external emmc particle by configuring described mode register, if be configured to " two emmc particle pattern ", then these two emmc particles share the signal of described clock line; And be which in described two emmc particles by the described device id register of configuration with the transmission address determined certain and communicate, to be sent to concrete emmc particle by corresponding order wire, or read and write data through corresponding data line group.
Further, in two groups of data lines of the present invention, the quantity often organizing data line is 4.
Further, if the external emmc particle that configures of described mode register control the size as " single emmc particle pattern ", then described two groups of data lines use all to the emmc particle communication of single correspondence.
Further, the layoutprocedure of described " two emmc particle pattern " is:
(1) transmission control command is first driven, read capacity C 1 and the C2 of two emmc particles respectively, and C3=C1+C2 is reported operating system, indicate the capacity sum that disk size is low level emmc particle capacity and high-order emmc particle, operating system will drop in capacity C 3 to the data A of disk access;
(2) drive the described mode register of reading, judge current as " two emmc particle pattern ", need to carry out following address arithmetic:
If A is less than C1, then the address of data A belongs to low level emmc particle, ID register configuration is the ID that low level emmc particle is corresponding by the therefore actual address=A of this data A, and now emmc controller sends the request of reading or writing address A to low level emmc particle; If A is greater than C1, then the address of data A belongs to high-order emmc particle, ID register configuration is the ID that high-order emmc particle is corresponding by the actual address=A-C1 of this data A, and now emmc controller sends the request of reading or writing address A-C1 to high-order emmc particle.。
Tool of the present invention has the following advantages: make two emmc particles share clock line signal and individually use an order wire and one group of data line, the quantity of controlled emmc particle is realized by the mode register in configuration emmc controller, be which in described two emmc particles by configuration device ID register with the transmission address determined certain and communicate again, to be sent to concrete emmc particle by corresponding order wire, or read and write data through corresponding data line group, thus realize emmc controller the segmentation of two emmc particles is accessed, the present invention can under the prerequisite not increasing controller number, compatibility makes system use the concurrent access of two emmc particles simultaneously, greatly increase Consumer's Experience.
Accompanying drawing explanation
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the structural representation of emmc control system of the present invention.
Fig. 2 is the FB(flow block) of the segmentation access of emmc control system of the present invention.
Embodiment
Refer to shown in Fig. 1 and Fig. 2; the emmc control system of segmentation access of the present invention; comprise an emmc controller and two emmc particles; mode register, device id register and interface transmitting element is provided with in this emmc controller; described mode register and device id register are all connected described interface transmitting element; this interface transmitting element connects two emmc particles respectively by same clock line, and these two emmc particles are also connected this interface transmitting element respectively by an order wire with two groups of data lines.
Wherein, described mode register is for configuring controlling the size of external emmc particle; Which in described two emmc particles described device id register be for configuring the transmission address of certain communication.
As shown in Figure 1, two emmc particles are respectively low level emmc particle 1 and high-order emmc particle 2, in described two groups of data lines, the quantity often organizing data line is 4, low level emmc particle 1 and high-order emmc particle 2 is made all to operate in 4 ray modes, the data line of corresponding low level emmc particle 1 is data line 0-3, and the data line of corresponding high-order emmc particle 2 is data line 4-7; In addition, the order wire of low level emmc particle 1 correspondence is order wire a, and the order wire of high-order emmc particle 2 correspondence is order wire b.
Based on above-mentioned emmc control system, method of the present invention is namely by configuring described mode register to control the quantity of external emmc particle, if be configured to " two emmc particle pattern ", then these two emmc particles share the signal of described clock line; And be which in described two emmc particles by the described device id register of configuration with the transmission address determined certain and communicate, to send control signals to concrete emmc particle by corresponding order wire, or to read and write data through corresponding data line group.If be configured to " single emmc particle pattern ", then described two groups of data lines use all to the emmc particle communication of single correspondence.
As shown in Figure 2, the layoutprocedure of the present invention to " two emmc particle pattern " is:
(1) transmission control command is first driven, read capacity C 1 and the C2 of two emmc particles respectively, and C3=C1+C2 is reported operating system, indicate the capacity sum that disk size is low level emmc particle capacity and high-order emmc particle, now operating system do not know that actual is two emmc particles, it thinks the emmc particle of a vast capacity, and so operating system will drop in capacity C 3 to the data A of disk access; If A is less than C1, then the actual address of data A is on emmc particle 1; If A is greater than C1, then the actual address of data A is on emmc particle 2.
(2) drive and read described mode register, judge current as " two emmc particle pattern ", judge it is physically an emmc particle or two according to Mode Selection register, if two, then need to carry out following address arithmetic:
If A is less than C1, then the address of data A belongs to low level emmc particle, ID register configuration is the ID that low level emmc particle is corresponding by the therefore actual address=A of this data A, and now emmc controller sends the request of reading or writing address A to low level emmc particle; If A is greater than C1, then the address of data A belongs to high-order emmc particle, ID register configuration is the ID that high-order emmc particle is corresponding by the actual address=A-C1 of this data A, and now emmc controller sends the request of reading or writing address A-C1 to high-order emmc particle.
The present invention makes two emmc particles share clock line signal and individually uses an order wire and one group of data line as previously mentioned, the quantity of controlled emmc particle is realized by the mode register in configuration emmc controller, be which in described two emmc particles by configuration device ID register with the transmission address determined certain and communicate again, to be sent to concrete emmc particle by corresponding order wire, or read and write data through corresponding data line group, thus realize emmc controller the segmentation of two emmc particles is accessed, the present invention can under the prerequisite not increasing controller number, compatibility makes system use the concurrent access of two emmc particles simultaneously, greatly increase Consumer's Experience.
Although the foregoing describe the specific embodiment of the present invention; but be familiar with those skilled in the art to be to be understood that; specific embodiment described by us is illustrative; instead of for the restriction to scope of the present invention; those of ordinary skill in the art, in the modification of the equivalence done according to spirit of the present invention and change, should be encompassed in scope that claim of the present invention protects.
Claims (8)
1. an emmc control system, it is characterized in that: comprise an emmc controller and two emmc particles, mode register, device id register and interface transmitting element is provided with in this emmc controller, described mode register and device id register are all connected described interface transmitting element, this interface transmitting element connects two emmc particles respectively by same clock line, and these two emmc particles are also connected this interface transmitting element respectively by an order wire with two groups of data lines;
Described mode register is for configuring controlling the size of external emmc particle, if be configured to " two emmc particle pattern ", then these two emmc particles share the signal of described clock line;
Which in described two emmc particles described device id register be for configuring the transmission address of certain communication, to be sent to concrete emmc particle by corresponding order wire, or reads and writes data through corresponding data line group.
2. a kind of emmc control system according to claim 1, is characterized in that: in described two groups of data lines, and the quantity often organizing data line is 4.
3. a kind of emmc control system according to claim 1 and 2, it is characterized in that: if the external emmc particle that configures of described mode register control the size as " single emmc particle pattern ", then described two groups of data lines use all to the emmc particle communication of single correspondence.
4. a kind of emmc control system according to claim 1, is characterized in that: the layoutprocedure of described " two emmc particle pattern " is:
(1) transmission control command is first driven, read capacity C 1 and the C2 of two emmc particles respectively, and C3=C1+C2 is reported operating system, indicate the capacity sum that disk size is low level emmc particle capacity and high-order emmc particle, operating system will drop in capacity C 3 to the data A of disk access;
(2) drive the described mode register of reading, judge current as " two emmc particle pattern ", need to carry out following address arithmetic:
If A is less than C1, then the address of data A belongs to low level emmc particle, ID register configuration is the ID that low level emmc particle is corresponding by the therefore actual address=A of this data A, and now emmc controller sends the request of reading or writing address A to low level emmc particle; If A is greater than C1, then the address of data A belongs to high-order emmc particle, ID register configuration is the ID that high-order emmc particle is corresponding by the actual address=A-C1 of this data A, and now emmc controller sends the request of reading or writing address A-C1 to high-order emmc particle.
5. the access method of an emmc control system, it is characterized in that: described emmc control system comprises an emmc controller and two emmc particles, mode register, device id register and interface transmitting element is provided with in this emmc controller, described mode register and device id register are all connected described interface transmitting element, this interface transmitting element connects two emmc particles respectively by same clock line, and these two emmc particles are also connected this interface transmitting element respectively by an order wire with two groups of data lines;
Described method controls the quantity of external emmc particle by configuring described mode register, if be configured to " two emmc particle pattern ", then these two emmc particles share the signal of described clock line;
And be which in described two emmc particles by the described device id register of configuration with the transmission address determined certain and communicate, to be sent to concrete emmc particle by corresponding order wire, or read and write data through corresponding data line group.
6. the access method of a kind of emmc control system according to claim 5, is characterized in that: in described two groups of data lines, and the quantity often organizing data line is 4.
7. the access method of a kind of emmc control system according to claim 5 or 6, it is characterized in that: if the external emmc particle that configures of described mode register control the size as " single emmc particle pattern ", then described two groups of data lines use all to the emmc particle communication of single correspondence.
8. the access method of a kind of emmc control system according to claim 5, is characterized in that: the layoutprocedure of described " two emmc particle pattern " is:
(1) transmission control command is first driven, read capacity C 1 and the C2 of two emmc particles respectively, and C3=C1+C2 is reported operating system, indicate the capacity sum that disk size is low level emmc particle capacity and high-order emmc particle, operating system will drop in capacity C 3 to the data A of disk access;
(2) drive the described mode register of reading, judge current as " two emmc particle pattern ", need to carry out following address arithmetic:
If A is less than C1, then the address of data A belongs to low level emmc particle, ID register configuration is the ID that low level emmc particle is corresponding by the therefore actual address=A of this data A, and now emmc controller sends the request of reading or writing address A to low level emmc particle; If A is greater than C1, then the address of data A belongs to high-order emmc particle, ID register configuration is the ID that high-order emmc particle is corresponding by the actual address=A-C1 of this data A, and now emmc controller sends the request of reading or writing address A-C1 to high-order emmc particle.
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Cited By (2)
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| CN106409337A (en) * | 2016-09-20 | 2017-02-15 | 北京润科通用技术有限公司 | eMMC control method and FPGA-based eMMC controller |
| CN107729140A (en) * | 2017-09-22 | 2018-02-23 | 华南理工大学 | A kind of device and method of the multiple eMMC Host Interface Commands queuing capabilitys of Parallel Implementation |
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| CN106409337A (en) * | 2016-09-20 | 2017-02-15 | 北京润科通用技术有限公司 | eMMC control method and FPGA-based eMMC controller |
| CN107729140A (en) * | 2017-09-22 | 2018-02-23 | 华南理工大学 | A kind of device and method of the multiple eMMC Host Interface Commands queuing capabilitys of Parallel Implementation |
| CN107729140B (en) * | 2017-09-22 | 2020-07-28 | 华南理工大学 | Device and method for realizing command queuing functions of multiple eMMC host interfaces in parallel |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |