CN105144369B - 印刷复杂的电子电路 - Google Patents

印刷复杂的电子电路 Download PDF

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Publication number
CN105144369B
CN105144369B CN201480013809.6A CN201480013809A CN105144369B CN 105144369 B CN105144369 B CN 105144369B CN 201480013809 A CN201480013809 A CN 201480013809A CN 105144369 B CN105144369 B CN 105144369B
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group
substrate
conductor
printed circuit
electrode
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CN105144369A (zh
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威廉·约翰斯通·雷
理查德·奥斯汀·布兰查德
马克·戴维·洛温塔尔
布拉德利·史蒂文·奥拉韦
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Global Co Of Nice Di Gerui Science And Technology
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Global Co Of Nice Di Gerui Science And Technology
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Abstract

本发明涉及一种可编程电路，其包含微观晶体管或二极管(40)的经印刷群组(72、74)的阵列。装置经预成形且作为墨水印刷且经固化。每一群组中的所述装置经并联连接，使得每一群组充当单个装置。在一个实施例中，每一群组中含有大约10个装置，因此冗余使得每一群组非常可靠。每一群组具有至少一个电引线(85)，其终接在衬底(50)上的贴片区域(86)中。一互连导体图案使所述贴片区域中的所述群组的至少一些所述引线互连，以针对通用电路的自定义应用形成逻辑电路。所述群组还可被互连为逻辑门，且门引线终接在所述贴片区域中。所述互连导体图案随后使所述门互连以形成复杂逻辑电路。

Description

印刷复杂的电子电路
相关申请案的交叉参考
本申请案是基于由威廉·约翰史东·雷(William Johnstone Ray)等人于2013年3月14日申请的第61/785,292号美国临时申请案，所述申请案被让渡给本受让人且以引用的方式并入本文中。
技术领域
本发明涉及在衬底上以单独群组印刷预成形微观半导体装置，例如晶体管及二极管，其中每一群组中的随机分布装置经并联连接，且本发明涉及使群组互连以产生更复杂电路，例如逻辑电路。
背景技术
通过本受让人自身的工作已了解如何以适当定向在导电衬底上形成及印刷微观两端垂直发光二极管(LED)及将LED并联连接以形成光板。可于标题为“制造二极管的可印刷液体或胶体悬浮合成物的方法(Method of Manufacturing a Printable Compositionof Liquid or Gel Suspension of Diodes)”的美国申请公开案US 2012/0164796中找到此类LED印刷的细节，所述案被让渡给本受让人且以引用的方式并入本文中。
图1是可使用下列工艺印刷的LED 16的层的横截面图。每一LED 16包含标准半导体GaN层，包含n层及活性层以及p层。
LED晶片(含有数千个垂直LED)经制作使得每一LED 16的底部金属阴极电极18包含反射层。每一LED 16的顶部金属阳极电极20为小的以允许几乎所有LED光逸出阳极侧。通过粘着层接合到LED晶片的“顶部”表面的载体晶片可用于接达到LED的两侧以进行金属化。随后，例如通过围绕每一LED向下蚀刻沟槽到粘着层及溶解暴露的粘着层或通过薄化载体晶片而切分LED 16。
随后，将微观LED均匀浸泡于包含粘度改质聚合物树脂的溶剂中，以形成用于印刷(例如丝网印刷或胶版印刷)的LED墨水。
如果需在印刷后使阳极电极20定向在与衬底22相反的方向上，那么使电极20较高以使得LED 16在安定在衬底表面上时通过流体压力而在溶剂中旋转。LED 16旋转到最小电阻的定向。已实现超过90％的类似定向。
在图1中，提供起始衬底22。如果衬底22本身不导电，那么例如通过印刷在衬底22上沉积反射导体层24(例如，铝)。衬底22可为薄的且柔性。
随后，例如通过胶版印刷在导体层24上印刷LED 16，其中辊板上的图案确定了卷带式工艺的沉积，或通过使用适当网进行丝网印刷以允许LED穿过并控制层的厚度而在导体层24上印刷LED 16。由于相对较低浓度，LED 16将被印刷为单层，且相当均匀地分布在导体层24上方。
随后，使用例如红外线炉使溶剂热蒸发。在固化后，LED 16保持附接到下伏导体层24，其中溶解在LED墨水中的少量残余树脂作为粘度改质剂。树脂的粘着性质及在固化期间LED 16下方的树脂的量的减小会将底部LED电极18压抵在下伏导体24上，从而与其进行欧姆接触。
随后，在表面上方印刷电介质层26以囊封LED 16且进一步将其固定在适当位置中。
随后，在电介质层26上方印刷顶部透明导体层28以电接触电极20且在适于所使用的透明导体类型的炉中固化顶部透明导体层28。
如果需要散布电流，那么随后沿着导体层24及28的相反边沿印刷金属汇流条30到33，且金属汇流条30到33分别电终接在阳极及阴极引线(未展示)用于供电给LED 16。汇流条30到33最终将连接到正或负驱动电压。
图2是图1的俯视图。图2的横截面是图3的水平对分。LED 16在经印刷层中的位置是随机的。
如果将适当电压差施加到阳极及阴极引线，那么具有适当定向的所有LED 16将被照明。图1展示光线38。
上述工艺严格结合具有顶部电极及底部电极的两端装置使用，这是因为LED在衬底上的位置是随机的，且仅可通过将LED夹置于任何厚度的两个导电层之间而互连LED。此外，上述工艺严格用于形成用于产生光的LED阵列。所述LED不旨在执行任何类型的逻辑功能，这是因为并联连接的LED的阵列只形成单个二极管。
将期望调适上述印刷/固化工艺以产生涉及三端晶体管、二极管及可能的额外类型的组件的复杂印刷电路以执行逻辑功能。
发明内容
本发明大体上涉及在衬底(例如柔性电路)上以小的单独群组印刷预成形微观(例如，介于10微米到200微米之间的尺寸)电子装置，包含晶体管及二极管。每一群组可含有例如大约10个装置。每一群组中的装置是使用经印刷导体层并联连接。
每一群组充当单个装置(例如，单个晶体管或单个二极管)，这是因为相同装置在每一群组中并联连接。在形成群组后的任何时间，群组随后经互连(编程)以形成自定义电路，例如用于执行指定功能的逻辑电路。
在一个实施例中，所印刷装置是晶体管或二极管，且编程步骤形成多个逻辑门。在另一实施例中，衬底最初经处理以从群组形成逻辑门的阵列，且后续“编程”步骤通过使门互连以形成复杂的逻辑电路而自定义衬底。因此，经印刷衬底可形成可编程门阵列。
在一个实施例中，“编程”以形成电路是通过以下步骤执行：在衬底上形成疏水掩模；界定互连图案；及随后沉积导电材料以在衬底上形成互连金属迹线。在另一实施例中，互连迹线通过胶版印刷或丝网印刷直接印刷在衬底上。
装置的群组可均为相同装置(例如，晶体管)或为多种装置(例如，晶体管及二极管)。电路可为除逻辑电路以外的电路，例如控制电路、切换电路、模拟电路等。
许多类型的电组件使用三个端子，例如MOSFET、双极晶体管、JFET、晶闸管、硅控整流器等。此类组件中的常规组件通常针对横向装置在顶部上具有三个端子，或针对垂直装置在顶部上具有两个端子且在底部上具有一个端子。已知通过在衬底上方印刷各种晶体管层而形成薄膜晶体管，但是此类经印刷晶体管的性能归因于印刷单晶体的困难而不良。如果晶体管(或其它三端装置)可更常规地形成在半导体晶片中且随后经切分以产生作为墨水印刷的微观装置，那么装置的质量可为第一流的。然而，迄今为止，尚不知道如何设计此类装置或在印刷后使此类三端微观装置互连以执行复杂的功能。
在一个实施例中，形成三端装置(例如晶体管)的半导体(例如，硅)晶片。晶体管经形成在晶片中以具有底部电极、顶部电极及定位于装置的顶部与底部之间某处的架子上的中间电极。起始晶片最终通过粘着剂贴附到载体晶片以在制作晶体管时可接达到所述晶体管的两个表面。
通过围绕每一晶体管形成沟槽而将晶体管切分为个别晶体管，例如以形成六边形装置。沟槽向下延伸到粘着层且粘着层溶解在溶液中，从而从载体晶片释放所有晶体管。
随后，将晶体管均匀混合到溶液中以形成墨水。晶体管的形状导致其大多数以所需定向印刷在衬底上。
随后，印刷晶体管以在衬底上方的相关联第一导体层部分上形成晶体管的群组的阵列，且使墨水固化(加热及蒸发)，使得每一晶体管的底部电极欧姆接触到此类第一导体层部分。归因于溶液中的晶体管的相对低密度，晶体管将被印刷为松散单层。产品中的任何层的印刷可通过胶版印刷(尤其适于卷带式工艺)、丝网印刷(在形成平板时尤其适用)或其它类型的印刷。
随后，在第一导体层部分上方印刷第一电介质层。第一电介质层未覆盖中间电极。随后，印刷与第一导体层部分对准的第二导体层部分，第二导体层部分接触中间电极但未覆盖顶部电极。各种薄的经印刷层通过强表面张力而自平坦化，使得层未覆盖“高于”层的厚度的任何特征。或者，层可在固化后经毯覆式蚀刻以暴露任何电极。
随后，在第二导体层部分上方印刷第二电介质层，但未覆盖顶部电极。随后，印刷顶部(第三)导体层部分以接触每一群组中的晶体管的顶部电极。
因此，晶体管的顶部电极并联连接，底部电极并联连接，且中间电极(或其子集)并联连接，以传导广泛范围的电流。
如上所述，随后可在编程步骤中使群组互连以形成逻辑门或更复杂电路。
可印刷微观垂直二极管来代替晶体管，且只需两个导体层以使每一群组中的二极管并联连接。
对于简单无源装置(例如电阻器)，电阻材料本身(而非印刷含有个别电阻器的墨水)可被印刷在小区域中，且通过导体沿着电阻器长度在何处接触电阻器来确定电阻。
衬底的不同区域可印刷有不同装置或相同装置，且每一区域中的装置被并联连接。因此，每一区域本质上是单个装置。导体层终接在衬底上紧邻每一区域的连接器区域中。
在一个实施例中，衬底可具有指定“贴片(patch)”区域，其中制成群组或门的互连。此简化经编程互连的设计，这是因为贴片区域可针对编程步骤而优化。
装置经形成使得在群组中的一些装置经倒置印刷或形成不良连接的情况下，对群组中的适当定向装置的功能无不利影响。
印刷工艺可使用大气压下的卷带式工艺。经印刷可编程衬底的成本远低于使用常规技术形成的相当可编程衬底的成本。
揭示其它实施例。
附图说明
图1是可使用受让人的现有技术工艺形成的经印刷微观垂直LED的松散单层的横截面。
图2是图1的结构的俯视图，其中图1是水平对分图2而取得。
图3是根据本发明的一个实施例的已从晶片切分的单个三端晶体管的透视图。晶体管经混合到溶液中以形成用于印刷在衬底上的墨水。
图4是使用导体层的三个平面并联连接的图3的晶体管的经印刷层的小部分的横截面。可在每一单独群组中印刷大约10个并联连接晶体管，且在衬底上方印刷群组的阵列。
图5图解说明图3的晶体管如何可为npn双极晶体管。
图6图解说明图3的晶体管如何可为p沟道MOSFET。
图7及8图解说明一些晶体管在印刷时可如何由于晶体管的不当定向而“不正确地”互连，其中互连未不利影响适当定向的晶体管的功能。
图9是识别MOSFET及双极晶体管的顶部电极、底部电极及中间电极的优选功能的图表。
图10图解说明使晶体管的群组互连以形成逻辑电路。
图11图解说明装置的各种群组的引线可如何被带到衬底的贴片区域以用于使群组互连。在另一实施例中，可将由群组制成的逻辑门(例如，NAND门)的引线带到贴片区域。
图12是使用疏水掩模图案化的导体的俯视图。
图13是使用图12的掩模形成的导体线中的一者的横截面图。
图14图解说明疏水掩模可如何用于形成导体线以使装置的群组互连以形成逻辑电路。
图15图解说明可如何通过导体接触经印刷电阻材料的位置确定电阻器值。
图16图解说明装置可如何被印刷在衬底的两侧上且通过通孔互连。
图17图解说明电路可如何被印刷在相对较小衬底上且经测试，随后小衬底在自定义步骤期间附接到较大“基底”衬底。
图18图解说明图17的小衬底上的电极可如何接合到基底衬底上的电极。
图19图解说明可用于形成电路的卷带式工艺。
在各种图中，类似或相同的元件用相同数字标记。
具体实施方式
本发明的经印刷可编程电路可使用无源装置(例如，电容器、电阻器)、两端无机半导体装置(例如，二极管)及三端无机半导体装置(例如，晶体管)的任何组合。最复杂的待印刷及电连接到的装置是三端装置。在一些情况中，可通过只使用两个端子或将两个端子连接到相同导体而将三端装置(例如双极晶体管)用作二极管。
本发明的实施例中所使用的三端装置可小于人类头发的直径，从而使所述装置在跨衬底稀疏散布时对于裸眼基本上不可见。装置的大小可在宽大约10微米到200微米的范围内。每单位面积的微装置的数目可在将微装置应用到衬底时自由调整。装置可使用胶版印刷、丝网印刷或其它形式的印刷而作为墨水印刷。三端装置的常规设计可易于经调适用于形成本发明的微装置。光微影的精度完全能达到形成微装置所需的精度要求。由于许多微装置将并行操作，所以每一微装置的效率并非至关重要的。
图3是可悬浮在溶剂中且作为墨水印刷在衬底上的三端装置40的透视图。装置40可为双极晶体管、MOSFET、JFET、三MOS(tri-MOS)装置或任何其它三端装置，其大致包含两个载流端子及一个控制端子。装置40可为横向或垂直晶体管，这是因为三个电极的位置未规定在装置40内部的半导体层/区域或栅极的位置。电极可使用通孔接触装置40中的任何位置。
装置40完全形成在半导体晶片上(包含通过在处理期间使用一或多个载体晶片以接达到用于金属化的两个表面而进行的电极金属化)。虽然生长晶片可为硅，但是载体晶片可为任何材料。硅晶片使用粘着剂或其它适当材料贴附到载体晶片。每一装置40的形状是通过掩蔽及蚀刻界定。各种层或区域可使用经掩蔽植入或通过在外延生长的同时掺杂层而受到掺杂。在装置形成在晶片上之后，围绕每一装置40在晶片的前表面中光微影界定沟槽且向下蚀刻沟槽到粘着层。每一装置40的优选形状是六边形。沟槽蚀刻暴露下伏晶片接合粘着剂。随后，粘着剂溶解在溶液中以从载体晶片释放装置40。可代替性地通过薄化载体晶片的后表面直到装置40被切分来执行切分。随后，微观装置40被均匀浸泡在包含粘度改质聚合物树脂的溶剂中，以形成用于印刷(例如丝网印刷或胶版印刷)的墨水。
可使用类似技术以形成两端装置，例如垂直二极管，其中一个电极处于顶部上且另一电极处于底部上。二极管可具有类似于图3中所示的形状的形状但无中间电极。
关于在晶片中塑形垂直LED(两端装置)且随后切分LED用于作为墨水印刷的细节描述于标题为“制造二极管的可印刷液体或胶体悬浮合成物的方法(Method ofManufacturing a Printable Composition of Liquid or Gel Suspension of Diodes)”的美国申请公开案US 2012/0164796中，所述案被让渡给本受让人且以引用的方式并入本文中。所属领域技术人员可调适此类工艺以用于形成三端装置40及非LED二极管。
装置40具有两个区段：下区段42(或基底部分)及上区段44。上区段44被制成相对较高及窄，使得装置40在其安定于衬底表面上时由于流体压力在溶剂中旋转。装置40旋转到最小电阻的定向。已实现超过90％类似定向，但是令人满意的性能可在超过75％的装置40处于相同定向的情况下实现。
下区段42应经塑形使得装置40在墨水固化后平放在衬底上。图4图解说明三个经印刷装置40，其中只有两个经印刷装置40是以正确定向印刷。
装置40包含金属顶部电极46、金属中间电极48及金属底部电极(图3中未展示)。中间电极48的形状提供大的侧表面积，以用于与中间导体层良好电接触。
中间电极48应偏离装置40的中间，使得装置40在印刷后的不当定向导致中间电极48未电接触中间导体层。在实例中，中间电极48处在装置40的中间下方(即，H2＜1/2H1)。
在图4中，提供起始衬底50。为了轻重量、低成本、向空气或散热器的良好热传导及便于处理，衬底50优选地为薄且柔性。衬底50可为适当聚合物，例如聚碳酸酯、PMMA或PET，且可为柔性的以从辊施配。衬底50可为适于最终产品的任何大小。衬底50可为常规柔性电路衬底，其中金属(例如，铜)迹线已在下文处理步骤之前通过常规方式形成在衬底50上。
如果衬底50尚未如柔性电路般在其上形成金属迹线，那么例如通过印刷在衬底50上沉积导体层52(例如，银、铝、铜)。可使用穿过衬底50的导电通孔54以将导体层52耦合到形成在衬底50的底部表面上的金属层56。在各种实例中，导体层52被印刷为衬底50上的圆点的阵列(见图11)。点彼此电隔离以允许装置40的群组以任何方式互连以形成逻辑电路。代替圆点，导体层52可被印刷为方点或其它形状的点。
随后，例如通过胶版印刷或通过使用适当网进行丝网印刷而将装置40印刷在导体层52上以允许装置40穿过并控制层的厚度。由于相对较低浓度，装置40将被印刷为松散单层，且相当均匀地分布在导体层52上方。装置40的经印刷位置与导体层52的经印刷点的位置对准。
随后，通过使用(例如)红外线炉使溶剂热蒸发。在固化后，装置40保持附接到下伏导体层52，其中溶解在墨水中的少量残余树脂作为粘度改质剂。树脂的粘着性质及在固化期间装置40下方的树脂的量减小会将底部电极58压抵在下伏导体层52上，从而与其进行欧姆接触。
随后，印刷薄电介质层60以覆盖导体层52，且进一步将装置40固定在适当位置中。电介质层60经设计以在固化期间通过表面张力自平坦化，以拉脱顶部电极46及中间电极48，或使其去湿。因此，无需蚀刻电介质层60。如果电介质层60覆盖电极46/48，那么可使用毯覆式蚀刻以暴露电极46/48。
随后，在电介质层60上方印刷与导电层52的点对准的中间导体层62以电接触中间电极48，且在适于所使用的导体的类型的炉中固化中间导体层62。各种导体层可为金属(或含有金属)或可为任何其它类型的可印刷导体层。
在中间导体层62上方印刷另一薄电介质层64以便不覆盖顶部电极46。
随后，在电介质层64上方印刷与中间导体层62的点对准的顶部导体层66以电接触顶部电极46，且在适于所使用的导体的类型的炉中固化顶部导体层66。
随后，可在导体层66上方印刷较厚金属层68以用于改进导电性及/或热传导。中间导体层62从点的边沿延伸出以形成装置40的群组的端子。
图4图解说明形成图4的结构所需的仅有步骤是印刷步骤67及固化步骤69。装置40的随机图案可类似图2中的LED 16的图案。
图4图解说明最右装置40A经定向在相反方向上。但是，中间电极48保持浮动，因此装置40A并未操作且对所得电路无影响。
经印刷装置40通过导体层并联连接。将适当的操作电压及控制电压施加到导体层以操作装置40。在图4的实例中，顶部电极46是装置40的控制电极(例如，用于栅极或基极)。剩余两个电极是载流电极(例如，源极/漏极、射极/集极)。由于不当定向的装置40A的中间电极48是浮动的，所以装置40保持断开且为开路。
图5图解说明装置40如何可为npn双极晶体管40B，其中中间电极48是基极电极。中间电极48可使用通孔连接到装置40B中的任何其它半导体层。
图6图解说明装置40如何可为p沟道MOSFET 40C，其中中间电极48是源极电极。中间电极48可使用通孔连接到装置40C中的任何其它层。
如果装置40将连接为二极管，那么只可使用导体层62及52或66及62。因此，可通过将哪两个导体层用以接触二极管来选择二极管的有效极性。替代地，两个导电层可经远程连接以形成二极管。
任何数目个装置40可并联连接在群组中以用于处置广泛范围的电流。在一个实施例中，大约10个装置40被定位在每一群组中。装置40的群组是例如通过在胶版印刷工艺中使用辊上的图案或通过使用丝网印刷网上的掩模而印刷为群组的二维阵列，且各种导体层可经类似图案化使得每一群组中的装置40并联连接，但是每一群组彼此电隔离。因此，每一群组形成单独组件。随后，可使用衬底50上的“编程”导体迹线来选择性地使群组互连以形成更复杂电路，例如逻辑电路。衬底50上的金属柔性电路图案可用于使装置40的群组互连以形成逻辑电路。在一个实施例中，由于每一群组可小到每侧一毫米或直径一毫米，所以此类群组的二维阵列可超过数千个群组。小区域内的群组可经互连以形成逻辑门，且所述门的端子可在编程期间互连以执行任何逻辑功能。
图7图解说明图4中的装置40A的不当定向如何未不利影响群组中并联连接的适当定向装置40的操作。装置40/40A被假设为npn双极晶体管，其具有用作基极的顶部电极46、用作射极的底部电极58及用作集极的中间电极48。由于装置40A在印刷期间非所需地倒置定向(图4中所示)，所以其基极短接到装置40的射极，且其射极短接到装置40的基极。当装置40的基极/射极结经正向偏压以开启装置40时，装置40A保持断开且对装置40的操作无影响。注意，通过使用偏离装置40的中间的中间电极48(如图3及图4中所示)，装置40A的中间电极48将是浮动的，从而使其效应更加微不足道。
图8类似于图9，但是装置40及40A是MOSFET。
图9是表，其展示形成为MOSFET或双极晶体管的装置40的顶部电极、底部电极及中间电极的可能连接，使得不当定向未不利影响并联连接的适当定向装置40的功能。
图10图解说明经印刷npn双极晶体管(例如，装置40)的两个群组72及74，其中每一群组中的晶体管经并联连接，使得每一群组充当单个晶体管。装置40及导体层的印刷图案作为圆点形成群组，但可使用任何形状的点。图4中的群组的互连使电路成为AND门。导电迹线75针对每一群组连接到图4中的各种导体层。两个晶体管(即，群组72及74)串联连接在供应电压端子76与78之间，晶体管的基极连接到输入端子80及82，且输出端子84连接到由群组74形成的晶体管的射极。各种端子可在衬底50的边沿附近或邻近群组。
电阻器r1及r2被展示为连接在输入端子80/82与基极之间用于电流控制。归因于电阻器的简单性，电阻材料可运用经图案化辊使用胶版印刷或用于印刷电阻材料的筛网上的掩模直接图案化在衬底上。电阻材料的形状可确定电阻或连接器沿着电阻材料长度的位置可确定电阻。电阻器还可包含在每一装置40上。也可通过印刷电容器的层而形成电容器。
衬底50可含有数百或数千个此类AND门或其它门，且所述门可经互连以形成更复杂的功能。在此情况中，所述门等效于可编程门阵列。对于更柔性电路，群组最初可未连接，且互连的编程掩模可确定最终电路。三维编程可用于允许迹线的交叉。可产生门及其它逻辑电路的任何组合。一些群组可包含晶体管且其它群组可含有其它装置，例如二极管。也可通过使各种群组互连而形成模拟电路。
归因于装置40在墨水中随机但实质上均匀的分布，相同面积的每一群组将具有近似相同数目的装置40。群组中装置40的数目的细微差异将不影响逻辑电路的性能。在一个实施例中，归因于所需的低电流，在每一群组中可存在大约10个相同装置。单个群组(其表示单个晶体管)中的装置40的成本为大约0.143美分。因此，所得电路板可相对廉价地制成。
如图11中所示，为了简化可印刷为有序二维阵列的群组的编程，源于所有群组的导体层(图4)的导电迹线85可终接在衬底50上的贴片区域86处，其中产品现为可编程电路板87。此类迹线85可为电路板87的“标准”设计的部分，其随后接着经自定义用于特定用途。此使得用于形成迹线85的印刷工艺能够经优化以连接到群组中的导体层且使编程工艺能够经优化用于使端子88的末端互连。例如，编程工艺可在已制作电路板87之后的时间执行且编程步骤可由特殊设备在计算机控制下执行。此外，互连的图案可比将晶体管端子电连接到贴片区域86的迹线85复杂得多。
在图11的实例中，贴片区域86中的编程形成图10的AND门。对于更复杂的电路，编程迹线90可能需交叉，且可形成多个层以避免迹线的短路。
在另一实施例中，装置40的群组最初可邻近群组互连以形成单独逻辑门，例如AND、NAND、NOR门，且每一门的引线终接在贴片区域86中用于随后编程以针对特定客户自定义衬底。因此，通用电路形成可编程门阵列。
多个间隔的贴片区域可被提供在电路板87上以简化互连的布线。在一个实施例中，针对所有输入信号的端子被提供在贴片区域中的一个层级上，且输出端子被提供在另一层级上。
如果互连的编程是复杂的，那么将互连直接印刷在衬底50上的X-Y平面中可能是不够的。将导体直接印刷在衬底上是有限制的，因为导体之间的最小间隔是大约30微米以避免交叉桥接，且薄导体具有由于表面张力破裂的倾向。
在不期望直接印刷导体线的情况中，首先在衬底上形成掩模层，接着如下般在掩模层上方沉积导体墨水。
图案化互连迹线或图案化电路板87上的任何其它迹线或图案化装置40的群组的一条途径是形成疏水掩模。掩模可通过印刷(例如，使用经图案化辊或丝网印刷)而沉积或可通过光微影工艺(如果印刷无法实现所需精度)图案化。一种适当掩蔽物质是浸泡于作为墨水的溶液中的经彻底清洁的硅藻土粒子。以相对于所需配接线/装置图案为负片的图案印刷墨水。在固化后，所得膜经由氟化工艺活化，从而产生超疏水表面(即，其不会被导体墨水或装置墨水润湿)。由膜暴露的衬底的区域将适度亲水或超亲水(即，其会被导体墨水或装置墨水润湿)。
为形成迹线，亲水导电墨水经制备且沉积在疏水掩模上方。暴露的衬底区域将被墨水覆盖，且已沉积在疏水掩模表面上的导电墨水将堆积在暴露区域中。此产生导电墨水的更大横截面积(针对良好导电性及机械强度)且防止交叉桥接。
图12是界定暴露衬底的区域96的疏水掩模94的俯视图。图13是展示形成在区域96中的一者中的单个导体98的横截面图。注意，导体98比掩模94厚。导体98的高度是由沉积在掩模上方的导电墨水量确定。对于界定衬底的大暴露区域的掩模，需要沉积更多导电墨水以确保暴露区域被墨水完全覆盖。在迹线的终接区域处，例如为了将迹线的末端连接到其它导体，应形成扩大的衬垫区域以缓解针对后续印刷层的对准容限且改进所得电连接。
在固化导电墨水之后，随后在相同掩模上方沉积电介质墨水，其中电介质墨水含有足够的表面活性剂以覆盖掩模表面及导体且中和掩模的疏水效应。额外掩模及迹线层可经形成以产生互连的三维矩阵。垂直通孔可用于导体层之间的互连。
图14图解说明当产生群组72与74之间的互连以形成AND门时在图11的电路板87上方使用疏水掩模100。在另一实施例中，掩模100只在贴片区域86中用于编程，且在印刷群组的各种导体层时形成引到各种群组的迹线85。
此一般掩蔽工艺还可用于图案化装置40的群组及导体层。相同或不同装置的群组可经堆叠以允许形成非常复杂的电路。
在已形成电路板87的标准特征之后，可在卷带式工艺中对大量柔性电路板87廉价地执行编程工艺。在最终编程之后，电路板87可从辊切分。如所见，未使用真空处理或危险材料来制作电路板87及对其编程。
图15图解说明可如何通过将电阻材料胶版印刷或丝网印刷在衬底上而形成图14中的电阻器R1及R2，其中筛网上的掩模界定电阻材料的形状。可使用其它沉积技术。电阻材料的形状(长度、宽度、高度)可确定电阻或连接器102或103沿着电阻材料长度的位置可确定电阻。如果连接器的位置确定电阻，那么所有电阻器可被相同地形成。还可通过将电阻器串联及/或并联互连而选择电阻。
图16图解说明电路板106的仰视图及横截面图，其中已在衬底108的两侧上印刷装置的群组，例如底部上的群组72及74及顶部上的其它群组110及112。迹线114及116使群组互连。通孔118将一侧上的电路连接到另一侧上的电路。在印刷互连层之前，在衬底108中冲出通孔孔洞且用例如UV固化的孔填充导体加以填充。如果形成镜像，那么此简化互连设计，因为两侧上的贴片区域可相同。
可使用环绕式连接器来代替通孔。
由于衬底108可为非常薄及柔性的膜(如柔性电路)，所以所得电路板106可经折叠以减小其大小。由墨水形成的柔性导体可市售。衬底108上可存在特殊区域，其界定可折叠电路板106而不损坏电路的位置。
为了改进电路板的使用的可靠性及灵活性，“基底”电路板120(图17)可经制作以具有特定基本特征及连接端子。在电路板120已经测试及认可后，额外电路板122及124可电附接到基底电路板120以针对特定应用自定义性能。
在图17的实施例中，经测试及认可的电路板122及124具有施加到其表面的粘着剂，粘着剂将粘着到基底电路板120。电路板122及124的端子126与基底电路板120上的端子对准。所述端子126涂布有导电粘着剂。电路板122及124随后与基底电路板120对准且粘着到基底电路板120的表面。在一个实施例中，电路板122及124的“装置侧”面向基底电路板120的装置侧。通过单独形成各种功能单元，测试期间各单元的通过率将更高，且功能单元可以各种组合连接以增加更多功能可能性。
在一个实施例中，电路板122/124在卷带式工艺中形成，且在测试之后，在最终站施加粘着剂。电路板122/124可具有在切分期间切割的测试突片。在切分之后，将电路板122/124粘着到基底电路板120。作为任何实例，一个电路板122可为A/D转换器且另一电路板可为D/A转换器。
图18图解说明用于将电路板122安装到基底电路板120的另一技术。在图18中，在区域128处的电连接位置处对电路板122穿孔。随后，使用电介质粘着剂涂布电路板122的底侧(非装置侧)，且将电路板122粘着到基底电路板120，因此穿孔是在基底电路板120上的连接端子上方。随后，通过穿孔沉积导电粘着剂130以将基底电路板120的端子连接到电路板122的顶部端子。例如，迹线132及134通过导电粘着剂130连接。
此技术还可结合图16的双侧电路板使用。
使用装置的大量冗余阵列(例如，图11中的装置40)以及贴片区域86中的标准无源装置(例如，图11中的电阻器R1到R3)允许电路板具有非常高的通过率且产生随后可根据需要经编程以制成独有装置的可编程电路板。
对于更高密度的装置群组，可印刷群组的多个绝缘层以形成三维结构。垂直通孔可用于接达到各种层。装置的群组可使用垂直对准的群组串联连接。
图19示意图解说明用于通过在卷带式工艺中印刷而制造电路的一个可能组装线。辊136含有衬底材料，且辊138系卷取辊。标记各种站。工艺依序印刷各种层并固化层。胶版印刷优选地用于使用卷带式工艺的印刷。层的数目取决于所印刷的电路及装置的复杂性。取决于特定客户需求，卷带式工艺可产生未经编程的电路板且单独系统可用于最终编程步骤。
本文中使用的各种方向属性(例如，底部、顶部及垂直)不应解释为表达相对于地球表面的绝对方向，而是用于表达当图表被竖直固持时相对于附图的定向。在实际实施例中，此类术语仍适用于产品，而不管产品相对于地球表面的绝对定向如何。
虽然已展示并描述本发明的特定实施例，但是所属领域技术人员应了解可进行改变及修改而不脱离本发明的较宽泛方面，且因此随附权利要求书将在其范围内涵盖落在本发明的真实精神及范围内的所有此类改变及修改。

Claims (15)

1.一种印刷电路，其包括：
衬底；
预成形半导体电装置的多个单独群组，所述预成形半导体电装置已被混合在溶液中，沉积在所述衬底上方且固化，
每一群组含有并联连接于每一群组内的多个实质上相同电装置，并联连接的所有电装置形成单个群组；
每一群组中的并联连接的所有电装置在所述衬底上形成所述电装置的随机二维布置，
其中每一群组中的并联连接的电装置的总数是随机的，
其中每一群组中的所述并联连接的电装置不以任何预定方式彼此对齐；
互连导体图案，其将至少一些所述群组互连在一起以实现电逻辑功能；
至少一个输入端子，其连接到所述互连导体图案以接收输入信号供所述电逻辑功能转换以产生输出信号；以及
至少一个输出端子，其连接到所述互连导体图案以接收所述输出信号。
2.根据权利要求1所述的印刷电路，其中每一群组具有从其相关联群组延伸的至少一个电连接器，其中每一电连接器终接在终接区域处，且其中所述互连导体图案包括在所述终接区域处电连接到所述群组的导体。
3.根据权利要求1所述的印刷电路，其中所述预成形半导体电装置是通过印刷而沉积。
4.根据权利要求1所述的印刷电路，其中所述预成形半导体电装置具有小于200微米的最大尺寸。
5.根据权利要求1所述的印刷电路，其中所述多个单独群组中的每一群组含有实质上相同的第一装置，其中所述多个单独群组是第一多个单独群组，所述印刷电路进一步包括第二多个单独群组，其中所述第二多个群组含有与所述第一装置不同的第二装置。
6.根据权利要求1所述的印刷电路，其中所述预成形半导体电装置包括晶体管或二极管中的至少一者。
7.根据权利要求1所述的印刷电路，其中所述衬底具有贴片区域，其中每一群组具有从其相关联群组延伸且终接在所述贴片区域中的至少一个电连接器，且其中所述互连导体图案包括在所述贴片区域处电连接到所述群组的导体。
8.根据权利要求1所述的印刷电路，其中所述互连导体图案使所述群组互连以形成逻辑门。
9.根据权利要求1所述的印刷电路，其中所述互连导体图案使所述群组互连以执行逻辑功能。
10.根据权利要求1所述的印刷电路，其中所述衬底是第一衬底，所述印刷电路进一步包括含有电子电路的至少第二衬底，其中所述第二衬底具有贴附到所述第一衬底的表面的表面，且其中所述第一衬底上的端子连接到所述第二衬底上的端子。
11.根据权利要求1所述的印刷电路，其中所述群组以二维阵列沉积。
12.一种印刷电路，其包括：
衬底；
预成形半导体电装置的多个单独群组，所述预成形半导体电装置已被混合在溶液中，沉积在所述衬底上方且固化，
每一群组含有并联连接于每一群组内的多个实质上相同电装置，所述电装置随机分布在所述衬底上的每一群组内；
互连导体图案，其将至少一些所述群组互连在一起以实现电逻辑功能；
至少一个输入端子，其连接到所述互连导体图案以接收输入信号供所述电逻辑功能转换以产生输出信号；以及
至少一个输出端子，其连接到所述互连导体图案以接收所述输出信号；
其中所述预成形半导体电装置是三端装置，其具有第一电极、第二电极及第三电极，其中所述第一电极是所述装置的底部电极，所述第三电极是所述装置的顶部电极，且所述第二电极是垂直定位在所述顶部电极与所述底部电极之间的中间电极，所述印刷电路进一步包括：
第一导体层，其在所述衬底上方，其中所述装置的所述第一电极是电连接到所述第一导体层；
第一电介质层，其上覆于所述第一导体层；
第二导体层，其上覆于所述第一电介质层以电接触所述第二电极；以及
第二电介质层，其在所述第二导体层上方；以及
第三导体层，其上覆于所述第二电介质层以电接触所述第三电极，
其中所述电装置是通过所述第一导体层、所述第二导体层及所述第三导体层的组合并联电连接。
13.根据权利要求12所述的印刷电路，其中所述预成形半导体电装置经形成以具有比所述装置的上部宽的下部，所述下部形成架子，其中所述第二电极是形成在所述架子上。
14.根据权利要求12所述的印刷电路，其中所述第二电极偏离所述装置上的介于所述第一电极与所述第三电极之间的中途点。
15.根据权利要求12所述的印刷电路，电信号耦合到所述第一导体层、所述第二导体层及所述第三导体层以并行操作所述电装置。
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US20170125372A1 (en) 2017-05-04
US10964665B2 (en) 2021-03-30
KR101768789B1 (ko) 2017-08-17
US9572249B2 (en) 2017-02-14
CN105144369A (zh) 2015-12-09
KR20150129827A (ko) 2015-11-20
TWI549257B (zh) 2016-09-11
US20140268591A1 (en) 2014-09-18
WO2014160225A4 (en) 2015-01-08

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