CN105141546A

CN105141546A - Method for reducing FIFO (first input first output) overhead in data forwarding process

Info

Publication number: CN105141546A
Application number: CN201510389392.XA
Authority: CN
Inventors: 毕研山; 于治楼; 姜凯
Original assignee: Inspur Group Co Ltd
Current assignee: Inspur Group Co Ltd
Priority date: 2015-07-06
Filing date: 2015-07-06
Publication date: 2015-12-09

Abstract

The invention relates to the technical field of FPGA (field-programmable gate array) based data forwarding, and particularly relates to a method for reducing the FIFO overhead in the data forwarding process. In the invention, an FPGA receives message data, a message load is cached, a message header is transmitted to a follow-up module, message header data is transmitted in each module, and the message load is taken out from the cache after the message header is processed so as to finish data forwarding. The method for reducing the FIFO overhead in the data forwarding process can reduce the FIFO overhead as much as possible under the premise of ensuring that functional requirements and performance requirements are met, thereby significantly reducing the hardware cost of an FPGA board card.

Description

A kind of method reducing FIFO expense in data forwarding process

Technical field

The present invention relates to the data retransmission technical field based on FPGA, particularly a kind of method reducing FIFO expense in data forwarding process.

Background technology

The abbreviation of FIFO, FirstInputFirstOutput, First Input First Output, this is a kind of traditional manner of execution according to the order of sequence, and the instruction be introduced into first completes and retires from office, and and then just performs Article 2 instruction.

Based on FPGA(Field-ProgrammableGateArray, field programmable gate array) data retransmission design in, the requisite parts of module such as FIFO is data buffer storage, message shaping, flow control, strategy are searched, channel selecting.The FIFO size that each module is opened up requires to deposit down the maximum message segment flowing through this module, module is more, the FIFO needed is larger, and under the prerequisite of FPGA internal RAM resource-constrained, the size of FIFO expense directly determines the number that FPGA inside can use RAM resource.

In data forwarding method under prior art, there is no the design of the reduction expense for FIFO.

Summary of the invention

In order to solve the problem of prior art, the invention provides a kind of method reducing FIFO expense in data forwarding process, under the prerequisite ensureing content with funtion, performance requirement, the expense of FIFO can be reduced as much as possible, thus significantly reduce the hardware cost of FPGA board.

The technical solution adopted in the present invention is as follows:

Reduce a method for FIFO expense in data forwarding process, comprise the following steps:

After A, FPGA receive message data, message load buffer memory is got off, heading is sent to subsequent module;

After B, message header processing terminate, take out message load from buffer memory, after being spliced to heading, composition complete message forwards, and completes data retransmission.

In steps A, do not participate in the message load of computing, be only cached in the FIFO of inbound port.

In steps A, participate in each subsequent module of deal with data, only store and process heading data, no longer buffer memory message load.

The beneficial effect that technical scheme provided by the invention is brought is:

1, do not participate in the message load of computing, be only cached in the FIFO of inbound port, participate in each module of deal with data, only store and process heading data, no longer buffer memory message load.

2, after heading data processing, the message load of buffer memory need be taken out, after being spliced to heading, composition complete message forwards, and achieves the forwarding of message.

3, because except inlet module, each module is buffer memory message load no longer separately, and therefore the use amount of FIFO is reduced to 1/N, and N forwards the module number comprised in design.

In sum, adopt method of the present invention, the FIFO use amount in data retransmission face can be reduced to intrinsic 1/N(N and forward the module number comprised in design).It is nervous that this method is applicable to FPGA internal RAM resource, the occasion not high to data traffic requirement.

Accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is a kind of fundamental diagram reducing the method for FIFO expense in data forwarding process of the present invention.

Embodiment

For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.

Embodiment one

As shown in Figure 1, a kind of method reducing FIFO expense in data forwarding process of the present embodiment, its method step is as follows:

After FPGA receives message data, got off by message load buffer memory, heading is sent to subsequent module, what transmit in each module is heading data, after message header processing terminates, takes out message load, complete data retransmission from buffer memory.Do not participate in the message load of computing, be only cached in the FIFO of inbound port, participate in each module of deal with data, only store and process heading data, no longer buffer memory message load.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. reduce a method for FIFO expense in data forwarding process, comprise the following steps:

2. a kind of method reducing FIFO expense in data forwarding process according to claim 1, is characterized in that, in described steps A, does not participate in the message load of computing, is only cached in the FIFO of inbound port.

3. a kind of method reducing FIFO expense in data forwarding process according to claim 1, is characterized in that, in described steps A, participates in each subsequent module of deal with data, only stores and process heading data, no longer buffer memory message load.