CN110995598B

CN110995598B - Variable-length message data processing method and scheduling device

Info

Publication number: CN110995598B
Application number: CN201911099710.3A
Authority: CN
Inventors: 赵姣; 张建杰; 杨珂; 吴汉明
Original assignee: Elownipmicroelectronics Beijing Co ltd
Current assignee: Elownipmicroelectronics Beijing Co ltd
Priority date: 2019-11-12
Filing date: 2019-11-12
Publication date: 2022-03-04
Anticipated expiration: 2039-11-12
Also published as: CN110995598A

Abstract

The invention provides a variable-length message data processing method and a scheduling device, belonging to the field of high-speed transmission of data communication. The data processing method comprises the following steps: receiving and storing the variable length message; inquiring a route according to the address type information carried by the variable length message and acquiring output port information; according to the scheduling strategy of the scheduling device, realizing the scheduling of the corresponding port; and carrying out data exchange. The switching device executes message caching, sequencing and switching copy operation according to the input port and the type of the variable-length message and the destination port; the variable-length message adopts a shared cache storage and virtual output queue mode in a plane, and the cache space is adjusted according to the number of the variable ports. The invention can realize the orderly non-blocking exchange of the unicast and multicast variable-length messages according to the port setting of the exchange device.

Description

Variable-length message data processing method and scheduling device

Technical Field

The invention belongs to the field of high-speed transmission of data communication, and particularly relates to a variable-length message data processing method and a scheduling device.

Background

PCIE (peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard intended to replace the old PCI, PCI-X and AGP bus standards. A typical PCIE topology includes four functional types, Root Complex, Switch, endpoint, and bridge. In the field of variable-length message exchange such as PCIe Switch, the variable-length message data exchange mainly relates to storage and control information exchange, including data storage exchange, flow management, protocol-related sequencing and the like. In the aspect of message data storage, the message data is mainly stored in a cross-bar or Share-memory form, and the scheduling mode is scheduled according to different storage forms. The cross-bar storage mode needs to set a single cache node for each input/output combination, the bit width, depth and number of the cache nodes are fixed, the depth of the cache nodes needs to be calculated according to the line speed requirement, the storage delay and the like, and the cross-bar storage mode has high storage resource waste rate for the exchange of variable length messages and variable port numbers; in the share-memory mode, the utilization rate of the cache is greatly improved compared with the cross-bar mode, but the shared cache needs to perform RR (or WRR) or TDM scheduling on multi-port parallel data, and needs to improve the system clock frequency or the bit width of the internal data-path to meet the requirement of line speed.

In summary, for variable-length packet switching with variable ports (both the number of ports and the data rate of the ports can be changed), the utilization rate of cache resources needs to be improved under the condition of meeting the requirement of line speed, and especially area and power consumption are saved in the asic design.

Disclosure of Invention

Aiming at the problems in the prior art, the invention aims to provide a variable-length message exchange processing method and a scheduling device, so as to improve the utilization rate of variable-length message cache and bus resources in the scene of variable port and port rate, ensure the line speed, avoid cache read-write conflict and meet PCIe ordering rules.

In order to achieve the above object, an aspect of the present invention provides a method for processing variable-length packet data, including the following steps: receiving and storing the data message with indefinite length; inquiring a route according to the address information of the variable-length data message and acquiring port information; according to the scheduling strategy of the scheduling device, realizing the scheduling of the corresponding port; and carrying out data exchange.

Furthermore, a plurality of processing planes are divided in the port, and message processing is independently carried out between the processing planes; the port number is determined according to the message data volume, and matrix type exchange of the source port and the destination port is supported.

Another aspect of the present invention provides a method for storing variable-length message data, including the following steps: storing the message to a shared cache corresponding to the input port according to the input port of the message; checking the port number, the port data rate and the bit width; grouping the cache addresses; selecting a variable-length message storage address; and storing the data of the variable-length message.

Furthermore, the size of the shared cache is determined by the data rate of the enabled port and is in a direct proportion change relationship; the shared cache address comprises a logical address and a physical address, and the physical address and the logical grouping number form the logical address.

Further, the port number, port data rate and bit width are predetermined.

Further, the packet includes a mutual translation between a physical address and a logical address.

Furthermore, when the variable-length message is stored, the variable-length message is stored according to a minimum data unit, one physical or logical address corresponds to a plurality of minimum data units, and the length and the number of each minimum data unit are fixed; the minimum data unit, its length and number are determined by the management overhead and shared cache utilization.

Furthermore, when the variable-length message is stored, one or more messages are stored in one logic or physical storage address of the shared cache; a message is stored in a plurality of physical or logical address units; the addresses of the variable-length messages during reading and writing are output by the virtual output queue.

In another aspect, the present invention provides a variable length packet data scheduling apparatus, including: the system comprises a scheduling key generation module, a scheduling key queue management module and a scheduling key sequencing module, wherein the scheduling key generation module is used for encapsulating message types and lengths, sop/eop and key features required by PCIe sequencing and time for a message to enter an exchange device to form a scheduling key; the scheduling key queue management module is used for combining with the virtual output queue to perform queue scheduling; and the scheduling key sorting module is used for scheduling key sorting and comparison and comprises a scheduling key sorting and comparison unit and a cache unit of the scheduling key.

Further, the work process of the scheduling key queue management module is as follows: the message inquires a routing table according to the type and the address field to obtain a directional port; the scheduling key acquires the state of the virtual output queue corresponding to the outgoing port; if the virtual output queue is empty, writing the scheduling key into the head cache of the virtual output queue; otherwise, writing into the virtual output queue.

Further, the scheduling key sorting and comparing unit of the scheduling key sorting module has the working process that: setting an internal comparison node and an internal comparison level stage according to the number of virtual output queues participating in sequencing and comparison; extracting a key of the scheduling key at the head of the virtual output queue, and writing the key into an input side node; the input side node is compared with the PCIe ordering rule; if the PCIe ordering rule is applied, the ordering and comparison result is finally output, the virtual queue number is obtained and fed back to the cache and the virtual queue management, and the output and the forwarding of the message data are realized.

Further, the internal comparison node in the scheduling key sorting and comparing unit has a working process that: judging whether the stored scheduling keys and the scheduling keys are back-pressed or not; if the next node is empty or the next node successfully competes, forwarding the key to the next node, and receiving the sequencing result of the previous node by the node, otherwise, staying at the node, and continuously keeping the relevant sequencing result of the previous node which cannot be updated to the node; and the scheduling key failing in competition stays at the node of the current level, and meanwhile, the related sequencing result of the previous level cannot be updated to the current level and is continuously reserved.

Further, in the sorting and comparing unit, the number of nodes in the internal comparison level stage is 2ⁱI is 0,1,2, …, and n is the stage number of stage.

Further, the number of stages and the number of nodes in the sorting and comparing unit are determined by the number of queues participating in sorting and comparing.

Furthermore, the cache unit of the scheduling key is set when the organization form of the scheduling queue changes, and scheduling is performed in the multi-plane and between the multi-plane, and the cache unit is used as a buffer between the sequencing and comparing units and is used for adjusting time sequence and pipelining operation.

According to still another aspect of the present invention, there is provided an electronic device, comprising a central processing unit and a memory storing computer-executable instructions, wherein the computer-executable instructions, when executed, cause the processor to execute the above-mentioned variable-length message data processing method.

According to a fifth aspect of the present invention, there is provided a computer readable storage medium having stored thereon computer instructions which, when executed by a processor, implement the above-described variable length message data processing method.

The effect of the invention is that the variable length message exchange processing method and the scheduling device have the following significant technical effects:

(1) shared storage and virtual output queue management of the variable-length messages can be performed according to the variable ports, and the scheduling device can sequentially forward the variable-length messages according to a sequencing rule and a strict time sequence;

(2) the large-scale data storage adopts a shared cache, the scheduling key adopts multi-level organization sequencing and comparison, and flow control, feedback of the shared cache state and reverse scheduling network transmission are added, so that cache resources are saved, the utilization rate of the cache is ensured, the conflict of read-write ports of the shared cache is avoided, and the data forwarding sequence and the data forwarding rate are ensured;

(3) the method can realize flexible connection relation among chips or devices and good resource utilization and data forwarding effects while finishing variable-length data message processing. .

Drawings

FIG. 1 is a flow chart of a method for processing variable-length message data according to the present invention;

FIG. 2 is a flow chart of a method for storing variable length message data according to the present invention;

FIG. 3 is a diagram illustrating a variable length storage mode according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a variable-length message data scheduling apparatus according to the present invention;

FIG. 5 is a diagram illustrating scheduling key ordering performed by a scheduling policy according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a prior art cross-bar mode for storage used in an embodiment of the present invention;

fig. 7 is a schematic diagram illustrating a principle of storing a share-memory pattern in the prior art used in the embodiment of the present invention.

Detailed Description

The invention is further described with reference to the following figures and detailed description.

In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, the following detailed description is made with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Fig. 1 shows a flowchart of a variable length message data processing method according to the present invention. The method comprises the following steps:

s101: receiving and storing the data messages with indefinite length, and receiving message data from an upstream chip controller or a downstream chip controller, wherein the message data comprises unicast messages and multicast messages.

S102: and inquiring the route and acquiring the port information according to the address information of the variable-length data message. In one embodiment, the packet carries a header and payload, and the header includes fields such as the length, type, and address of the packet. Extracting the message type and the address field in the message header, and sending the message type and the address field to a routing module, wherein the routing module feeds back port and copy information; combining a message header and payload together according to the minimum data unit of the shared cache, then dividing the combined message header and payload into equal data segments, and simultaneously applying for an idle address; applying for an idle address, averagely distributing each group sharing the cache to the ports according to the effective port setting and the port rate setting of the switching device, for example, 1 port of 16G and 2 ports of 8G respectively obtain cache resources of 2/1/1 groups; the idle addresses come from physical memory units in the group and are combined into logical addresses according to the serial numbers of the logical groups;

s103: and realizing corresponding port scheduling according to the scheduling strategy of the scheduling device. In one embodiment, a routing result is awaited to return while a scheduling key is generated. The switching device is provided with a counter, the counter counts and fully turns according to the system clock cycle, the current count of the message entering the switching device is used as a clock cycle identifier, and the clock cycle identifier is written into a scheduling key, besides, the scheduling key also comprises the message length, sop/eop, a fan-out identifier, a destination port identifier, the message type and the ID of the message applied to the PCIe ordering rule.

And returning a message routing result, and adding the message storage address into the corresponding virtual VOQ queue.

And selecting whether the scheduling key is written into the queue or directly written into the head of queue cache according to the head of queue cache and the depth of the queue of the corresponding virtual VOQ queue.

And (4) input side sequencing and scheduling, namely selecting a queue to which the message forwarded by the input side to the centralized module belongs according to a first-in message first-out rule and a PCIE (peripheral component interface express) specific sequencing rule.

The scheduling module is divided into multiple stages, wherein the input side scheduling/centralized scheduling and the output side scheduling are performed, and the scheduling key, the scheduling stage and the node of each stage of scheduling are different. Scheduling belongs to control plane functions.

The input side sorting and scheduling and the centralized scheduling cooperate together, the input side is selected to output a virtual queue number, dequeuing is applied to an input side queue chain list management module, the input side queue chain list management module implements dequeuing operation according to the virtual queue number and the message length, a chain list head address of a queue chain list is taken, the physical memory is located through logic- > physical conversion, the physical address is used as a read memory index, and memory data is read.

After the Memory data of the input side is read, separating the message header according to the sop identifier of the message, and sending the message header and the payload as an independent data bus to a control module.

After receiving the message header and payload, the Concentration module caches the map to the output side corresponding to the message output port. The output side buffers process data in the same way as the input side.

And the control plane mainly comprises the scheduling and sorting module, is divided into input side scheduling/centralized scheduling and output side scheduling, shares the sorting and comparing units, and completes comparison of different members according to different queue inputs and caches.

And the input side scheduling module is divided into two stages of comparison and two stages of cache. The dispatching key of the 1 st-level cache comes from the input-side virtual output queue, and the input node of the 1 st-level sorting and comparing unit is the dispatching key of the 1 st-level cache. The level 1 scheduling is divided into independent sequencing comparison planes according to outgoing ports and message types, and the members participating in the scheduling are messages of the same source port. And selecting a scheduling result of each type after the clock identification comparison of the scheduling key and the WRR or RR scheduling, entering the 2 nd-level cache, inputting the scheduling key of the 2 nd-level cache into the 2 nd-level scheduling, and comparing the 2 nd-level scheduling with the PCIe ordering rule. When the last stage is effective, the key at the input side can enter the last stage, the dispatching key in the cache can be extracted forwards, and the cache can request a new message dispatching key from the virtual output queue.

The collocation scheduling is divided into two stages, the principle is the same, and conflict between a destination port and a source port is avoided at the stage.

The output side scheduling only comprises primary scheduling and primary cache, which are carried out in the outgoing port, and PCIe ordering rules are added.

S104: and carrying out data exchange.

Fig. 2 shows a flowchart of a variable length message data storage method according to the present invention. The method comprises the following steps:

s201: storing the message to a shared cache corresponding to the input port according to the input port of the message;

s202: checking the port number, the port data rate and the bit width;

s203: grouping the cache addresses; selecting a variable-length message storage address;

s204: and storing the data of the variable-length message.

In an embodiment, both the port number and the port data rate of the switching apparatus may be configured to change, when the ASIC sets a logical correspondence between the cache and the port, the cache resource corresponds to the data rate of the enabled port, and the larger the data rate is, the more the dynamically allocated cache resources are. The cache resource corresponds to a logical address and a physical address, the physical address and the logical grouping number form the logical address, and the storage address control management uses the logical address. The packet is split into interconversion between physical and logical addresses.

The variable length message is stored according to a minimum data unit data _ unit, one physical or logical address corresponds to a plurality of data _ units, and the length and the number of the data _ units corresponding to one physical address or one logical address are fixed. The minimum data unit can be the minimum message length and can be subdivided, and the smaller the subdivided data _ unit width is, the higher the cache utilization rate is. The method sets the length and the number of the data _ units, and comprehensively considers the cache utilization rate and the data _ unit management overhead.

The variable-length message is stored, and the storage address of the variable-length message is managed by using a virtual output queue VOQ linked list; one logic or physical memory address of the shared cache can have one or more message memories; a message may be stored in multiple physical or logical address units. The addresses of the variable-length messages during reading and writing are output by a virtual output queue VOQ linked list control unit.

Fig. 3 is a schematic diagram illustrating a variable length storage mode according to an embodiment of the present invention, where the storage of the variable length packet data may be managed by using the shared cache manner.

In order to implement non-blocking store-and-forward of the variable length packet, fig. 4 shows a variable length packet data scheduling apparatus according to the present invention, so as to meet the requirement of line speed, avoid read collision, and meet the PCIe ordering rule.

The device includes:

the message scheduling key generation module 310: the message type and length, the sop/eop, key characteristics required by PCIe ordering and the time for the message to enter the switching device are packaged into a message key.

The packet scheduling key queue management module 320: and the message key participates in scheduling according to the VOQ virtual queue, and the message inquires a routing table according to the message type and the address field to obtain the destination port. The message key acquires the state of a virtual output queue corresponding to the outgoing port, the virtual output queue is empty, and the message key is directly written into the head cache of the virtual output queue backwards; otherwise, writing into the virtual output queue.

Scheduling key ordering module 330: including a sort and compare unit 331 of the schedule key and a cache unit 332 of the schedule key. Fig. 5 is a schematic diagram of scheduling key ordering performed by a scheduling policy according to an embodiment of the present invention, and the following explains a scheduling ordering working principle according to this embodiment.

The sorting and comparing unit 331 of the scheduling key sets an internal comparison level stage and an internal comparison node according to the number of virtual queues participating in sorting and comparison. And extracting keys of the virtual output queue head of the scheduling Key, writing the keys into an input side node of the scheduling and comparing unit, performing multi-stage comparison on the input side node, applying PCIe (peripheral component interconnect express) sequencing rules, finally outputting sequencing and comparing results to obtain a virtual queue number, feeding the virtual queue number back to a cache and virtual queue for management, and outputting and forwarding message data.

The node of the sorting and comparing unit stores the scheduling key and the information whether the scheduling key is back-pressed; if the next node is empty or the next node successfully competes, forwarding the key to the next node, and if the node can receive the sequencing result of the previous node, stopping on the node, and if the node cannot update the relevant sequencing result of the previous node to the node, continuing to reserve the node; and the scheduling key failing in competition stays at the node of the current level, and meanwhile, the related sequencing result of the previous level cannot be updated to the current level and is continuously reserved.

The sequencing and comparing unit has only one node in stage0, only 2 nodes in stage1 and only 4 nodes in stage2, and so on, and the number of the stages and the number of the nodes in the sequencing and comparing unit are determined by the number of queues participating in sequencing and comparing.

The sequencing and comparing unit receives backpressure information and controls the state of the port Busy, and the backpressure information is continuously transmitted among stages of each stage and cannot be out of step. The node0 of stage0 of the sequencing and comparing unit represents the sequencing result, receives the control signals of back pressure and non-dequeuing and feeds back the control signals to the virtual output queue, namely the input side of the sequencing and comparing unit step by step.

The cache unit of the scheduling key is arranged when the organization form of the scheduling queue changes, the scheduling is carried out in a multi-plane (plane) and the scheduling is carried out among the planes, and the cache unit is used as the buffer among the sequencing and comparing units and is used for adjusting the time sequence and carrying out the flow operation, so that the processing of conflict avoidance logic is conveniently carried out.

The scheduling device is combined with a sequencing comparison unit and a cache unit 332, so that pipeline scheduling key comparison can be conveniently carried out among all modules of data processing, changes of virtual queue organization forms and sequencing and comparison at all levels are isolated by the cache, and the functions are independent; meanwhile, the cache unit enables PCIe ordering rules, WRR/SP scheduling rules and active flow control rules to be applied conveniently.

It will be appreciated by persons skilled in the art that the method and apparatus of the present invention is not limited to the embodiments described in the specific embodiments, and that the foregoing detailed description is for the purpose of illustrating the invention only and is not to be construed as limiting the invention. Other embodiments will be apparent to those skilled in the art from the following detailed description, which is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method for processing variable-length message data is characterized by comprising the following steps:

receiving and storing the variable length message; inquiring a route according to the address information of the variable-length message and acquiring forwarding output port information; according to the scheduling strategy of the scheduling device, scheduling the message to the corresponding output port is realized; carrying out data exchange; the port number is determined according to the message data volume, and matrix type message exchange of the source port and the destination port is supported.

2. The method according to claim 1, wherein the number of ports is determined according to the amount of packet data, and supports matrixed packet switching between source port and destination port; a plurality of processing planes are divided in the port, and message processing is independently carried out between the processing planes.

3. The method for processing variable-length message data according to claim 1, wherein the receiving and storing the variable-length message comprises the following steps:

storing the message to a shared cache corresponding to the input port according to the input port of the message; checking the port number, the port data rate and the bit width; grouping the cache addresses; selecting a variable-length message storage address; and storing the data of the variable-length message.

4. The method as claimed in claim 3, wherein the size of the shared buffer is determined by the data rate of the enable port and is in a direct change relationship; the shared cache address comprises a logical address and a physical address, and the physical address and the logical grouping number form the logical address.

5. The method of claim 3, wherein the number of ports, port data rate, and bit width are predetermined.

6. The variable length message data processing method of claim 3, wherein the packet includes a mutual translation between a physical address and a logical address.

7. The method according to claim 3, wherein when storing the variable length message, the variable length message is stored according to a minimum data unit, one physical or logical address corresponds to a plurality of minimum data units, and the length and the number of each minimum data unit are fixed; the minimum data unit, its length and number are determined by the management overhead and shared cache utilization.

8. The method according to any one of claims 3 to 7, wherein when storing the variable-length message, one logical or physical memory address of the shared cache has one or more message stores; a message is stored in a plurality of physical or logical address units; the addresses of the variable-length messages during reading and writing are output by the virtual output queue.

9. A variable-length message data scheduling apparatus for scheduling message data processed according to the method of any one of claims 1-8, comprising: a scheduling key generation module, a scheduling key queue management module and a scheduling key sorting module, wherein,

the scheduling key generation module is used for encapsulating the message type and length, sop/eop and key characteristics required by PCIe sequencing and the time for the message to enter the exchange device to form a scheduling key;

the scheduling key queue management module is used for combining with the virtual output queue to perform queue scheduling;

and the scheduling key sorting module is used for scheduling key sorting and comparison and comprises a scheduling key sorting and comparison unit and a cache unit of the scheduling key.

10. The variable-length message data scheduling device according to claim 9, wherein the scheduling key queue management module performs the following steps:

the message inquires a routing table according to the type and the address field to obtain a directional port;

the scheduling key acquires the state of the virtual output queue corresponding to the outgoing port;

if the virtual output queue is empty, writing the scheduling key into the head cache of the virtual output queue; otherwise, writing into the virtual output queue.

11. The variable-length message data scheduling device of claim 9, wherein the scheduling key sorting and comparing unit of the scheduling key sorting module has a working process that:

setting an internal comparison node and an internal comparison level stage according to the number of virtual output queues participating in sequencing and comparison;

extracting a key of the scheduling key at the head of the virtual output queue, and writing the key into an input side node;

the input side node is compared with the PCIe ordering rule;

if the PCIe ordering rule is applied, the ordering and comparison result is finally output, the virtual queue number is obtained and fed back to the cache and the virtual queue management, and the output and the forwarding of the message data are realized.

12. The variable-length packet data scheduling device according to claim 11, wherein the internal comparison node in the scheduling key ordering and comparing unit operates as follows:

judging whether the stored scheduling keys and the scheduling keys are back-pressed or not;

if the next node is empty or the next node successfully competes, forwarding the key to the next node, and simultaneously receiving the sequencing result of the previous node by the node; otherwise, staying at the node of the level, and keeping the related sorting result of the previous level not to be updated to the node of the level;

and the scheduling key failing in competition stays at the node of the current level, and meanwhile, the related sequencing result of the previous level cannot be updated to the current level and is continuously reserved.

13. The variable-length message data scheduling device of claim 11 wherein in the sorting and comparing unit, the number of nodes in the internal comparison level stage is 2ⁱI is 0,1,2, …, n is the number of stages.

14. The variable-length message data scheduling apparatus as claimed in any of claims 11-13, wherein the number of stages and the number of nodes in the sorting and comparing unit are determined by the number of queues participating in sorting and comparing.

15. The variable-length message data scheduling device of claim 14, wherein the cache unit of the scheduling key is configured when the organization form of the scheduling queue changes, and scheduling is performed within a multiplanar plane and between the multiplanar planes, and the cache unit is used as a buffer between the sequencing and comparing unit and is used for adjusting timing sequence and pipelining operation.

16. An electronic device comprising a central processor and a memory storing computer-executable instructions, wherein the computer-executable instructions, when executed, cause the processor to perform the method of any one of claims 1-8.

17. A computer readable storage medium storing one or more programs, which when executed by a processor implement the method of any of claims 1-8.