CN105140282A - 一种基于非自对准cmos结构的太赫兹探测器 - Google Patents
一种基于非自对准cmos结构的太赫兹探测器 Download PDFInfo
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Abstract
基于非自对准CMOS工艺的MOSFET结构的太赫兹探测器,p型衬底209上两个n型掺杂区分别为源极区和漏极区,源极区和漏极区的中央上面为SiO2层,重掺杂多晶硅区为栅极,SiO2层置于栅极与衬底之间,MOSFET源端区域与漏端区域相对于多晶硅栅非对称分布;MOSFET源端区域的LDD扩散到栅极区域下的长度小于漏端区域的LDD扩散到栅极下的长度;或者是MOSFET源端区域的LDD扩散到栅极区域下的长度小于采用自对准工艺技术生产的传统MOSFET的源端区域的LDD?104扩散到栅极区域下的长度;该MOSFET的源端区域与栅极区域的交叠面积小于传统MOSFET的源栅交叠面积;栅极侧面为侧墙氧化硅。
Description
技术领域
本发明涉及太赫兹探测器领域和MOSFET领域,特别是涉及到一种采用非自对准CMOS工艺的MOSFET结构,其可以有效提高太赫兹探测器的性能。
背景技术
太赫兹是一种频率介于红外和微波之间的电磁波。由于太赫兹的空间分辨率和时间分辨率很高使得太赫兹成像技术成为目前研究热点之一。同时许多非金属极性材料对太赫兹射线吸收较小,因此能够探测材料内部信息,加之太赫兹电磁能量较小,不会对物质产生破坏作用,且生物分子振动和转动频率的共振频率均在太赫兹波段,因此太赫兹在安全检查和医学成像领域具有广泛应用前景。
太赫兹探测器是太赫兹成像技术的关键部件之一,其核心是太赫兹天线和混频器(例如CMOS器件)。利用集成电路工艺将太赫兹天线与CMOS混频器集成在芯片上,实现低成本的微小太赫兹探测器件是未来太赫兹技术实用化的重要途径。图1为基于传统自对准CMOS工艺技术的太赫兹探测器中MOSFET结构图。探测器制作在p型衬底109上,两个重掺杂n区形成源端101和漏端102,重掺杂的多晶硅区作为栅103,一层薄SiO2层108使栅与衬底隔离。器件的工作区在栅氧化下的沟道区。如果衬底109是n型衬底,源端101与漏端102是p+型,器件工作原理与上述器件类似,以下不限于此说明。通常CMOS太赫兹探测器结构中MOSFET的源端101和漏端102是对称的,使用时源端101和漏端102的作用可以互换。现有技术在沟道中靠近漏极的附近设置一个低掺杂的漏区(或源区104、105),让该低掺杂的漏区也承受部分电压,这种结构可防止热电子退化效应。实际上,现在这种结构已经成为了大规模集成电路中MOSFET的基本结构。106、107为侧墙氧化硅。
目前,为了获得更高响应的CMOS太赫兹探测器,一般采用先进集成电路制程工艺研制更小的CMOS太赫兹探测器。然而,先进制程工艺的使用使得CMOS太赫兹探测器的成本急剧增加;另一方面研究表明[1],器件的电压响应随器件的输入阻抗变化而变化。当MOSFET器件工作在直流条件时,器件的源栅输入阻抗只与器件的输入端电阻相关;但是当MOSFET的输入信号为高频信号,器件的输入阻抗还要受到输入端寄生电容的影响。MOSFET器件的输入端电容主要由栅源交叠电容、氧化层电容和源与衬底间寄生电容组成,其中栅源交叠电容对器件的输入阻抗起到了重要的作用。对于传统的对称的MOSFET器件,因为采用标准的自对准工艺实现,进行源端离子注入时,由于离子横向扩散,这样就会产生很大的源栅交叠面积。该交叠面积的尺寸越大则源栅交叠电容就越大,导致基于MOSFET的太赫兹探测性能降低。
参考文献:
[1]E.U.Pfeiffer,A.Lisauskas,andH.Roskos“A0.65THzFocal-PlaneArrayinaQuarter-MicronCMOSProcessTechnology”IEEEJournalofSolid-StateCircuits,vol.44,no.7,pp.1968-1976(2009).
发明内容
本发明目的是,针对现有技术的不足,提出一种减小源栅交叠电容的MOSFET探测器新结构。尤其是非自对准MOSFET结构,这种非自对准MOSFET结构通过减小源端离子注入后扩散到栅氧化层下的长度,减小源端区域与栅端区域的交叠面积,从而减小源端寄生交叠电容,提高了MOSFET的输出电压响应率Rv,并降低了器件的噪声等效功率NEP,实现对太赫兹信号的高性能探测。
本发明的技术方案是:基于非自对准CMOS工艺的MOSFET结构的太赫兹探测器,其特征是p型衬底209上两个n型掺杂区分别为源极区201和漏极区202,源极区201和漏极区202的中央上面为SiO2层208,重掺杂多晶硅区为栅极203,SiO2层208置于栅极203与衬底209之间,MOSFET源端区域201与漏端区域202相对于多晶硅栅203非对称分布;MOSFET源端区域的LDD204扩散到栅极区域203下的长度小于漏端区域的LDD205扩散到栅极区域203下的长度;或者是MOSFET源端区域的LDD204扩散到栅极区域203下的长度小于采用自对准工艺技术生产的传统MOSFET的源端区域的LDD104扩散到栅极区域103下的长度;该MOSFET的源端区域201与栅极区域203的交叠面积小于传统MOSFET的源栅交叠面积;栅极侧面为侧墙氧化硅。
该非对称MOSFET栅源交叠面积较小,其具有较小的栅源交叠电容。
基于非自对准CMOS结构的太赫兹探测器的制备方法:实现本发明提出的基于非自对准CMOS工艺的MOSFET结构可以基于传统CMOS工艺技术;进行MOSFET的源端轻掺杂漏工艺(LDD)时,通过改变源端刻蚀掉的光刻胶掩蔽层的位置,来增加源端离子注入区域边缘偏移多晶硅栅极区域边缘的横向距离;进行源端离子重掺杂时,使用与轻掺杂漏工艺相同的光刻胶掩膜板。
通过调节源端离子注入区域边缘与栅极区域边缘的横向距离,减小源端离子注入后扩散到栅极下的长度,实现减小栅极区域与源极区域的交叠电容。
增加源端离子注入区域边缘与栅极区域边缘的横向距离,减小栅极203与源极201之间的交叠电容,从而提高MOSFET的源栅输入阻抗;进而可以有效提高MOSFET的电压响应率并降低噪声等效功率。
轻掺杂漏工艺和源漏重掺杂工艺的步骤:MOSFET进行轻掺杂漏工艺(LDD)时,源端离子注入区域的边缘偏移栅极区域边缘的横向距离为WS;低浓度离子注入后,源端的LDD301扩散到栅极区域303下面的长度LS小于采用自对准工艺技术生产的MOSFET的源端的LDD104扩散到栅极区域103下面的长度;完成CMOS的轻掺杂漏工艺之后,为了防止大剂量的源漏注入过于接近沟道从而导致沟道过短甚至源漏连通,在多晶硅栅的两侧形成二氧化硅侧墙406和407;其实现方案为:在薄膜区利用化学气相淀积设备淀积一层二氧化硅,然后利用干法刻蚀工艺刻掉这层二氧化硅;由于所用刻蚀剂的各向异性,刻蚀掉了绝大部分的二氧化硅,多晶硅的侧墙上保留了一部分二氧化硅;二氧化硅侧墙形成之后,进行源漏重掺杂;
源漏重掺杂工艺所使用的掩膜板409与LDD工艺所使用的掩膜板304为同一块掩膜板;由于侧墙的存在,减小了离子扩散到栅氧化层下面,同时源端离子注入区域偏离栅极区域,增加了扩散之后源端重掺杂区401与栅极区403的横向距离,减小了栅极区域与源端重掺杂区域的交叠面积;通过改变MOSFET的源端离子注入区域偏移栅极区域的横向距离WS,有效地减小了源端的LDD离子注入之后扩散到栅极区域下面的长度LS,从而减小了栅源交叠面积,即减小了栅源交叠电容,提高了探测器的输出电压响应率Rv并降低了噪声等效功率NEP。
所述的MOSFET的探测器的工作方法,在晶体管的栅极203上施加一个直流偏置电压,源端201直流接地,漏端202浮空,从源端201输入太赫兹信号,从漏端202输出探测器响应电压信号。
根据MOSFET的输出电压响应Rv与栅源交叠电容Cgs0的关系公式:
rs为源极区域寄生电阻,rgs为栅-源电阻,ω为太赫兹频率,Cgs为栅源氧化层电容,Cgs0为栅源交叠电容,Vg为栅极工作电压,Vth为器件阈值电压。通过增加MOSFET的源极区域201边缘与栅极区域203边缘之间的横向距离有效地减小栅源实际交叠面积,从而降低栅源交叠电容Cgs0,最终提高晶体管的输出电压响应Rv。另一方面,晶体管的噪声等效功率NEP为:
kB为玻尔兹曼常量,T为绝对温度,Rds为源-漏沟道电阻。由于提高了太赫兹探测器的输出电压响应Rv,晶体管的噪声等效功率也得到了减小,因此采用基于非自对准CMOS工艺技术的MOSFET结构可以获得更好的CMOS太赫兹探测器性能。
本发明的有效效益为:本发明中的基于非自对准CMOS工艺技术的MOSFET结构与基于自对准工艺的MOSFET结构相比,通过增加源端离子注入区域边缘与多晶硅栅极区域边缘之间的横向距离,缩短了源端离子注入之后扩散到栅极氧化层下的长度,有效地减小了源端与栅端之间的交叠电容,从而增加了器件的高频输入阻抗,提高了器件的输出电压响应RV,以及减小了噪声等效功率NEP。
附图说明
图1:基于自对准CMOS工艺技术的对称MOSFET剖面结构图;
图2:采用非自对准CMOS工艺技术的MOSFET剖面结构图;
图3:进行源漏LDD注入的MOSFET剖面结构图;
图4:进行源漏重掺杂注入的MOSFET剖面结构图;
图5:TCAD仿真计算得到的不同源端偏移距离WS下的器件电压响应Rv。
具体实施方式
为使本发明的内容更加清楚,下面将结合附图对本发明实施方式作进一步地详细描述。
图2为本发明所述的可以有效提高太赫兹探测器性能的MOSFET剖面结构图。MOSFET器件制作在p型衬底209上,两个n型掺杂区分别为源极区201和漏极区202,重掺杂多晶硅区为栅极203,栅极与衬底之间是SiO2层208,MOSFET源端区域201与漏端区域202相对于多晶硅栅203非对称分布;该MOSFET源端区域的LDD204扩散到栅极区域203下的长度小于图1所示的采用自对准CMOS工艺技术生产的传统MOSFET源端区域的LDD104扩散到栅极区域103下的长度;该结构MOSFET的源极区域201与栅极区域203的交叠面积比传统结构MOSFET的源栅交叠面积更小。
MOSFET的源极区域201,对其进行离子注入,形成高浓度有源区,当太赫兹天线向其馈入太赫兹信号,则源极201将向漏极202提供大量电子;MOSFET的漏端区域202,对其进行离子注入,形成高浓度有源区,当其接收到源极201提供的电子时,向外输出直流信号;MOSFET的多晶硅栅203,通过施加在栅极203上的直流偏置电压电压,来控制MOSFET的开启及工作状态;源端LDD204,漏端LDD205,该结构可以防止随着沟道长度减小而产生的短沟道效应;侧墙氧化硅206和207,其作用为防止大剂量的源漏注入过于接近沟道从而导致沟道过短甚至源漏连通;栅极二氧化硅层208,其为绝缘介质层,阻挡栅极导通;209为硅衬底。在该结构图中,源端LDD204与SiO2层208的交叠部分小于漏端LDD205与SiO2层208的交叠部分,则该结构的MOSFET的源端201与栅极203之间的交叠电容小于漏端202与栅极203之间的交叠电容。
生产图2所示MOSFET结构的工艺与采用自对准技术生产传统MOSFET的工艺不同,主要区别在于轻掺杂漏工艺和源漏重掺杂工艺。图3为MOSFET进行轻掺杂漏工艺(LDD)时的结构剖面图。301为源端的LDD离子注入区域,302为漏端的LDD离子注入区域,303为多晶硅栅,304为离子注入掩膜板。源端离子注入区域的边缘偏移栅极区域边缘的横向距离为WS。低浓度离子注入后,源端的LDD扩散到栅极区域下面的长度LS小于采用自对准工艺技术生产的MOSFET的源端的LDD扩散到栅极区域下面的长度。完成CMOS的轻掺杂漏工艺之后,为了防止大剂量的源漏注入过于接近沟道从而导致沟道过短甚至源漏连通,要在多晶硅栅的两侧形成侧墙406和407。其实现方案为:在薄膜区利用化学气相淀积设备淀积一层二氧化硅,然后利用干法刻蚀工艺刻掉这层二氧化硅。由于所用刻蚀剂的各向异性,刻蚀掉了绝大部分的二氧化硅,多晶硅的侧墙上保留了一部分二氧化硅。侧墙形成之后,进行源漏重掺杂。图4为MOSFET进行源漏重掺杂工艺的结构剖面图。该步骤工艺所使用的掩膜板409与LDD工艺所使用的掩膜板304为同一块掩膜板。由于侧墙的存在,减小了离子扩散到栅氧化层下面,同时源端离子注入区域偏离栅极区域,进一步增加了扩散之后源端重掺杂区401与栅极区403的横向距离,很大程度上减小了栅极区域与源端重掺杂区域的交叠面积。所以栅极203与源极201的交叠电容主要受LDD离子注入扩散到栅极区域下面的长度LS影响。通过改变MOSFET的源端离子注入区域偏移栅极区域的横向距离WS,有效地减小了源端的LDD离子注入之后扩散到栅极区域下面的长度LS,从而减小了栅源交叠面积,即减小了栅源交叠电容,提高了探测器的输出电压响应率Rv并降低了噪声等效功率NEP。
图5为TCAD仿真软件模拟得到的不同源端偏移距离WS下的器件电压响应Rv。TCAD模拟仿真软件中的器件结构根据图2建立,器件置于p型衬底上,栅长为0.18μm,栅宽为0.6μm;栅极203施加一个直流偏置电压Vg=0.35V;从源端201输入太赫兹信号u(t)=1×10-3sin(ωt)V,其中ω=2πf,f=500GHz;漏极202连接R=1×1012Ω的电阻后接地,该设置下漏极202可等效为浮空状态。测试太赫兹响应电压Vout的电压表与电阻R并联。在所设偏压条件下获得Vout后,进一步通过以下公式计算器件的太赫兹响应:
Pin为信号输入功率。从图5中明显看到,随着器件源端离子注入区偏移多晶硅栅极区的横向距离WS的增大,MOSFET的输出电压响应随之增大。其中WS=20nm的非对称MOSFET结构相对于WS=0nm的对称MOSFET结构,电压响应提高了1.5倍。
通过以上实施案例可以表明,本发明所设计的非对称MOSFET通过增加源端注入区域与多晶硅栅之间的横向距离,从而减小离子横向扩散后源端与栅端的交叠面积,进而减小了栅源的交叠电容。在太赫兹频段下,减小交叠电容而提高了器件的输入阻抗,实现太赫兹探测器的电压响应率提高,噪声等效功率降低。因此该结构可以有效地提高太赫兹探测器的性能。
虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,本发明所述技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作各种的更改和润湿。因此,本发明的保护范围当视权利要求书所界定者为准。
Claims (7)
1.基于非自对准CMOS工艺的MOSFET结构的太赫兹探测器,其特征是p型衬底上两个n型掺杂区分别为源极区和漏极区,源极区和漏极区的中央上面为SiO2层,重掺杂多晶硅区为栅极,SiO2层置于栅极与衬底之间,MOSFET源端区域与漏端区域相对于多晶硅栅非对称分布;MOSFET源端区域的LDD扩散到栅极区域下的长度小于漏端区域的LDD扩散到栅极下的长度;或者是MOSFET源端区域的LDD扩散到栅极区域下的长度小于采用自对准工艺技术生产的传统MOSFET的源端区域的LDD扩散到栅极区域下的长度;该MOSFET的源端区域与栅极区域的交叠面积小于传统MOSFET的源栅交叠面积为非对称MOSFET源栅交叠面积;栅极侧面为侧墙氧化硅。
2.根据权利要求1所述的太赫兹探测器,其特征在于:非对称MOSFET源栅交叠面积小,具有更小的栅源交叠电容。
3.根据权利要求1或2所述的基于非自对准CMOS结构的太赫兹探测器的制备方法,其特征在于:进行MOSFET的源端轻掺杂漏工艺(LDD)时,通过改变源端刻蚀掉的光刻胶掩蔽层的位置,来增加源端离子注入区域边缘偏移多晶硅栅极区域边缘的横向距离;进行源端离子重掺杂时,使用与轻掺杂漏工艺相同的光刻胶掩膜板。
4.根据权利要求3所述的方法,其特征在于:通过调节源端离子注入区域边缘与栅极区域边缘的横向距离,减小源端离子注入后扩散到栅极下的长度,实现减小栅极区域与源极区域的交叠电容。
5.根据权利要求4所述的方法,其特征在于:增加源端离子注入区域边缘与栅极区域边缘的横向距离,减小栅极203与源极201之间的交叠电容,从而提高MOSFET的源栅输入阻抗;进而可以有效提高MOSFET的电压响应率并降低噪声等效功率。
6.根据权利要求3-5之一所述的方法,其特征在于:MOSFET进行轻掺杂漏工艺(LDD)时,源端离子注入区域的边缘偏移栅极区域边缘的横向距离为WS;低浓度离子注入后,源端的LDD301扩散到栅极区域303下面的长度LS小于采用自对准工艺技术生产的MOSFET的源端的LDD104扩散到栅极区域103下面的长度;完成CMOS的轻掺杂漏工艺之后,为了防止大剂量的源漏注入过于接近沟道从而导致沟道过短甚至源漏连通,在多晶硅栅的两侧形成二氧化硅侧墙406和407;其实现方案为:在薄膜区利用化学气相淀积设备淀积一层二氧化硅,然后利用干法刻蚀工艺刻掉这层二氧化硅;由于所用刻蚀剂的各向异性,刻蚀掉了绝大部分的二氧化硅,多晶硅的侧墙上保留了一部分二氧化硅;二氧化硅侧墙形成之后,进行源漏重掺杂;
源漏重掺杂工艺所使用的掩膜板409与LDD工艺所使用的掩膜板304为同一块掩膜板;由于侧墙的存在,减小了离子扩散到栅氧化层下面,同时源端离子注入区域偏离栅极区域,增加了扩散之后源端重掺杂区401与栅极区403的横向距离,减小了栅极区域与源端重掺杂区域的交叠面积;通过改变MOSFET的源端离子注入区域偏移栅极区域的横向距离WS,有效地减小了源端的LDD离子注入之后扩散到栅极区域下面的长度LS,从而减小了栅源交叠面积,即减小了栅源交叠电容,提高了探测器的输出电压响应率R v 并降低了噪声等效功率NEP。
7.根据权利要求1所述的MOSFET的探测器的工作方法,其特征在于:在晶体管的栅极上施加一个直流偏置电压,源端直流接地,漏端浮空,从源端输入太赫兹信号,从漏端输出探测器响应电压信号。
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