CN105140268A - 沟槽型超级结器件的超级结结构 - Google Patents

沟槽型超级结器件的超级结结构 Download PDF

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CN105140268A
CN105140268A CN201510458488.7A CN201510458488A CN105140268A CN 105140268 A CN105140268 A CN 105140268A CN 201510458488 A CN201510458488 A CN 201510458488A CN 105140268 A CN105140268 A CN 105140268A
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CN105140268B (zh
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王飞
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

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Abstract

本发明公开了一种沟槽型超级结器件的超级结结构，在硅衬底上有上层及下层的双层外延，多个平行沟槽穿通上层外延底部位于下层外延中，下层外延的浓度高于上层外延，上层外延的厚度决定了器件的耐压能力。本发明通过上下两层不同厚度和浓度的外延层，上层外延层主要提供耐压能力，下层外延浓度高于上层外延浓度，通过上下两层外延的浓度比例控制来补偿沟槽深度不均匀而导致的耐压性能的波动。

Description

沟槽型超级结器件的超级结结构
技术领域
本发明涉及半导体集成电路制造领域，特别是指一种沟槽型超级结器件的超级结结构。
背景技术
目前沟槽型超级结产品的耐击穿电压能力主要是由在外延层的沟槽内的P型(或者N型)杂质与外延层的N型(或者P型)杂质在反偏电压下产生的耗尽区来提供的。所以耗尽区的有效厚度也就决定了沟槽型超级结产品的击穿电压的高低。
而耗尽区的厚度主要是由沟槽的深度来决定的，所以沟槽的深度的变化，会直接影响沟槽型超级结产品的耐压能力。而沟槽加工的深度的变动程度，也会影响产品的击穿电压的变化程度。
沟槽的深度决定了产品的击穿电压能力，击穿电压的大小与沟槽的深度成正比。击穿电压大致与槽深的关系是击穿电压＝沟槽深度*(15～20)V/μm,而沟槽加工是由刻蚀设备一次性加工出来的，加工时间是指定的，由于设备的状态的变化，会导致批次和批次之间，以及在同一片硅片上的沟槽深度的变化，进而影响产品在批次间以及在硅片上分布的变化。比如如果目前沟槽的深度加工精度控制在±1μm，那么各个产品之间的击穿电压的波动将可能出现至少30V的变化范围，对产品批次性能的稳定性影响很大。
发明内容
本发明所要解决的技术问题是提供一种新型的沟槽型超级结器件的超级结结构，降低产品击穿电压与沟槽深度的依赖性，减小批次产品之间的击穿电压波动范围。
为解决上述问题，本发明所述的沟槽型超级结器件的超级结结构，包含在硅衬底上有上层及下层的双层外延，多个平行沟槽穿通上层外延底部位于下层外延中。
进一步地，所述下层外延的掺杂浓度高于上层外延的掺杂浓度。
进一步地，所述下层外延的掺杂浓度为上层外延的浓度的1.5～10倍。
进一步地，所述上层外延的厚度有器件所需的击穿电压确定：
进一步地，所述下层外延的厚度由沟槽的底部到硅衬底的距离来决定，该距离为沟槽型超级结原胞内沟槽之间间距的50～100％。
本发明所述的沟槽型超级结器件的超级结结构，通过上下两层外延层，上层外延层主要提供耐压能力，下层外延浓度高于上层外延浓度，通过上下两层外延的浓度比例控制来补偿沟槽深度不均匀而导致的耐压性能的波动。
附图说明
图1是本发明沟槽型超级结器件的超级结结构示意图。
附图标记说明
1是衬底，2a是上层外延，2b是下层外延，m是沟槽底部下层外延的厚度，n是沟槽间距。
具体实施方式
本发明所述的沟槽型超级结器件的超级结结构如图1所示，在硅衬底1上有上下两层外延，沟槽的深度要大于上层外延2a的厚度，即多个沟槽穿过上层外延底部位于下层外延2b中。上层外延2a主要提供器件的击穿耐压能力，根据半导体的极限电场强度计算，上层外延2a能够提供的耐压值大概是上层外延2a的厚度*17V/μm。
下层外延2b的浓度大于上层外延2a的浓度。上下两层外延的浓度的比例就是击穿电压的波动范围的比例。下层外延2b的浓度越高，相对于原来单层浓度的产品的击穿波动程度就越小。下层外延2b的浓度可以选择为上层外延2a的浓度的1.5倍到10倍的范围。
由于产品的击穿强度主要有上层外延2a的厚度来决定，下层外延2b的厚度(指沟槽底部剩下的厚度，即图1中m所标识的厚度)对击穿电压的贡献不大，同时厚度的增加也会增加器件的导通电阻，所以选择沟槽底部到硅衬底的距离m为沟槽间距离n的50～100％。
本发明的重点在于利用深槽型超级结产品在深槽底部的耐压和深槽底部的耗尽区展开的宽度相关的特点，将深槽底部附近的外延浓度加大，导致深槽底部的PN结耗尽区的展开程度变小。而击穿电压的能力又和耗尽区的展开宽度相关，这样通过将在下层浓外延部分2b的深沟槽附近的耗尽区展开能力降低，来降低了这一部分能够提供的电压能力，使得产品的耐压能力大部分由上层外延2a的耗尽来提供，而深槽在下一层深度的变化对耐压的贡献随着下层外延2b浓度的变高而降低，进而降低了深槽的深度的变化对击穿电压的影响，也就是工艺波动造成的沟槽的深度的变化不会对产品的耐压产生较大的波动，达到减小产品耐压波动的效果。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (6)

1.一种沟槽型超级结器件的超级结结构，其特征在于：硅衬底上有上层及下层的双层外延，多个平行沟槽穿通上层外延底部位于下层外延中。
2.如权利要求1所述的沟槽型超级结器件的超级结结构，其特征在于：所述下层外延的掺杂浓度高于上层外延的掺杂浓度。
3.如权利要求2所述的沟槽型超级结器件的超级结结构，其特征在于：所述下层外延的掺杂浓度为上层外延的浓度的1.5～10倍。
4.如权利要求1所述的沟槽型超级结器件的超级结结构，其特征在于：所述上层外延提供器件的击穿电压能力，通过上下两层外延的浓度比例控制来补偿沟槽深度不均匀而导致的耐压性能的波动。
5.如权利要求1所述的沟槽型超级结器件的超级结结构，其特征在于：所述上层外延的厚度由器件所需的击穿电压确定：
6.如权利要求1所述的沟槽型超级结器件的超级结结构，其特征在于：所述下层外延的厚度由沟槽的底部到硅衬底的距离来决定，该距离为沟槽型超级结原胞内沟槽之间间距的50～100％。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111370468A (zh) * 2020-04-23 2020-07-03 上海华虹宏力半导体制造有限公司 超级结器件及其制造方法

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US20090085100A1 (en) * 2007-09-28 2009-04-02 Fuji Electric Device Technology Co., Ltd. Semiconductor device
CN103022123A (zh) * 2011-09-21 2013-04-03 上海华虹Nec电子有限公司 超级结半导体器件及其制造方法
CN104009084A (zh) * 2013-02-21 2014-08-27 英飞凌科技奥地利有限公司 在单元区域中带有额定击穿电压的超级结半导体器件
CN104037206A (zh) * 2013-03-08 2014-09-10 上海华虹宏力半导体制造有限公司 超级结器件及制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090085100A1 (en) * 2007-09-28 2009-04-02 Fuji Electric Device Technology Co., Ltd. Semiconductor device
CN103022123A (zh) * 2011-09-21 2013-04-03 上海华虹Nec电子有限公司 超级结半导体器件及其制造方法
CN104009084A (zh) * 2013-02-21 2014-08-27 英飞凌科技奥地利有限公司 在单元区域中带有额定击穿电压的超级结半导体器件
CN104037206A (zh) * 2013-03-08 2014-09-10 上海华虹宏力半导体制造有限公司 超级结器件及制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111370468A (zh) * 2020-04-23 2020-07-03 上海华虹宏力半导体制造有限公司 超级结器件及其制造方法

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