CN105116760A - System for dynamically detecting state of railway retarder based on FPGA - Google Patents

Abstract

The present invention provides an FPGA-based dynamic detection system for the state of railway deceleration tops, which includes a central processing unit module, an AD acquisition module, a USB storage module, a PWM differential output module, a photoelectric encoding pulse counting module, and an RS232 serial port The output display module and a power supply module, AD collection module, USB storage module, PWM differential output module, photoelectric coding pulse counting module, RS232 serial port output display module, and power supply module are all connected to the central processing unit module. The present invention subverts the previous method in which the railway decelerators are judged by experience by railway workers stepping on them, realizes the fully automatic detection of railway decelerators, fills the gap in the field of automatic detection of decelerators, and greatly improves the detection efficiency of decelerators . For the first time, the data collection of the working state of the retarder has been realized, which can be used by relevant professionals for effective data analysis.

Description

FPGA-based dynamic detection system for railway deceleration top status

technical field

The patent of the present invention relates to a dynamic detection system for the state of a railway deceleration jack, especially a dynamic detection system for the state of a railway deceleration top based on FPGA, which belongs to the technical field of automatic detection of railway track systems.

Background technique

The retarder is an essential hydraulic device for controlling the speed of the vehicle in the hump speed regulating system of the railway marshalling station. In order to ensure that the retarder can work normally, it is necessary to carry out quality inspection on the retarder installed on the railway to ensure that it is in normal working condition. However, nowadays, the research on the automatic detection system of the retarder is still very scarce. Most of the state detection of the retarder is judged by the manual experience of the railway workers with their feet. It will cause misjudgment of the quality of the retarder. This has brought serious safety hazards to railway transportation.

As we all know, compared with general microprocessors, FPGA has outstanding advantages such as the shortest design cycle, the lowest development cost, fast processing speed, and flexible design. Nowadays, the research on the automatic detection system of retarder jacks based on FPGA is still very scarce. For hydraulic equipment such as retarder jacks that need to work on railways for many years, once a failure occurs, it will bring great safety hazards to railway transportation. Therefore, study the dynamic detection technology of the retarder state based on the FPGA, study the data storage technology of the working state of the retarder based on the FPGA, develop the real-time display technology of the serial screen based on the FPGA serial port communication, and realize the visualization of the working state of the retarder and the sound and light alarm of the fault state, etc. It is of great significance to realize the safe, stable and trouble-free operation of the retarder for a long time.

Contents of the invention

The purpose of the present invention is to overcome that most of the state detection of deceleration jacks is judged manually by railway workers with their feet, which not only lacks effective data analysis under the current working state of deceleration jacks, but also affects the quality of deceleration jacks. misjudged this defect. The patent of the present invention provides an FPGA-based dynamic detection system for the status of railway deceleration jacks, whose working status is visualized and is conducive to data analysis of the working status of deceleration jacks.

The specific solutions of the present invention are as follows: a dynamic detection system for the state of railway deceleration tops based on FPGA, characterized in that it includes a central processing unit module, an AD acquisition module, a USB storage module, a PWM differential output module, a photoelectric Coded pulse counting module, a RS232 serial port output display module and a power supply module, AD acquisition module, USB storage module, PWM differential output module, photoelectric coded pulse counting module, RS232 serial port output display module, and power supply module are all connected to the central processing unit module .

Further, the AD acquisition module collects data on the braking force of the deceleration jack; the PWM differential output module controls the driver to drive the servo motor, the photoelectric encoder counting module measures the speed of the servo motor, and the RS232 serial port output display module is used to check the working status of the deceleration jack. For real-time display, the USB storage module is used to record the working status data of the speed reducer, and the power supply module supplies power for the entire controller.

Further, the AD acquisition module includes a third resistor, a fourth resistor, an AD conversion chip, a common-mode filter, a first resistor, a first capacitor, a second resistor, a third capacitor, a second capacitor, and a first inductance coil , the fifth capacitor, the fourth capacitor, the second inductance coil, the voltage amplifying chip, the fifth resistor, the sixth resistor, the third inductance coil, the voltage regulating chip, the seventh resistor, and the two output terminals of the common mode filter are respectively passed through The first resistor and the second resistor are connected to both ends of the first capacitor, one end of the first capacitor is connected to a grounded second capacitor, the other end of the first capacitor is connected to a grounded third capacitor, and both ends of the first capacitor are connected to a signal Input the second pin and the third pin of a voltage amplifying chip; the first pin and the eighth pin of the voltage amplifying chip are connected through the seventh resistor, and the fourth pin of the voltage amplifying chip is connected to the grounded first pin The four capacitors are connected, the fourth pin of the voltage amplifying chip is also connected to the second inductance coil and connected to the -12v voltage, the fourth pin of the voltage amplifying chip is also connected to the fourth pin of the voltage regulating chip, and the fourth pin of the voltage amplifying chip The fifth pin is connected to the sixth pin of the voltage regulation chip, the seventh pin of the voltage amplifying chip is connected to the fifth capacitor grounded, and the seventh pin of the voltage amplifying chip is also connected to the first inductance coil and connected to 12v Voltage, the sixth pin of the voltage amplifying chip is connected to the second pin of the voltage regulating chip through the fifth resistor, the second pin of the voltage regulating chip is connected to the sixth pin of the voltage regulating chip through the sixth resistor, the voltage regulating chip The third pin of the chip is connected to 2.5V voltage, the seventh pin of the voltage regulation chip is connected to the third inductance coil, the third inductance coil is connected to 12V voltage, the sixth pin of the voltage regulation chip is converted to AD through the third resistor chip connection, the sixth pin of the voltage regulation chip is connected to the AD conversion chip through the fourth resistor.

Further, the USB storage module includes a USB interface, a sixth capacitor, a seventh capacitor, an eighth capacitor, a crystal oscillator, a file management control chip, a ninth capacitor, a tenth capacitor, an eighth resistor, a light emitting diode, and a central processing unit module They are respectively connected to the first pin, the third pin, the fourth pin, the eighth pin, the fifteenth pin to the twenty-second pin of the file management control chip, and the fifth pin of the file management control chip , the twelfth pin, the twenty-third pin, and the twenty-seventh pin are respectively grounded; the second pin of the file management control chip is connected to the sixth capacitor, and the sixth capacitor is connected to a 3.3V voltage; the file management control chip The ninth pin of the file management control chip is connected to the 3.3V voltage; the tenth pin and the eleventh pin of the file management control chip are respectively connected to the second pin and the third pin of the USB interface; the thirteenth pin of the file management control chip 1. The fourteenth pin is respectively connected to the two ends of the crystal oscillator, and the two ends of the crystal oscillator are respectively connected to the seventh capacitor and the eighth capacitor, and both the seventh capacitor and the eighth capacitor are grounded; the twenty-fourth pin of the file management control chip The eighth resistor is connected to the cathode of the light-emitting diode, and the anode of the light-emitting diode is connected to a voltage of 3.3V; the twenty-eighth pin of the file management control chip is connected to the ninth capacitor and the tenth capacitor of the capacitor, and the twenty-eighth pin of the file management control chip is connected to the capacitor. The eight pins, the ninth capacitor and the tenth capacitor are connected to the 3.3V voltage at the same time, and the ninth capacitor and the tenth capacitor are both grounded.

Further, the PWM differential output module includes a PWM signal connection resistor, a first photoelectric isolation chip, an eleventh capacitor, a ninth resistor, a tenth resistor, a twelfth capacitor, an eleventh resistor, a differential drive chip, a second The photoelectric isolation chip, the thirteenth capacitor, the direction signal connection resistor, the PWM signal connection resistor are connected to the first pin of the first photoelectric isolation chip, the third pin and the fourth pin of the first photoelectric isolation chip, the second photoelectric isolation chip The third pin and the fourth pin of the isolation chip are all grounded, the sixth pin of the first photoelectric isolation chip 38 is connected to the eleventh capacitor, and the eleventh capacitor is grounded, the sixth pin of the first photoelectric isolation chip, The sixth pin of the second photoelectric isolation chip is connected to the eleventh capacitor and the ninth resistor, the eleventh capacitor and the ninth resistor are connected to 5V at the same time, and the fifth pin of the first photoelectric isolation chip is connected to the ninth resistor , the fifth pin of the first photoelectric isolation chip is connected to the twelfth capacitor and the first pin of the differential drive chip, the twelfth capacitor is connected to the ground, and the direction signal connection resistor is connected to the first pin of the second photoelectric isolation chip The fifth pin of the second photoelectric isolation chip is connected to the seventh pin of the differential drive chip, and the fifth pin of the second photoelectric isolation chip is also connected to the tenth resistor.

Further, the photoelectric encoding pulse counting module includes a twelfth resistor, a third photoelectric isolation chip, a thirteenth resistor, a fourteenth resistor, a fourteenth capacitor, a fifteenth resistor, and a double Schmidt inverter chip , the sixteenth resistor, the fourth photoelectric isolation chip, the seventeenth resistor, the first positive input signal is connected to the first pin of the third photoelectric isolation chip through the seventeenth resistor, and the first negative input signal is isolated from the third photoelectric isolation chip The third pin of the chip is connected, the sixth pin of the third photoelectric isolation chip, the sixth pin of the fourth photoelectric isolation chip are connected to 5V voltage, the fourth pin of the third photoelectric isolation chip, the fourth photoelectric isolation chip The fourth pin of the chip is grounded, the fifth pin of the third photoelectric isolation chip is connected to the thirteenth resistor and the fourteenth capacitor, the thirteenth resistor is connected to the 5V voltage, and the fifth pin of the third photoelectric isolation chip Connect the first pin of the dual Schmidt inverter chip through the fifteenth resistor; the second positive input signal is connected with the first pin of the fourth photoelectric isolation chip through the twelfth resistor, and the second negative input signal is connected with the first pin of the fourth photoelectric isolation chip through the twelfth resistor. The third pin of the fourth photoelectric isolation chip is connected, the first pin of the fourth photoelectric isolation chip is connected to the fourteenth resistor, the fourteenth resistor is connected to 5V voltage, the sixteenth resistor is connected to the double Schmidt inverter chip The third pin of the dual Schmidt inverter chip is connected to the ground and the fifth pin is connected to 3.3V voltage.

Further, the RS232 serial port output display module includes a level conversion chip, a fifteenth capacitor, a sixteenth capacitor, a serial port, a seventeenth capacitor, and an eighteenth capacitor, and the serial screen signal passes through the second pin of the serial port, The third pin is respectively connected with the fourteenth pin and the thirteenth pin of the level conversion chip, and the first pin and the third pin of the level conversion chip are respectively connected with the two ends of the fifteenth capacitor; The fourth pin and the fifth pin of the conversion chip are respectively connected to the two ends of the eighteenth capacitor; the second pin of the level conversion chip is connected to the sixteenth pin of the level conversion chip through the sixteenth capacitor, and the power The second pin and the sixteenth pin of the level conversion chip are connected to 3.3V voltage at the same time; the sixth pin of the level conversion chip is grounded through the seventeenth capacitor.

Compared with the prior art, the present invention has the following obvious substantive features and advantages: the present invention is a dynamic detection system for the status of railway deceleration tops based on FPGA, which overturns the experience judgment of railway deceleration tops by trampling on them by railway workers in the past. The way of the quality of the retarder realizes the fully automatic detection of the railway retarder, fills the gap in the field of automatic detection of the retarder, and greatly improves the detection efficiency of the retarder. For the first time, the data collection of the working state of the retarder has been realized, which can be used by relevant professionals for effective data analysis.

Description of drawings

Fig. 1 is the overall principle block diagram of the state dynamic detection system of railway deceleration jack based on FPGA of the present invention.

Fig. 2 is a functional block diagram of the AD acquisition module in the present invention.

Fig. 3 is a functional block diagram of the USB storage module in the present invention.

Fig. 4 is a functional block diagram of a PWM differential output module in the present invention.

Fig. 5 is a functional block diagram of the photoelectric encoding pulse counting module in the present invention.

Fig. 6 is a functional block diagram of the RS232 serial port output display module in the present invention.

Detailed ways

Below in conjunction with accompanying drawing, preferred implementation of the present invention is described in further detail:

Referring to Fig. 1, the state dynamic detection system of railway deceleration top based on FPGA of the present invention comprises a CPU module 1, an AD acquisition module 2, a USB storage module 3, a PWM differential output module 4, a photoelectric code pulse counting module 5 , a RS232 serial port output display module 6 and a power supply module 7, AD acquisition module 2, USB storage module 3, PWM differential output module 4, photoelectric code pulse counting module 5, RS232 serial port output display module 6, and power supply module 7 are all connected with the central Processor module 1 is connected.

The CPU module is composed of FPGA control chip, clock circuit, reset circuit, SDRAM memory chip, EPCS memory chip, AS interface circuit and JTAG interface circuit. The control driver drives the servo motor, the photoelectric encoder counting module measures the speed of the servo motor, the RS232 serial port output display module is used to display the working status of the decelerator in real time, the USB storage module is used to record the working status data of the decelerator, and the power module is the controller for the entire controller. powered by. The power modules are mainly 5V-3.3V, 5V-1.8V, 3.3V-1.2V power conversion chips.

2, the AD acquisition module 2 includes a third resistor 8, a fourth resistor 9, an AD conversion chip 10, a common mode filter 11, a first resistor 12, a first capacitor 13, a second resistor 14, a third capacitor 15, Second capacitor 16, first inductance coil 17, fifth capacitor 18, fourth capacitor 19, second inductance coil 20, voltage amplifying chip 21, fifth resistor 22, sixth resistor 23, third inductance coil 24, voltage regulator Chip 25, the seventh resistor 36, two analog signals AI2+, AI2- enter a common mode filter 11, and the two output ends of the common mode filter are respectively connected to a first capacitor via the first resistor 12 and the second resistor 14 13, one end of the first capacitor 13 is connected to a grounded second capacitor 16, the other end of the first capacitor 13 is connected to a grounded third capacitor 15, and the signal at both ends of the first capacitor 13 is connected to a voltage The second pin and the third pin of the amplifying chip 21; the first pin of the voltage amplifying chip 21 is connected to the eighth pin through the seventh resistor 36, and the fourth pin of the voltage amplifying chip 21 is connected to the grounded pin. The fourth capacitor 19 is connected, the fourth pin of the voltage amplifying chip 21 is also connected to the second inductance coil 20 and connected to the -12v voltage, the fourth pin of the voltage amplifying chip 21 is also connected to the fourth pin of the voltage regulating chip 25 Connect, the fifth pin of the voltage amplification chip 21 is connected with the sixth pin of the voltage regulation chip 25, the seventh pin of the voltage amplification chip 21 is connected with the fifth capacitor 18 of grounding, the seventh pin of the voltage amplification chip 21 Also connected with the first inductance coil 17 and connected to 12v voltage, the sixth pin of the voltage amplifying chip 21 is connected with the second pin of the voltage regulating chip 25 through the fifth resistor 22, and the second pin of the voltage regulating chip 25 passes through The sixth resistor 23 is connected to the sixth pin of the voltage regulating chip 25, the third pin of the voltage regulating chip 25 is connected to 2.5V voltage, the seventh pin of the voltage regulating chip 25 is connected to the third inductance coil 24, and the third pin of the voltage regulating chip 25 is connected to the third inductance coil 24. The inductance coil 24 is connected to 12V voltage, the sixth pin of the voltage regulation chip 21 is connected to the AD conversion chip 10 through the third resistor 8 , and the sixth pin of the voltage regulation chip 21 is connected to the AD conversion chip 10 through the fourth resistor 9 . The collected analog signal is filtered by the filter circuit, the analog voltage signal is amplified by the voltage amplification chip, and the analog signal is converted into a digital signal by the AD conversion chip and transmitted to the central processing unit module. Wherein, the filter circuit is composed of a common mode filter 11 , a first resistor 12 , a first capacitor 13 , a second resistor 14 , a third capacitor 15 , and a second capacitor 16 .

3, the USB storage module 3 includes a USB interface 26, a sixth capacitor 27, a seventh capacitor 28, an eighth capacitor 29, a crystal oscillator 30, a file management control chip 31, a ninth capacitor 32, a tenth capacitor 33, and an eighth resistor 34. Light-emitting diodes 35, the central processing unit module 1 and the first pin, the third pin, the fourth pin, the eighth pin, the fifteenth pin to the twenty-second pin of the file management control chip 31 respectively The fifth pin, the twelfth pin, the twenty-third pin, and the twenty-seventh pin of the file management control chip are respectively grounded; the second pin of the file management control chip is connected to the sixth capacitor 27 , the sixth capacitor 27 is connected to the 3.3V voltage; the ninth pin of the file management control chip is connected to the 3.3V voltage; the tenth pin and the eleventh pin of the file management control chip are connected to the second pin and the eleventh pin of the USB interface 26 respectively The third pin; the thirteenth pin and the fourteenth pin of the file management control chip are connected to the two ends of the crystal oscillator 30 respectively, and the two ends of the crystal oscillator 30 are also connected with the seventh capacitor 28 and the eighth capacitor 29 respectively, and the seventh capacitor 28 and the eighth capacitor 29 are respectively connected. Both the capacitor 28 and the eighth capacitor 29 are grounded; the twenty-fourth pin of the file management control chip is connected to the cathode of the light-emitting diode 35 through the eighth resistor 34, and the anode of the light-emitting diode 35 is connected to a 3.3V voltage; the first pin of the file management control chip The twenty-eighth pin is connected to the ninth capacitor 32 and the tenth capacitor 33 of the capacitor, and the twenty-eighth pin, the ninth capacitor 32, and the tenth capacitor 33 of the file management control chip are connected to 3.3V voltage at the same time, and the ninth capacitor 32, The tenth capacitor 33 is all grounded. The central processing unit module stores the data to be stored in the external U disk through the USB interface after being processed by the file management control chip.

Referring to FIG. 4 , the PWM differential output module 4 includes a PWM signal connection resistor 37 , a first photoelectric isolation chip 38 , an eleventh capacitor 39 , a ninth resistor 40 , a tenth resistor 41 , a twelfth capacitor 42 , and an eleventh resistor 43 , differential drive chip 44, second photoelectric isolation chip 45, thirteenth capacitor 46, direction signal connection resistor 47, central processing unit module 1 output PWM signal, direction signal, PWM signal connection resistance 37 and first photoelectric isolation chip 38 The first pin is connected, the third pin and the fourth pin of the first photoelectric isolation chip 38, the third pin and the fourth pin of the second photoelectric isolation chip 45 are all grounded, the first photoelectric isolation chip 38 of the first pin is grounded. The six pins are connected to the eleventh capacitor 39, the eleventh capacitor 39 is grounded, the sixth pin of the first photoelectric isolation chip 38 and the sixth pin of the second photoelectric isolation chip 45 are all connected to the eleventh capacitor 39, the sixth pin of the second photoelectric isolation chip 45 Nine resistors 40 are connected, the eleventh capacitor 39 and the ninth resistor 40 are connected to 5V voltage at the same time, the fifth pin of the first photoelectric isolation chip 38 is connected to the ninth resistor 40, the fifth pin of the first photoelectric isolation chip 38 is connected to The twelfth capacitor 42 is connected to the first pin of the differential drive chip 44, the twelfth capacitor 42 is connected to the ground, the direction signal connection resistor 47 is connected to the first pin of the second photoelectric isolation chip 45, and the second photoelectric isolation chip The fifth pin of 45 is connected to the seventh pin of the differential drive chip 44 , and the fifth pin of the second photoelectric isolation chip 45 is also connected to the tenth resistor 41 . The central processing unit module sends out an adjustable PWM signal, and the interference signal is removed by the first photoelectric isolation chip and transmitted to the differential output driver chip, which can output two complementary PWM channels and high and low levels.

Referring to Fig. 5, the photoelectric code pulse counting module 5 includes a twelfth resistor 48, a third photoelectric isolation chip 49, a thirteenth resistor 50, a fourteenth resistor 51, a fourteenth capacitor 52, a fifteenth resistor 53, a dual Miter inverter chip 54, the sixteenth resistor 55, the fourth photoelectric isolation chip 56, the seventeenth resistor 57, the first positive input signal 3PAIN+ passes through the seventeenth resistor 57 and the first lead of the third photoelectric isolation chip 49 The pin is connected, the first negative input signal 3PAIN- is connected with the third pin of the third photoelectric isolation chip 49, the sixth pin of the third photoelectric isolation chip 49, and the sixth pin of the fourth photoelectric isolation chip 56 are all connected to 5V Voltage connection, the fourth pin of the third photoelectric isolation chip 49, the fourth pin of the fourth photoelectric isolation chip 56 are all grounded, the fifth pin of the third photoelectric isolation chip 49 is connected to the thirteenth resistor 50, the fourteenth resistor The capacitor 52 is connected, the thirteenth resistor 50 is connected to the 5V voltage, and the fifth pin of the third photoelectric isolation chip 49 is connected to the first pin of the double Schmidt inverter chip 54 through the fifteenth resistor 53; The positive input signal 3PBIN+ is connected to the first pin of the fourth photoelectric isolation chip 56 through the twelfth resistor 48, the second negative input signal 3PBIN- is connected to the third pin of the fourth photoelectric isolation chip 56, and the fourth photoelectric isolation chip The first pin of 56 is connected with the fourteenth resistor 51, the fourteenth resistor 51 is connected with 5V voltage, the sixteenth resistor 55 is connected with the third pin of the double-Schmidt inverter chip 54, and the double-Schmidt inverter The second pin of the inverter chip 54 is grounded and the fifth pin is connected to a voltage of 3.3V. The fourth pin and the sixth pin of the dual Schmidt inverter chip 54 output signals to the CPU module 1 . The photoelectric encoder signal is removed from the interference signal by the photoelectric isolation chip, and then the signal is stabilized by the double Schmidt inverter chip and then input to the central processing module. The central processing module performs pulse counting by determining the phase of the input signal.

Referring to Fig. 6, the RS232 serial port output display module 6 includes a level conversion chip 58, a fifteenth capacitor 59, a sixteenth capacitor 60, a serial port 61, a seventeenth capacitor 62, and an eighteenth capacitor 63, and the serial screen signal passes through the serial port 61 The second pin and the third pin of the level conversion chip 58 are respectively connected to the fourteenth pin and the thirteenth pin, and the first pin and the third pin of the level conversion chip 58 are connected to the tenth pin respectively. The two ends of the fifth capacitor 59; the fourth pin and the fifth pin of the level conversion chip 58 are respectively connected to the two ends of the eighteenth capacitor 63; the second pin of the level conversion chip 58 passes through the sixteenth capacitor 60 and the The sixteenth pin of the level conversion chip 58 is connected, and the second pin and the sixteenth pin of the level conversion chip are connected to 3.3V voltage at the same time; the sixth pin of the level conversion chip 58 passes through the seventeenth capacitor 62 grounding; the eleventh and twelfth pins of the level conversion chip 58 output signals to the CPU module 1 . The serial port screen is connected to the CPU module through the serial port to realize serial port communication.

The clock circuit is introduced into the clock pin of the CPU module by a 50MHz crystal oscillator through a resistance value of 33 ohms.

The working principle of the present invention is: the central processor module sends signals to the PWM differential output module through control instructions, and controls the speed and direction of the servo motor through the output signals of the PWM differential output module, thereby driving the piston rod to press down on the deceleration top. During the process of the decelerator being pressed down, the force sensor converts the oil-gas reaction force generated by the decelerator into a voltage signal. After filtering and amplifying, the data is collected by the AD acquisition module, and then transmitted to the central processing unit module. While the motor is rotating, the photoelectric coded pulse module collects the speed of the motor, and transmits the speed signal to the central processing unit module. After the central processor module processes the collected force signal and speed signal, it can obtain the displacement of the deceleration jack and the oil-gas reaction force value corresponding to different moments, and then store the data in the external U disk through the USB storage module At the same time, the data is displayed on the serial screen in real time through the RS232 serial display module, and the real-time dynamic "time-displacement-force" curve is drawn on the serial screen and the sound and light alarm function is realized.

Claims (7)

1. the railway decelerating state dynamic detection system based on FPGA, it is characterized in that, it comprises a CPU module, an AD acquisition module, a USB memory module, a PWM difference output module, photoelectric coding pulse counter module, a RS232 serial ports output display module and a power module, AD acquisition module, USB memory module, PWM difference output module, photoelectric coding pulse counter module, RS232 serial ports output display module, power module are all connected with CPU module.

2. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described AD acquisition module carries out data acquisition to the damping force of decelerating; PWM difference output module control and drive system drives servomotor, photoelectric encoder counting module measures servomotor rotating speed, RS232 serial ports output display module is used for showing in real time decelerating duty, USB memory module is for recording decelerating operating state data, and power module is that whole controller is powered.

3. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described AD acquisition module comprises the 3rd resistance, 4th resistance, AD conversion chip, common-mode filter, first resistance, first electric capacity, second resistance, 3rd electric capacity, second electric capacity, first telefault, 5th electric capacity, 4th electric capacity, second telefault, voltage amplification chip, 5th resistance, 6th resistance, 3rd telefault, voltage-regulation chip, 7th resistance, two output terminals of common-mode filter are connected the two ends of the first electric capacity respectively with the second resistance through the first resistance, one end of first electric capacity connects the second electric capacity of ground connection, the other end of this first electric capacity connects the 3rd electric capacity of a ground connection, two end signals of the first electric capacity access the second pin of a voltage amplification chip, 3rd pin, first pin of this voltage amplification chip is connected by the 7th resistance with between the 8th pin, 4th pin of voltage amplification chip is connected with the 4th electric capacity of ground connection, 4th pin of voltage amplification chip is also connected with the second telefault and accesses-12v voltage, 4th pin of voltage amplification chip is also connected with the 4th pin of voltage-regulation chip, 5th pin of voltage amplification chip is connected with the 6th pin of voltage-regulation chip, 7th pin of voltage amplification chip is connected with the 5th electric capacity of ground connection, 7th pin of voltage amplification chip is also connected with the first telefault and accesses 12v voltage, 6th pin of voltage amplification chip is connected with the second pin of voltage-regulation chip by the 5th resistance, second pin of voltage-regulation chip is connected with the 6th pin of voltage-regulation chip by the 6th resistance, 3rd pin of voltage-regulation chip is connected with 2.5V voltage, 7th pin of voltage-regulation chip is connected with the 3rd telefault, 3rd telefault connects 12V voltage, 6th pin of voltage-regulation chip is connected with AD conversion chip by the 3rd resistance, 6th pin of voltage-regulation chip is connected with AD conversion chip by the 4th resistance.

4. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described USB memory module comprises USB interface, 6th electric capacity, 7th electric capacity, 8th electric capacity, crystal oscillator, file management control chip, 9th electric capacity, tenth electric capacity, 8th resistance, light emitting diode, CPU module respectively with the first pin of file management control chip, 3rd pin, 4th pin, 8th pin, 15 pin is connected to the 22 pin, 5th pin of file management control chip, 12 pin, 23 pin, 27 pin is ground connection respectively, second pin of file management control chip is connected with the 6th electric capacity, and the 6th electric capacity connects 3.3V voltage, 9th pin of file management control chip connects 3.3V voltage, tenth pin of file management control chip, the 11 pin connect the second pin and the 3rd pin of USB interface respectively, 13 pin of file management control chip, the 14 pin connect the two ends of crystal oscillator respectively, and the two ends of crystal oscillator are also connected with the 7th electric capacity and the 8th electric capacity respectively, the 7th electric capacity and the 8th electric capacity all ground connection, 24 pin of file management control chip is connected with the negative electrode of light emitting diode through the 8th resistance, and the anode of light emitting diode connects 3.3V voltage, 28 pin of file management control chip is connected with electric capacity the 9th electric capacity, the tenth electric capacity, and the 28 pin of file management control chip, the 9th electric capacity, the tenth electric capacity connect 3.3V voltage simultaneously, the 9th electric capacity, the tenth electric capacity all ground connection.

5. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described PWM difference output module comprises pwm signal connecting resistance, first photoelectric isolated chip, 11 electric capacity, 9th resistance, tenth resistance, 12 electric capacity, 11 resistance, differential driving chip, second photoelectric isolated chip, 13 electric capacity, direction signal connecting resistance, pwm signal connecting resistance is connected with the first pin of the first photoelectric isolated chip, the 3rd pin of the first photoelectric isolated chip and the 4th pin, 3rd pin of the second photoelectric isolated chip and the 4th pin all ground connection, the 6th pin of the first photoelectric isolated chip 38 is connected with the 11 electric capacity, the 11 capacity earth, the 6th pin of the first photoelectric isolated chip, 6th pin of the second photoelectric isolated chip all with the 11 electric capacity, 9th resistance connects, the 11 electric capacity, 9th resistance connects 5V voltage simultaneously, and the 5th pin of the first photoelectric isolated chip is connected with the 9th resistance, the 5th pin of the first photoelectric isolated chip and the 12 electric capacity, first pin of differential driving chip connects, 12 electric capacity is connected to the ground, direction signal connecting resistance is connected with the first pin of the second photoelectric isolated chip, 5th pin of the second photoelectric isolated chip is connected with the 7th pin of differential driving chip, and the 5th pin of the second photoelectric isolated chip is also connected with the tenth resistance.

6. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described photoelectric coding pulse counter module comprises the 12 resistance, 3rd photoelectric isolated chip, 13 resistance, 14 resistance, 14 electric capacity, 15 resistance, two Schmidt's inverter chip, 16 resistance, 4th photoelectric isolated chip, 17 resistance, the first positive input signal is connected by first pin of the 17 resistance with the 3rd photoelectric isolated chip, and the first negative input signal is connected with the 3rd pin of the 3rd photoelectric isolated chip, the 6th pin of the 3rd photoelectric isolated chip, 6th pin of the 4th photoelectric isolated chip is all connected with 5V voltage, the 4th pin of the 3rd photoelectric isolated chip, 4th pin all ground connection of the 4th photoelectric isolated chip, the 5th pin of the 3rd photoelectric isolated chip and the 13 resistance, 14 electric capacity connects, and the 13 resistance is connected with 5V voltage, and the 5th pin of the 3rd photoelectric isolated chip accesses the first pin of two Schmidt's inverter chip by the 15 resistance, second positive input signal is connected with the first pin of the 4th photoelectric isolated chip by the 12 resistance, second negative input signal is connected with the 3rd pin of the 4th photoelectric isolated chip, first pin of the 4th photoelectric isolated chip is connected with the 14 resistance, 14 resistance connects 5V voltage, 16 resistance is connected with the 3rd pin of two Schmidt's inverter chip, the second pin ground connection of two Schmidt's inverter chip and the 5th pin connects 3.3V voltage.

7. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described RS232 serial ports output display module comprises level transferring chip, the 15 electric capacity, the 16 electric capacity, serial ports, the 17 electric capacity, the 18 electric capacity, serial ports screen signal is connected with the 14 pin of level transferring chip and the 13 pin respectively through the second pin of serial ports, the 3rd pin, and the first pin of level transferring chip, the 3rd pin connect the two ends of the 15 electric capacity respectively; 4th pin of level transferring chip, the 5th pin connect the two ends of the 18 electric capacity respectively; Second pin of level transferring chip is connected with the 16 pin of level transferring chip through the 16 electric capacity, and the second pin, the 16 pin of level transferring chip connect 3.3V voltage simultaneously; 6th pin of level transferring chip is through the 17 capacity earth.