CN105116760A - System for dynamically detecting state of railway retarder based on FPGA - Google Patents
System for dynamically detecting state of railway retarder based on FPGA Download PDFInfo
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Abstract
The invention provides a system for dynamically detecting the state of a railway retarder based on an FPGA, and the system comprises a CPU module, an AD collection module, a USB storage module, a PWM differential output module, a photoelectric coding pulse counting module, an RS232 serial port output display module, and a power module. The AD collection module, the USB storage module, the PWM differential output module, the photoelectric coding pulse counting module, the RS232 serial port output display module and the power module are respectively connected with the CPU module. The system overturns a conventional mode that a railway retarder is stamped by a foot of a railway worker for experience-based judgment of the quality of the retarder, achieves the full-automatic detection of the railway retarder, fills a gap in the field of automatic detection of the retarder, and greatly improves the detection efficiency of the retarder. The system firstly achieves the data collection of the working state of the retarder, and can be used by the related professionals for effective data analysis.
Description
Technical field
Patent of the present invention relates to a kind of railway decelerating state dynamic detection system, and especially a kind of railway decelerating state dynamic detection system based on FPGA, belongs to railway rail system test technique automatic field.
Background technology
Decelerating is the requisite hydraulically operated equipment (HOE) of one in marshaling yard hump speed control system, vehicle being carried out to speeds control.In order to ensure that decelerating can normally work, need to carry out quality testing to the decelerating that railway has been installed, to guarantee that it is in normal duty.But, nowadays the research of decelerating automatic checkout system is also very deficient, the state-detection of decelerating is mostly carried out artificial experience with pin to its mode of trampling by railway worker and is judged, not only lack data analysis effective under the current duty of decelerating, and erroneous judgement can be produced to the quality of decelerating.This brings serious potential safety hazard to transportation by railroad.
As everyone knows, compared with general microprocessor, FPGA has the outstanding advantages such as the design cycle is the shortest, development cost are minimum, processing speed is fast, flexible design.Nowadays, the research based on the decelerating automatic checkout system of FPGA is also very deficient, this once break down, can bring very big potential safety hazard to transportation by railroad for this hydraulically operated equipment (HOE) needing to work on the railway year in year out of decelerating.Therefore, study the decelerating state dynamic detection technology based on FPGA, study the decelerating operating state data memory technology based on FPGA, develop the serial ports screen real-time display technology based on FPGA serial communication, realizing the function such as decelerating visible working state, malfunction sound and light alarm, having great importance for realizing safe, stable, the long-time non-fault operation of decelerating.
Summary of the invention
The state-detection that the object of the invention is to overcome decelerating is mostly carried out artificial experience with pin to its mode of trampling by railway worker and is judged, not only lack data analysis effective under the current duty of decelerating, and this defect of erroneous judgement can be produced to the quality of decelerating.Patent of the present invention provides a kind of railway decelerating state dynamic detection system based on FPGA, its visible working state and be conducive to carrying out data analysis to decelerating duty.
The concrete solution of the present invention is as follows: a kind of railway decelerating state dynamic detection system based on FPGA, it is characterized in that, it comprises a CPU module, an AD acquisition module, a USB memory module, a PWM difference output module, photoelectric coding pulse counter module, a RS232 serial ports output display module and a power module, AD acquisition module, USB memory module, PWM difference output module, photoelectric coding pulse counter module, RS232 serial ports output display module, power module are all connected with CPU module.
Further, described AD acquisition module carries out data acquisition to the damping force of decelerating; PWM difference output module control and drive system drives servomotor, photoelectric encoder counting module measures servomotor rotating speed, RS232 serial ports output display module is used for showing in real time decelerating duty, USB memory module is for recording decelerating operating state data, and power module is that whole controller is powered.
Further, described AD acquisition module comprises the 3rd resistance, 4th resistance, AD conversion chip, common-mode filter, first resistance, first electric capacity, second resistance, 3rd electric capacity, second electric capacity, first telefault, 5th electric capacity, 4th electric capacity, second telefault, voltage amplification chip, 5th resistance, 6th resistance, 3rd telefault, voltage-regulation chip, 7th resistance, two output terminals of common-mode filter are connected the two ends of the first electric capacity respectively with the second resistance through the first resistance, one end of first electric capacity connects the second electric capacity of ground connection, the other end of this first electric capacity connects the 3rd electric capacity of a ground connection, two end signals of the first electric capacity access the second pin of a voltage amplification chip, 3rd pin, first pin of this voltage amplification chip is connected by the 7th resistance with between the 8th pin, 4th pin of voltage amplification chip is connected with the 4th electric capacity of ground connection, 4th pin of voltage amplification chip is also connected with the second telefault and accesses-12v voltage, 4th pin of voltage amplification chip is also connected with the 4th pin of voltage-regulation chip, 5th pin of voltage amplification chip is connected with the 6th pin of voltage-regulation chip, 7th pin of voltage amplification chip is connected with the 5th electric capacity of ground connection, 7th pin of voltage amplification chip is also connected with the first telefault and accesses 12v voltage, 6th pin of voltage amplification chip is connected with the second pin of voltage-regulation chip by the 5th resistance, second pin of voltage-regulation chip is connected with the 6th pin of voltage-regulation chip by the 6th resistance, 3rd pin of voltage-regulation chip is connected with 2.5V voltage, 7th pin of voltage-regulation chip is connected with the 3rd telefault, 3rd telefault connects 12V voltage, 6th pin of voltage-regulation chip is connected with AD conversion chip by the 3rd resistance, 6th pin of voltage-regulation chip is connected with AD conversion chip by the 4th resistance.
Further, described USB memory module comprises USB interface, the 6th electric capacity, the 7th electric capacity, the 8th electric capacity, crystal oscillator, file management control chip, the 9th electric capacity, the tenth electric capacity, the 8th resistance, light emitting diode, CPU module is connected to the 22 pin with the first pin of file management control chip, the 3rd pin, the 4th pin, the 8th pin, the 15 pin respectively, the 5th pin of file management control chip, the 12 pin, the 23 pin, the 27 pin ground connection respectively; Second pin of file management control chip is connected with the 6th electric capacity, and the 6th electric capacity connects 3.3V voltage; 9th pin of file management control chip connects 3.3V voltage; Tenth pin of file management control chip, the 11 pin connect the second pin and the 3rd pin of USB interface respectively; 13 pin of file management control chip, the 14 pin connect the two ends of crystal oscillator respectively, and the two ends of crystal oscillator are also connected with the 7th electric capacity and the 8th electric capacity respectively, the 7th electric capacity and the 8th electric capacity all ground connection; 24 pin of file management control chip is connected with the negative electrode of light emitting diode through the 8th resistance, and the anode of light emitting diode connects 3.3V voltage; 28 pin of file management control chip is connected with electric capacity the 9th electric capacity, the tenth electric capacity, and the 28 pin of file management control chip, the 9th electric capacity, the tenth electric capacity connect 3.3V voltage simultaneously, the 9th electric capacity, the tenth electric capacity all ground connection.
Further, described PWM difference output module comprises pwm signal connecting resistance, first photoelectric isolated chip, 11 electric capacity, 9th resistance, tenth resistance, 12 electric capacity, 11 resistance, differential driving chip, second photoelectric isolated chip, 13 electric capacity, direction signal connecting resistance, pwm signal connecting resistance is connected with the first pin of the first photoelectric isolated chip, the 3rd pin of the first photoelectric isolated chip and the 4th pin, 3rd pin of the second photoelectric isolated chip and the 4th pin all ground connection, the 6th pin of the first photoelectric isolated chip 38 is connected with the 11 electric capacity, the 11 capacity earth, the 6th pin of the first photoelectric isolated chip, 6th pin of the second photoelectric isolated chip all with the 11 electric capacity, 9th resistance connects, the 11 electric capacity, 9th resistance connects 5V voltage simultaneously, and the 5th pin of the first photoelectric isolated chip is connected with the 9th resistance, the 5th pin of the first photoelectric isolated chip and the 12 electric capacity, first pin of differential driving chip connects, 12 electric capacity is connected to the ground, direction signal connecting resistance is connected with the first pin of the second photoelectric isolated chip, 5th pin of the second photoelectric isolated chip is connected with the 7th pin of differential driving chip, and the 5th pin of the second photoelectric isolated chip is also connected with the tenth resistance.
Further, described photoelectric coding pulse counter module comprises the 12 resistance, 3rd photoelectric isolated chip, 13 resistance, 14 resistance, 14 electric capacity, 15 resistance, two Schmidt's inverter chip, 16 resistance, 4th photoelectric isolated chip, 17 resistance, first positive input signal is connected with the first pin of the 3rd photoelectric isolated chip by the 17 resistance, first negative input signal is connected with the 3rd pin of the 3rd photoelectric isolated chip, 6th pin of the 3rd photoelectric isolated chip, 6th pin of the 4th photoelectric isolated chip is all connected with 5V voltage, 4th pin of the 3rd photoelectric isolated chip, 4th pin all ground connection of the 4th photoelectric isolated chip, 5th pin of the 3rd photoelectric isolated chip and the 13 resistance, 14 electric capacity connects, 13 resistance is connected with 5V voltage, 5th pin of the 3rd photoelectric isolated chip accesses the first pin of two Schmidt's inverter chip by the 15 resistance, second positive input signal is connected with the first pin of the 4th photoelectric isolated chip by the 12 resistance, second negative input signal is connected with the 3rd pin of the 4th photoelectric isolated chip, first pin of the 4th photoelectric isolated chip is connected with the 14 resistance, 14 resistance connects 5V voltage, 16 resistance is connected with the 3rd pin of two Schmidt's inverter chip, the second pin ground connection of two Schmidt's inverter chip and the 5th pin connects 3.3V voltage.
Further, described RS232 serial ports output display module comprises level transferring chip, the 15 electric capacity, the 16 electric capacity, serial ports, the 17 electric capacity, the 18 electric capacity, serial ports screen signal is connected with the 14 pin of level transferring chip and the 13 pin respectively through the second pin of serial ports, the 3rd pin, and the first pin of level transferring chip, the 3rd pin connect the two ends of the 15 electric capacity respectively; 4th pin of level transferring chip, the 5th pin connect the two ends of the 18 electric capacity respectively; Second pin of level transferring chip is connected with the 16 pin of level transferring chip through the 16 electric capacity, and the second pin, the 16 pin of level transferring chip connect 3.3V voltage simultaneously; 6th pin of level transferring chip is through the 17 capacity earth.
The present invention compared with prior art, there is following apparent substantive distinguishing features and advantage: the present invention is a kind of railway decelerating state dynamic detection system based on FPGA, overturn railway decelerating in the past to be tramped with one's feet by railway worker and step into the mode of row micro-judgment decelerating quality, the full-automation achieving railway decelerating detects, fill up the blank in decelerating Aulomatizeted Detect field, significantly improve decelerating detection efficiency.Achieve the data acquisition of decelerating duty first, effective data analysis can be carried out for skilled addressee.
Accompanying drawing explanation
Fig. 1 is the general principles block diagram of the railway decelerating state dynamic detection system that the present invention is based on FPGA.
Fig. 2 is the theory diagram of AD acquisition module in the present invention.
Fig. 3 is the theory diagram of USB memory module in the present invention.
Fig. 4 is the theory diagram of PWM difference output module in the present invention.
Fig. 5 is photoelectric coding pulse counter module theory diagram in the present invention.
Fig. 6 is the theory diagram of RS232 serial ports output display module in the present invention.
Embodiment
Below in conjunction with accompanying drawing, preferred enforcement of the present invention is described in further detail:
See Fig. 1, the railway decelerating state dynamic detection system that the present invention is based on FPGA comprises a CPU module 1, an AD acquisition module 2, USB memory module 3, PWM difference output module 4, photoelectric coding pulse counter module 5, RS232 serial ports output display module 6 and power module 7, AD acquisition module 2, USB memory module 3, PWM difference output module 4, photoelectric coding pulse counter module 5, RS232 serial ports output display module 6, a power module 7 are all connected with CPU module 1.
CPU module is made up of FPGA control chip, clock circuit, reset circuit, SDRAM storage chip, EPCS storage chip, AS interface circuit, jtag interface circuit, and AD acquisition module carries out data acquisition to the damping force of decelerating; PWM difference output module control and drive system drives servomotor, photoelectric encoder counting module measures servomotor rotating speed, RS232 serial ports output display module is used for showing in real time decelerating duty, USB memory module is for recording decelerating operating state data, and power module is that whole controller is powered.Power module is mainly 5V-3.3V, 5V-1.8V, 3.3V-1.2V power conversion chip.
See Fig. 2, AD acquisition module 2 comprises the 3rd resistance 8, 4th resistance 9, AD conversion chip 10, common-mode filter 11, first resistance 12, first electric capacity 13, second resistance 14, 3rd electric capacity 15, second electric capacity 16, first telefault 17, 5th electric capacity 18, 4th electric capacity 19, second telefault 20, voltage amplification chip 21, 5th resistance 22, 6th resistance 23, 3rd telefault 24, voltage-regulation chip 25, 7th resistance 36, two simulating signal AI2+, AI2-enters a common-mode filter 11, two output terminals of this common-mode filter are connected the two ends of first electric capacity 13 respectively with the second resistance 14 through the first resistance 12, one end of this first electric capacity 13 connects the second electric capacity 16 of a ground connection, the other end of this first electric capacity 13 connects the 3rd electric capacity 15 of a ground connection, two end signals of the first electric capacity 13 access the second pin of a voltage amplification chip 21, 3rd pin, first pin of this voltage amplification chip 21 is connected by the 7th resistance 36 with between the 8th pin, 4th pin of voltage amplification chip 21 is connected with the 4th electric capacity 19 of ground connection, 4th pin of voltage amplification chip 21 is also connected with the second telefault 20 and accesses-12v voltage, 4th pin of voltage amplification chip 21 is also connected with the 4th pin of voltage-regulation chip 25, 5th pin of voltage amplification chip 21 is connected with the 6th pin of voltage-regulation chip 25, 7th pin of voltage amplification chip 21 is connected with the 5th electric capacity 18 of ground connection, 7th pin of voltage amplification chip 21 is also connected with the first telefault 17 and accesses 12v voltage, 6th pin of voltage amplification chip 21 is connected with the second pin of voltage-regulation chip 25 by the 5th resistance 22, second pin of voltage-regulation chip 25 is connected with the 6th pin of voltage-regulation chip 25 by the 6th resistance 23, 3rd pin of voltage-regulation chip 25 is connected with 2.5V voltage, 7th pin of voltage-regulation chip 25 is connected with the 3rd telefault 24, 3rd telefault 24 connects 12V voltage, 6th pin of voltage-regulation chip 21 is connected with AD conversion chip 10 by the 3rd resistance 8, 6th pin of voltage-regulation chip 21 is connected with AD conversion chip 10 by the 4th resistance 9.Collection analog passband signal is crossed filtering circuit and is carried out signal filtering, carries out analog voltage signal amplification, be converted to digital signal import CPU module into through AD conversion chip simulating signal through voltage amplification chip.Wherein, filtering circuit is made up of common-mode filter 11, first resistance 12, first electric capacity 13, second resistance 14, the 3rd electric capacity 15, second electric capacity 16.
See Fig. 3, USB memory module 3 comprises USB interface 26, the 6th electric capacity 27, the 7th electric capacity 28, the 8th electric capacity 29, crystal oscillator 30, file management control chip 31, the 9th electric capacity 32, the tenth electric capacity 33, the 8th resistance 34, light emitting diode 35, CPU module 1 is connected to the 22 pin with the first pin of file management control chip 31, the 3rd pin, the 4th pin, the 8th pin, the 15 pin respectively, the 5th pin of file management control chip, the 12 pin, the 23 pin, the 27 pin ground connection respectively; Second pin of file management control chip is connected with the 6th electric capacity 27, and the 6th electric capacity 27 connects 3.3V voltage; 9th pin of file management control chip connects 3.3V voltage; Tenth pin of file management control chip, the 11 pin connect the second pin and the 3rd pin of USB interface 26 respectively; 13 pin of file management control chip, the 14 pin connect the two ends of crystal oscillator 30 respectively, and the two ends of crystal oscillator 30 are also connected with the 7th electric capacity 28 and the 8th electric capacity 29 respectively, the 7th electric capacity 28 and the 8th electric capacity 29 all ground connection; 24 pin of file management control chip is connected with the negative electrode of light emitting diode 35 through the 8th resistance 34, and the anode of light emitting diode 35 connects 3.3V voltage; 28 pin of file management control chip is connected with electric capacity the 9th electric capacity 32, the tenth electric capacity 33,28 pin of file management control chip, the 9th electric capacity 32, the tenth electric capacity 33 connect 3.3V voltage simultaneously, the 9th electric capacity 32, the tenth electric capacity 33 all ground connection.CPU module, by needing the data stored after the process of file management control chip, is deposited in outside USB flash disk by USB interface.
Pwm signal connecting resistance 37 is comprised see Fig. 4, PWM difference output module 4, first photoelectric isolated chip 38, 11 electric capacity 39, 9th resistance 40, tenth resistance 41, 12 electric capacity 42, 11 resistance 43, differential driving chip 44, second photoelectric isolated chip 45, 13 electric capacity 46, direction signal connecting resistance 47, CPU module 1 output pwm signal, direction signal, pwm signal connecting resistance 37 is connected with the first pin of the first photoelectric isolated chip 38, the 3rd pin of the first photoelectric isolated chip 38 and the 4th pin, 3rd pin of the second photoelectric isolated chip 45 and the 4th pin all ground connection, the 6th pin of the first photoelectric isolated chip 38 is connected with the 11 electric capacity 39, the 11 electric capacity 39 ground connection, the 6th pin of the first photoelectric isolated chip 38, 6th pin of the second photoelectric isolated chip 45 all with the 11 electric capacity 39, 9th resistance 40 connects, the 11 electric capacity 39, 9th resistance 40 connects 5V voltage simultaneously, and the 5th pin of the first photoelectric isolated chip 38 is connected with the 9th resistance 40, the 5th pin of the first photoelectric isolated chip 38 and the 12 electric capacity 42, first pin of differential driving chip 44 connects, 12 electric capacity 42 is connected to the ground, direction signal connecting resistance 47 is connected with the first pin of the second photoelectric isolated chip 45,5th pin of the second photoelectric isolated chip 45 is connected with the 7th pin of differential driving chip 44, and the 5th pin of the second photoelectric isolated chip 45 is also connected with the tenth resistance 41.CPU module sends adjustable pwm signal, removes undesired signal import difference output driving chip into through the first photoelectric isolated chip, the complementary PWM of exportable two-way and low and high level.
See Fig. 5, photoelectric coding pulse counter module 5 comprises the 12 resistance 48, 3rd photoelectric isolated chip 49, 13 resistance 50, 14 resistance 51, 14 electric capacity 52, 15 resistance 53, two Schmidt's inverter chip 54, 16 resistance 55, 4th photoelectric isolated chip 56, 17 resistance 57, first positive input signal 3PAIN+ is connected with the first pin of the 3rd photoelectric isolated chip 49 by the 17 resistance 57, first negative input signal 3PAIN-is connected with the 3rd pin of the 3rd photoelectric isolated chip 49, the 6th pin of the 3rd photoelectric isolated chip 49, 6th pin of the 4th photoelectric isolated chip 56 is all connected with 5V voltage, the 4th pin of the 3rd photoelectric isolated chip 49, 4th pin all ground connection of the 4th photoelectric isolated chip 56, the 5th pin of the 3rd photoelectric isolated chip 49 and the 13 resistance 50, 14 electric capacity 52 connects, and the 13 resistance 50 is connected with 5V voltage, and the 5th pin of the 3rd photoelectric isolated chip 49 accesses the first pin of two Schmidt's inverter chip 54 by the 15 resistance 53, second positive input signal 3PBIN+ is connected with the first pin of the 4th photoelectric isolated chip 56 by the 12 resistance 48, second negative input signal 3PBIN-is connected with the 3rd pin of the 4th photoelectric isolated chip 56, first pin of the 4th photoelectric isolated chip 56 is connected with the 14 resistance 51, 14 resistance 51 connects 5V voltage, 16 resistance 55 is connected with the 3rd pin of two Schmidt's inverter chip 54, second pin ground connection of two Schmidt's inverter chip 54 and the 5th pin connects 3.3V voltage, 4th pin of two Schmidt's inverter chip 54, 6th pin outputs signal to CPU module 1.Photoelectric encoder signal is removed by two Schmidt's inverter chip stabilization signal input CPU module after undesired signal through photoelectric isolated chip, and CPU module is by carrying out step-by-step counting to the phase determination of input signal.
See Fig. 6, RS232 serial ports output display module 6 comprises level transferring chip the 58, the 15 electric capacity the 59, the 16 electric capacity 60, serial ports the 61, the 17 electric capacity the 62, the 18 electric capacity 63, serial ports screen signal is connected with the 14 pin of level transferring chip 58 and the 13 pin respectively through the second pin of serial ports 61, the 3rd pin, and the first pin of level transferring chip 58, the 3rd pin connect the two ends of the 15 electric capacity 59 respectively; 4th pin of level transferring chip 58, the 5th pin connect the two ends of the 18 electric capacity 63 respectively; Second pin of level transferring chip 58 is connected with the 16 pin of level transferring chip 58 through the 16 electric capacity 60, and the second pin, the 16 pin of level transferring chip connect 3.3V voltage simultaneously; 6th pin of level transferring chip 58 is through the 17 electric capacity 62 ground connection; 11 pin of level transferring chip 58, the 12 pin output signal to CPU module 1.Serial ports screen connects CPU module by serial ports, realizes serial communication.
Clock circuit is introduced the clock pins of CPU module through the resistance that a resistance is 33 ohm by 50MHz crystal oscillator.
Principle of work of the present invention is: CPU module transmits a signal to PWM difference output module by steering order, control servomotor speed and direction, thus driven plunger pole pair decelerating presses down by PWM difference output module output signal.Decelerating is in the process be pressed down, and the oil gas counter-force produced by decelerating by force snesor is transformed into voltage signal, carries out data acquisition, then import CPU module into after amplifying after filtering by AD acquisition module.While electric machine rotation, photoelectric coding pulse module gathers the rotating speed of motor, imports tach signal into CPU module.CPU module by the force signal that collects and rate signal after calculation process, displacement that not corresponding in the same time decelerating presses down and oil gas counter-force value can be obtained, pass through USB memory module again by data stored in outside USB flash disk, data are presented in real time on serial ports screen by RS232 serial ports display module simultaneously, and on serial ports screen, draw in real time dynamically " time m-displacement-force " curve and realize sound and light of alarm.
Claims (7)
1. the railway decelerating state dynamic detection system based on FPGA, it is characterized in that, it comprises a CPU module, an AD acquisition module, a USB memory module, a PWM difference output module, photoelectric coding pulse counter module, a RS232 serial ports output display module and a power module, AD acquisition module, USB memory module, PWM difference output module, photoelectric coding pulse counter module, RS232 serial ports output display module, power module are all connected with CPU module.
2. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described AD acquisition module carries out data acquisition to the damping force of decelerating; PWM difference output module control and drive system drives servomotor, photoelectric encoder counting module measures servomotor rotating speed, RS232 serial ports output display module is used for showing in real time decelerating duty, USB memory module is for recording decelerating operating state data, and power module is that whole controller is powered.
3. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described AD acquisition module comprises the 3rd resistance, 4th resistance, AD conversion chip, common-mode filter, first resistance, first electric capacity, second resistance, 3rd electric capacity, second electric capacity, first telefault, 5th electric capacity, 4th electric capacity, second telefault, voltage amplification chip, 5th resistance, 6th resistance, 3rd telefault, voltage-regulation chip, 7th resistance, two output terminals of common-mode filter are connected the two ends of the first electric capacity respectively with the second resistance through the first resistance, one end of first electric capacity connects the second electric capacity of ground connection, the other end of this first electric capacity connects the 3rd electric capacity of a ground connection, two end signals of the first electric capacity access the second pin of a voltage amplification chip, 3rd pin, first pin of this voltage amplification chip is connected by the 7th resistance with between the 8th pin, 4th pin of voltage amplification chip is connected with the 4th electric capacity of ground connection, 4th pin of voltage amplification chip is also connected with the second telefault and accesses-12v voltage, 4th pin of voltage amplification chip is also connected with the 4th pin of voltage-regulation chip, 5th pin of voltage amplification chip is connected with the 6th pin of voltage-regulation chip, 7th pin of voltage amplification chip is connected with the 5th electric capacity of ground connection, 7th pin of voltage amplification chip is also connected with the first telefault and accesses 12v voltage, 6th pin of voltage amplification chip is connected with the second pin of voltage-regulation chip by the 5th resistance, second pin of voltage-regulation chip is connected with the 6th pin of voltage-regulation chip by the 6th resistance, 3rd pin of voltage-regulation chip is connected with 2.5V voltage, 7th pin of voltage-regulation chip is connected with the 3rd telefault, 3rd telefault connects 12V voltage, 6th pin of voltage-regulation chip is connected with AD conversion chip by the 3rd resistance, 6th pin of voltage-regulation chip is connected with AD conversion chip by the 4th resistance.
4. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described USB memory module comprises USB interface, 6th electric capacity, 7th electric capacity, 8th electric capacity, crystal oscillator, file management control chip, 9th electric capacity, tenth electric capacity, 8th resistance, light emitting diode, CPU module respectively with the first pin of file management control chip, 3rd pin, 4th pin, 8th pin, 15 pin is connected to the 22 pin, 5th pin of file management control chip, 12 pin, 23 pin, 27 pin is ground connection respectively, second pin of file management control chip is connected with the 6th electric capacity, and the 6th electric capacity connects 3.3V voltage, 9th pin of file management control chip connects 3.3V voltage, tenth pin of file management control chip, the 11 pin connect the second pin and the 3rd pin of USB interface respectively, 13 pin of file management control chip, the 14 pin connect the two ends of crystal oscillator respectively, and the two ends of crystal oscillator are also connected with the 7th electric capacity and the 8th electric capacity respectively, the 7th electric capacity and the 8th electric capacity all ground connection, 24 pin of file management control chip is connected with the negative electrode of light emitting diode through the 8th resistance, and the anode of light emitting diode connects 3.3V voltage, 28 pin of file management control chip is connected with electric capacity the 9th electric capacity, the tenth electric capacity, and the 28 pin of file management control chip, the 9th electric capacity, the tenth electric capacity connect 3.3V voltage simultaneously, the 9th electric capacity, the tenth electric capacity all ground connection.
5. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described PWM difference output module comprises pwm signal connecting resistance, first photoelectric isolated chip, 11 electric capacity, 9th resistance, tenth resistance, 12 electric capacity, 11 resistance, differential driving chip, second photoelectric isolated chip, 13 electric capacity, direction signal connecting resistance, pwm signal connecting resistance is connected with the first pin of the first photoelectric isolated chip, the 3rd pin of the first photoelectric isolated chip and the 4th pin, 3rd pin of the second photoelectric isolated chip and the 4th pin all ground connection, the 6th pin of the first photoelectric isolated chip 38 is connected with the 11 electric capacity, the 11 capacity earth, the 6th pin of the first photoelectric isolated chip, 6th pin of the second photoelectric isolated chip all with the 11 electric capacity, 9th resistance connects, the 11 electric capacity, 9th resistance connects 5V voltage simultaneously, and the 5th pin of the first photoelectric isolated chip is connected with the 9th resistance, the 5th pin of the first photoelectric isolated chip and the 12 electric capacity, first pin of differential driving chip connects, 12 electric capacity is connected to the ground, direction signal connecting resistance is connected with the first pin of the second photoelectric isolated chip, 5th pin of the second photoelectric isolated chip is connected with the 7th pin of differential driving chip, and the 5th pin of the second photoelectric isolated chip is also connected with the tenth resistance.
6. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described photoelectric coding pulse counter module comprises the 12 resistance, 3rd photoelectric isolated chip, 13 resistance, 14 resistance, 14 electric capacity, 15 resistance, two Schmidt's inverter chip, 16 resistance, 4th photoelectric isolated chip, 17 resistance, the first positive input signal is connected by first pin of the 17 resistance with the 3rd photoelectric isolated chip, and the first negative input signal is connected with the 3rd pin of the 3rd photoelectric isolated chip, the 6th pin of the 3rd photoelectric isolated chip, 6th pin of the 4th photoelectric isolated chip is all connected with 5V voltage, the 4th pin of the 3rd photoelectric isolated chip, 4th pin all ground connection of the 4th photoelectric isolated chip, the 5th pin of the 3rd photoelectric isolated chip and the 13 resistance, 14 electric capacity connects, and the 13 resistance is connected with 5V voltage, and the 5th pin of the 3rd photoelectric isolated chip accesses the first pin of two Schmidt's inverter chip by the 15 resistance, second positive input signal is connected with the first pin of the 4th photoelectric isolated chip by the 12 resistance, second negative input signal is connected with the 3rd pin of the 4th photoelectric isolated chip, first pin of the 4th photoelectric isolated chip is connected with the 14 resistance, 14 resistance connects 5V voltage, 16 resistance is connected with the 3rd pin of two Schmidt's inverter chip, the second pin ground connection of two Schmidt's inverter chip and the 5th pin connects 3.3V voltage.
7. the railway decelerating state dynamic detection system based on FPGA according to claim 1, it is characterized in that, described RS232 serial ports output display module comprises level transferring chip, the 15 electric capacity, the 16 electric capacity, serial ports, the 17 electric capacity, the 18 electric capacity, serial ports screen signal is connected with the 14 pin of level transferring chip and the 13 pin respectively through the second pin of serial ports, the 3rd pin, and the first pin of level transferring chip, the 3rd pin connect the two ends of the 15 electric capacity respectively; 4th pin of level transferring chip, the 5th pin connect the two ends of the 18 electric capacity respectively; Second pin of level transferring chip is connected with the 16 pin of level transferring chip through the 16 electric capacity, and the second pin, the 16 pin of level transferring chip connect 3.3V voltage simultaneously; 6th pin of level transferring chip is through the 17 capacity earth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510138641.8A CN105116760A (en) | 2015-03-27 | 2015-03-27 | System for dynamically detecting state of railway retarder based on FPGA |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510138641.8A CN105116760A (en) | 2015-03-27 | 2015-03-27 | System for dynamically detecting state of railway retarder based on FPGA |
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| CN105116760A true CN105116760A (en) | 2015-12-02 |
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| CN201510138641.8A Pending CN105116760A (en) | 2015-03-27 | 2015-03-27 | System for dynamically detecting state of railway retarder based on FPGA |
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