CN105103296B - High electron mobility field-effect transistor and preparation method thereof - Google Patents

High electron mobility field-effect transistor and preparation method thereof Download PDF

Info

Publication number
CN105103296B
CN105103296B CN201380024745.5A CN201380024745A CN105103296B CN 105103296 B CN105103296 B CN 105103296B CN 201380024745 A CN201380024745 A CN 201380024745A CN 105103296 B CN105103296 B CN 105103296B
Authority
CN
China
Prior art keywords
layer
grid
drift region
drain electrode
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201380024745.5A
Other languages
Chinese (zh)
Other versions
CN105103296A (en
Inventor
萨梅·哈利勒
卡里姆·S·保特罗斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HRL Laboratories LLC
Original Assignee
HRL Laboratories LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/478,402 external-priority patent/US9000484B2/en
Priority claimed from US13/478,609 external-priority patent/US9379195B2/en
Priority claimed from US13/479,018 external-priority patent/US8680536B2/en
Application filed by HRL Laboratories LLC filed Critical HRL Laboratories LLC
Publication of CN105103296A publication Critical patent/CN105103296A/en
Application granted granted Critical
Publication of CN105103296B publication Critical patent/CN105103296B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A kind of high electron mobility field-effect transistor (HEMT) includes the two-dimensional electron gas (2DEG) in drift region between the gate and the drain, and the 2DEG, which has, to be distributed in the drift region along from the grid to the non-homogeneous transverse direction 2DEG gradually increased on the direction of the drain electrode.

Description

High electron mobility field-effect transistor and preparation method thereof
Cross reference to related applications
This application involves entitled " the HEMT GaN Device with a Non- submitted on May 23rd, 2013 Uniform Lateral Two-Dimensional Electron Gas Profile and Process for The U.S. Patent application No.13/478 of Manufacturing the Same ", further relates to carry on May 23rd, 2012 by No. 609 Entitled " the Non-Uniform Two-Dimensional Electron Gas Profile in III-Nitride HEMT handed over The U.S. Patent application No.13/479 of device ", No. 018, entire contents are incorporated herein by reference.In addition, the application is also It is related to and requires entitled " the Controlling Lateral Two-Dimensional submitted on May 23rd, 2013 Electron Hole Gas HEMT in Type III-Nitride Devices Using Ion Implantation The U.S. Patent application No.13/478 of Through Gray Scale Mask ", No. 402 priority, entire contents pass through Reference is incorporated herein.
Technical field
It is controllable invention shows being arranged in III-nitride device using the ion implanting by grayscale mask High electron mobility transistor (HEMT) of lateral two-dimensional electron gas and preparation method thereof.The present invention relates to group III-nitrides HEMT device, more particularly to the two-dimensional electron gas (2DEG) in drift region.
Background technology
High electron mobility transistor (HEMT) is a kind of knot for having and being formed between the material of two kinds of different band gap The field-effect transistor of (that is, hetero-junctions).Gallium nitride (GaN) HEMT is widely noticed due to its high-power performance.It is answered in power With in the group III-nitride HEMT device of middle use, there is the tradeoff between conducting resistance and breakdown voltage (BV).Due to BV Relationship between conducting resistance is at least secondary relationship, therefore for given drift region length, the improvement of BV can cause FOM in device (is defined as BV2/ Ron) significantly improve.
In the prior art, with uniform 2DEG density group III-nitride HEMT device can cause area of grid it There is peak value electric field in lower or vicinity.This field distribution shape is intended to rectangle, rather than desired can reduce device Drift region unit length breakdown voltage it is trapezoidal.The use of field plate and multistage field plate is adopted for improving field distribution Some technologies.But field plate typically results in the multiple peak values of appearance and can not obtain ideal flat field distribution, And notched profile may be showed.Field plate can also increase gate-drain capacitance.In addition, the increase of field plate series will increase processing again Miscellaneous degree and cost.
The United States Patent (USP) No.7 of Furukawa, 038,253 describes the GaN base device prepared with silicon (Si) technology, wherein Uniform 2DEG distributions are used in drift region.Due to no using any forming skill in the device of this Furukawa Art, breakdown voltage and dynamic on resistance between source and drain are limited by the local enhancing of electric field under area of grid, therefore are needed Conservative design is carried out to the device that the quality factor (figure of merit, FOM) that this device can obtain reduce.
In " the High Breakdown Voltage AlGaN/GaN HEMTs Achieved By of H.Xing etc. In Multiple Field Plates ", describes and use the field shaping technique of more field plates to improve field distribution.But more Plate cannot obtain uniform electric field, may have zigzag distribution, and bring gate-drain capacitance.Implement this device junction Structure can also increase device complexity and cost.
It needs significantly to improve the FOM of group III-nitride HEMT device, it is especially desirable to improve for given drift The breakdown voltage of zone length (is defined as BV so as to improve the FOM of device2/Ron).Embodiment of the invention discloses that above-mentioned The solution of problem and other demands.
Invention content
In first embodiment disclosed herein, a kind of high electron mobility field-effect transistor (HEMT) is included in grid Two-dimensional electron gas (2DEG) in drift region between drain electrode, the 2DEG have in the drift region along from described To the direction of the drain electrode, gradually increased non-homogeneous transverse direction 2DEG is distributed grid.
In another embodiment disclosed herein, a kind of high electron mobility field-effect transistor (HEMT) is included in grid Lattice damage in the drift region of carrier accommodating layer between pole and drain electrode, wherein the lattice damage is in the drift region Edge is gradually decreased from the grid to the direction of the drain electrode in domain.
In another embodiment disclosed herein, a kind of side of manufacture high electron mobility field-effect transistor (HEMT) Method, including：Channel carrier transport layer is formed on substrate；Carrier supply is formed in the channel carrier transport layer Layer；Mask layer is formed on carrier accommodating layer, the mask layer is configured as being aligned with the drift region from grid to drain electrode, And it is configured as from the grid to the variation with transverse direction on the direction of the drain electrode；And injection particle is across described Mask layer and the entrance carrier accommodating layer.
Pass through detailed description below and attached drawing, it will be clearly shown that these or other feature of the present invention is imitated with advantageous Fruit.In the accompanying drawings and the description, number shows different features, and in whole drawing and description, similar number represents class As feature.
Description of the drawings
Fig. 1 show it is according to an embodiment of the invention ion implanting is controlled using grayscale mask, make it in drift region Taper is presented in domain.
Fig. 2 shows two-dimensional electron gas (2DEG) charge of the taper according to the present invention in III-nitride device is close Degree.
Fig. 3 A to Fig. 3 C are the flow chart according to the method for the making group III-nitride HEMT device of the present invention.
Specific implementation mode
Hereinafter, many concrete details are shown so that various specific embodiments disclosed by the invention are explicitly described. But those skilled in the art are to be understood that the present invention can be in the case where not having detail discussed below Implement.In other cases, well-known characteristic is not described in order to avoid obscuring the present invention.
With reference to figure 1, field-effect transistor (FET) device architecture 10 is shown.FET device structure 10 is included in substrate 12 Iii-v layer (such as GaN layer 14 on (it can be any suitable substrate for being commonly used in growth III-nitride material) With AlGaN layer 16) it stacks.Suitable substrate includes but not limited to silicon (Si), sapphire, silicon carbide (SiC) and body mono-crystal nitride Gallium (GaN).
It may include the GaN grown on substrate 12 or aluminum gallium nitride (AlGaN) buffer layer that iii-v layer heap is folded.Then exist Channel layer, such as GaN layer 14 are grown on buffer layer, are also referred to as channel carrier transport layer.Then grow on gan layers 14 Barrier layer, such as AlGaN layer 16, are also referred to as carrier accommodating layer.It can be arranged between GaN layer 14 and AlGaN layer 16 AlN separate layers are to improve the electric property of device.
Suitable mask layer 50 is grown in AlGaN layer 16, can be Si3N4.The mask layer 50 is as preventing to lead to Cross the mask layer of most of arrival AlGaN layers 16 in the ion of the injection of ion implanting 52.Only make the injection ion of sub-fraction (at the magnetic tape trailer part of Gaussian Profile) reaches AlGaN layer 16, to bring damage to lattice.Successfully arrive at that of AlGaN layer 16 Sub-fraction ion will not ideally penetrate into AlGaN layer 16 too far.
In addition, the drift region that mask layer 50 is configured as between the grid and drain electrode of field-effect transistor (FET) changes Become the concentration of the ion of injection.As shown in fig. 1, mask layer 50 can be used for being formed in a little drift region between 62 and 64 Taper mask layer 60.There are taper mask layer 60 cross direction profiles, height gradually to increase towards drain electrode.In another embodiment In, the mask with various sizes of opening may be used to change the concentration of the ion of injection along drift region.Each mask The a little ion implanting between 62 and 64 can be modulated at so that the lattice damage caused by ion implanting in AlGaN layer 16 (as shown in Figure 2) is more serious at the point 62 of 22 adjacent edges of area of grid, and in the point 64 along drift region close to drain electrode 20 It is lighter to locate (as shown in Figure 2) lattice damage.Mask layer 50 can be configured as offer along drift region from drain electrode 20 nearby points 64 to the linearly increasing lattice damage of the point 62 near grid 22.After ion implantation, which is etched and removes.
The source contact 18 and drain contact 20 in Fig. 2 are formed by evaporation of metal or metal sputtering.Then in source electrode Deposit passivation layer 24 between 18 and drain electrode 20.
Then, source electrode 18 and drain electrode 20 between gate periphery in, by be etched through passivation layer 24 and etch into Enter AlGaN layer 16 to form area of grid.In another embodiment, which can extend through AlGaN layer 16, and portion Divide and enters suitable depth in GaN layer 14.Then, between source electrode 18 and grid 22 and grid 22 and drain electrode 20 it Between region on deposit gate insulating layer 26, and also deposition gate insulating layer 26 extends into the etching of AlGaN layer 16 to be formed The liner of groove.If etching groove extends into GaN layer 14, which also forms and extends into GaN layer 14 Etching groove liner.
After it deposited gate insulating layer 26, ditch is etched by evaporating or sputtering to form gate metal 22 and its is made to fill Slot.
Various alternate passivation layers and metal layer (part as back-end processing) can be formed to improve posting for device The connection of raw resistance and offer and device pads and/or encapsulant.
Using with taper mask layer 60 mask layer 50 or using being opened with different sizes in another embodiment Mouthful mask control distribution of the ion implanting to lattice damage of the control in the drift region of AlGaN layer 14, thus may be used To obtain the flat field distribution in the drift region between grid 22 and drain electrode 20, III group is nitrogenized to provide Quality factor (FOM's) in object HEMT device significantly improves.By controlling ion implanting and thus controlling from grid to leakage Lattice damage in the drift region of pole, thus it is possible to vary the 2DEG 42 in drift region, to form transverse direction heterogeneous 2DEG distributions 44.As shown for example in fig. 2, which gradually increases in drift region along from grid 22 to the direction of drain electrode 20 Greatly.Flat field distribution can be obtained by the non-homogeneous transverse direction 2DEG distributions 44 along drift region, provide quality The improvement of factor (FOM).
It is realized along drift region by applying the lattice damage of taper to carrier accommodating layer (such as AlGaN layer 16) Non-homogeneous transverse direction 2DEG distributions 44, to control damage in this layer or the degree of stress.By using suitable ionic species Reach in carrier accommodating layer across the method for the ion implanting of the mask layer (such as mask layer 50) with tapered profiles The crosswise joint of damage, wherein longitudinal height of mask layer determines cutting for injection projectile (implanted projectiles) Stopping power and range.The tapered profiles of mask layer can be made by grayscale lithography and subsequent etch step.
Selectively, the stress in AlGaN layer 16 can be changed by issuing various sizes of window in the photoresist, The size of the wherein described opening is being the function of lateral distance on from grid to drain directions.In drift region near grid Opening size can be larger or smaller and be gradually reduced or increases towards drain directions opening size in drift region.
The amplitude damaged caused by by by ion implanting locally determines the charge density in the regions 2DEG, because This can obtain 2DEG distributions 44 heterogeneous by laterally changing lattice damage in drift region.If covered by increasing The height of film layer 50 makes the lattice damage caused by ion implanting along drift by reducing the opening size in mask Region is reduced as the function apart from the distance of area of grid, then the density of 2DEG 44 along drift region as distance The function of the distance of area of grid and increase, as shown in Figure 2.
Fig. 3 A to Fig. 3 C are the flow chart according to the method for the making group III-nitride HEMT device of the present invention.
In step 100, channel carrier transport layer 14 is formed on substrate 12.Then in a step 102, it is carried in raceway groove It flows and forms carrier accommodating layer 16 in sub- transport layer 14.In embodiment, by extension manufacturer come forming layer 14 and layer 16.
Then, at step 104, mask layer 50 is formed on carrier accommodating layer 16.Mask layer be configured as with from grid The drift region alignment of best drain electrode, and it is configured as that there are cross directional variations on the direction from grid to drain electrode.Then note Enter ion 52, passes through mask layer 50 and enter carrier accommodating layer 16.
In one embodiment, mask layer is formed in the following manner：In step 108, it is formed and is had using grayscale lithography There are the mask layer of conical section, the thickness of the conical section to be gradually increased on the direction from grid to drain electrode；Then in step In 110, the mask layer is etched to form conical section.
In another embodiment, mask layer is formed in the following manner：In step 112, by applying with photoresist Carrier accommodating layer；And it then in step 114, is formed in the photoresist and issues various sizes of window, the size of window It is gradually reduced on the direction from grid to drain electrode.
Thus according to the requirement of patent statute, invention has been described, it will be appreciated by those skilled in the art that how right The present invention makes modifications and changes so that it meets specific requirement and condition.The present invention disclosed herein can not departed from These modifications and changes are made to the present invention in the case of scope and spirit.
Illustrated above is according to laws and regulations requirement to this hair exemplary and detailed description of preferred embodiment purpose It is bright to be shown and openly.Its purpose is not exhaustive or limits the invention in described (multiple) concrete form, and only uses It is appreciated that how the present invention is adapted to specific purposes or implementation in making others skilled in the art.It obtains employment to this field For technical staff, the possibility modified and changed is obvious.To including tolerance, characteristic size, specific operation The description of the exemplary embodiment of condition, engineering specification etc. is not intended to limit, can change between various implementations or It is changed as state of art changes, does not imply any restrictions.Applicant is according to prior art discloses this Invention, but still expection is further improved, and can make this by considering that these improve (i.e. following " prior art ") Invention will stand good in future.It is intended that the scope of the present invention is by the claims hereof and its equivalence applicatory Object is limited.Unless explicitly stated otherwise, the singulative being related to otherwise in claims is not meant as " one and only one It is a ".In addition, for any element of the present invention, component or method, process steps, no matter these elements, component or step whether It is distinctly claimed in detail in the claims, they are meant to gratuitously contribute to the public.The element of the present invention is unless adopt It is clearly quoted with phrase " device is used for ... ", otherwise cannot be explained according to Section 112 the 6th section of volume 35 of United States Code No. The element of claim, and otherwise step herein can not unless clearly quoted using " including the steps that ... " The method of claim or process steps are explained according to aforesaid clause.
Design：
Following design is at least disclosed herein.
Conceive a kind of 1. high electron mobility field-effect transistors (HEMT), including：
Two-dimensional electron gas (2DEG) in drift region between the gate and the drain, the 2DEG have in the drift Along from the grid to the gradually increased non-homogeneous transverse direction 2DEG distributions of the direction of the drain electrode in region.
Conceive 2. HEMT as described in design 1, further includes：
Lattice damage in the drift region of carrier accommodating layer between the grid and the drain electrode；
Wherein described lattice damage edge in the drift region is gradually decreased from the grid to the direction of the drain electrode.
Conceive 3. HEMT as described in design 1, further includes：
Substrate；
Channel carrier transport layer over the substrate；And
Carrier accommodating layer in the channel carrier transport layer.
HEMT of the design 4. as described in design 3, wherein：
The substrate includes silicon (Si), sapphire, silicon carbide (SiC) or bulk single crystalline gallium nitride (GaN)；
The channel carrier transport layer includes GaN layer；And
The carrier accommodating layer includes AlGaN layer.
Conceive 5. HEMT as described in design 4, further includes：
Passivation layer in the AlGaN layer；And
The wherein described grid includes：
It extends through the passivation layer and enters the gate metal of the AlGaN layer；And
The gate insulating layer of the gate metal around the passivation layer is extended through and into the AlGaN layer.
Conceive 6. HEMT as described in design 4, further includes：
Passivation layer above the AlGaN layer；And
The wherein described grid includes：
It extends through the passivation layer and the AlGaN layer and enters the gate metal of the GaN layer；And
The circular gate metal for extending through the passivation layer and the AlGaN layer and entering the GaN layer Gate insulating layer.
Conceive a kind of 7. high electron mobility field-effect transistors (HEMT), including：
Lattice damage in the drift region of carrier accommodating layer between the gate and the drain；
Wherein described lattice damage edge in the drift region is gradually decreased from the grid to the direction of the drain electrode.
Conceive 8. HEMT as described in design 7, further includes：
The two-dimensional electron gas (2DEG) in the drift region between the grid and the drain electrode, the 2DEG tools Have in the drift region along from the grid to the gradually increased non-homogeneous transverse direction 2DEG distributions of the direction of the drain electrode.
Conceive 9. HEMT as described in design 7, further includes：
Substrate；
Channel carrier transport layer over the substrate；And
Carrier accommodating layer in the channel carrier transport layer.
HEMT of the design 10. as described in design 9, wherein：
The substrate includes silicon (Si), sapphire, silicon carbide (SiC) or bulk single crystalline gallium nitride (GaN)；
The channel carrier transport layer includes GaN layer；And
The carrier accommodating layer includes AlGaN layer.
Conceive 11. HEMT as described in design 10, further includes：
Passivation layer above the AlGaN layer；And
The wherein described grid includes：
It extends through the passivation layer and enters the gate metal of the AlGaN layer；And
The gate insulating layer of the gate metal around the passivation layer is extended through and into the AlGaN layer.
Conceive 12. HEMT as described in design 10, further includes：
Passivation layer above the AlGaN layer；And
The wherein described grid includes：
It extends through the passivation layer and the AlGaN layer and enters the gate metal of the GaN layer；And
The circular gate metal for extending through the passivation layer and the AlGaN layer and entering the GaN layer Gate insulating layer.
Conceive a kind of 13. methods making high electron mobility field-effect transistor (HEMT), the method includes：
Mask layer is formed on carrier accommodating layer, the mask layer is configured as and from grid to the drift region of drain electrode Alignment, and be configured as from the grid to the variation with transverse direction on the direction of the drain electrode；And
Ion is injected to pass through the mask layer and enter the carrier accommodating layer.
Conceive 14. method as described in design 13, further includes：
Channel carrier transport layer is formed on substrate；And
Carrier accommodating layer is formed in the channel carrier transport layer.
Method of the design 15. as described in design 13, wherein forming the step of the mask layer on the carrier accommodating layer Suddenly include：
The direction thickness from the grid to the drain electrode is formed on the mask layer by following steps gradually to increase Big conical section：
Using grayscale lithography；And
The mask layer is etched to form the conical section.
Method of the design 16. as described in design 13, wherein including the step of forming mask layer on carrier accommodating layer：
The carrier accommodating layer is applied using photoresist；And
Being formed in the photoresist has various sizes of opening, wherein the size of the opening is along from the grid to described The direction of drain electrode is gradually reduced.
Method of the design 17. as described in design 13, wherein the step of injection ion includes：
Damage the lattice of the carrier accommodating layer；
Wherein, lattice damage edge in the drift region gradually subtracts from the grid to the direction of the drain electrode It is few.
Method of the design 18. as described in design 17, wherein
The substrate includes silicon (Si), sapphire, silicon carbide (SiC) or bulk single crystalline gallium nitride (GaN)；
The channel carrier transport layer includes GaN layer；And
The carrier accommodating layer includes AlGaN layer.
Conceive 19. method as described in design 18, further includes：
Passivation layer is formed above the AlGaN layer；And
Form grid comprising following steps：
Form the groove for extending through the passivation layer and entering the AlGaN layer；
Gate insulating layer is deposited in the trench；And
Gate metal is formed on the gate insulating layer.
Method of the design 20. as described in design 19 extends through the passivation layer and enters the AlGaN wherein being formed Layer groove the step of further include：
Form the groove for extending into the GaN layer.
Method of the design 21. as described in design 19, wherein the lattice damage in the drift region edge from the grid The direction of pole insulating layer to the drain electrode is gradually less.
Method of the design 22. as described in design 17, wherein the step of damaging the lattice of the carrier accommodating layer includes：
Two-dimensional electron gas (2DEG), the 2DEG are formed in the drift region between the grid and the drain electrode With from the grid to the direction of the drain electrode, gradually increased non-homogeneous transverse direction 2DEG is distributed on edge in the drift region.

Claims (21)

1. a kind of high electron mobility field-effect transistor HEMT, including：
Lattice damage in the drift region of carrier accommodating layer between the gate and the drain, wherein the lattice damage is along institute Dimension linear of the drift region from close to the drain electrode to close to the grid is stated to increase；And
Two-dimensional electron gas 2DEG, the two-dimensional electron gas 2DEG in drift region between the gate and the drain is with described Along from the grid to the direction of the drain electrode and gradually increased non-homogeneous lateral two-dimensional electron gas 2DEG points in drift region Cloth；
Wherein by being obtained along the flat of the drift region along the linearly increasing lattice damage of the drift region Electric field.
2. high electron mobility field-effect transistor HEMT as described in claim 1,
It is gradually linearly reduced from the grid to the direction of the drain electrode on wherein described lattice damage edge in the drift region.
3. high electron mobility field-effect transistor HEMT as described in claim 1, further includes：
Substrate；
Channel carrier transport layer over the substrate；And
Carrier accommodating layer in the channel carrier transport layer.
4. high electron mobility field-effect transistor HEMT as claimed in claim 3, wherein：
The substrate includes silicon Si, sapphire, silicon carbide SiC or bulk single crystalline gallium nitride GaN；
The channel carrier transport layer includes GaN layer；And
The carrier accommodating layer includes AlGaN layer.
5. high electron mobility field-effect transistor HEMT as claimed in claim 4, further includes：
Passivation layer in the AlGaN layer；And
The wherein described grid includes：
It extends through the passivation layer and enters the gate metal of the AlGaN layer；And
The gate insulating layer of the gate metal around the passivation layer is extended through and into the AlGaN layer.
6. high electron mobility field-effect transistor HEMT as claimed in claim 4, further includes：
Passivation layer above the AlGaN layer；And
The wherein described grid includes：
It extends through the passivation layer and the AlGaN layer and enters the gate metal of the GaN layer；And
The grid of the gate metal around the passivation layer and the AlGaN layer is extended through and into the GaN layer Insulating layer.
7. a kind of field-effect transistor FET, including：
Lattice damage in the drift region of carrier accommodating layer between the gate and the drain；
The wherein described lattice damage is in the drift region along the line from the close drain electrode to the direction of the close grid Property increase；And
Wherein by being obtained along the flat of the drift region along the linearly increasing lattice damage of the drift region Electric field.
8. field-effect transistor FET as claimed in claim 7, further includes：
The two-dimensional electron gas 2DEG in the drift region between the grid and the drain electrode, the two-dimensional electron gas 2DEG has in the drift region along gradually increased non-homogeneous laterally two-dimentional from the grid to the direction of the drain electrode Electron gas 2DEG distributions.
9. field-effect transistor FET as claimed in claim 7, further includes：
Substrate；
Channel carrier transport layer over the substrate；And
Carrier accommodating layer in the channel carrier transport layer.
10. field-effect transistor FET as claimed in claim 9, wherein：
The substrate includes silicon Si, sapphire, silicon carbide SiC or bulk single crystalline gallium nitride GaN；
The channel carrier transport layer includes GaN layer；And
The carrier accommodating layer includes AlGaN layer.
11. field-effect transistor FET as claimed in claim 10, further includes：
Passivation layer above the AlGaN layer；And
The wherein described grid includes：
It extends through the passivation layer and enters the gate metal of the AlGaN layer；And
The gate insulating layer of the gate metal around the passivation layer is extended through and into the AlGaN layer.
12. field-effect transistor FET as claimed in claim 10, further includes：
Passivation layer above the AlGaN layer；And
The wherein described grid includes：
It extends through the passivation layer and the AlGaN layer and enters the gate metal of the GaN layer；And
The grid of the gate metal around the passivation layer and the AlGaN layer is extended through and into the GaN layer Insulating layer.
13. a kind of method making high electron mobility field-effect transistor HEMT, the method includes：
Mask layer is formed on carrier accommodating layer, the mask layer is configured as and from grid to the drift region pair of drain electrode Together, it and is configured as from the grid to having gradual increased cross directional variations on the direction of the drain electrode；
Ion is injected to pass through the mask layer and enter the carrier accommodating layer；
Damage the lattice of the carrier accommodating layer；And
Wherein, lattice damage edge in the drift region gradually linearly subtracts from the grid to the direction of the drain electrode It is few.
14. method as claimed in claim 13, further includes：
Channel carrier transport layer is formed on substrate；And
The carrier accommodating layer is formed in the channel carrier transport layer.
15. method as claimed in claim 13, wherein being wrapped the step of forming the mask layer on the carrier accommodating layer It includes：
It is formed in from the grid to thickness on the direction of the drain electrode on the mask layer by following steps and is gradually increased Conical section：
Using grayscale lithography；And
The mask layer is etched to form the conical section.
16. method as claimed in claim 13, wherein including the step of forming mask layer on carrier accommodating layer：
The carrier accommodating layer is applied using photoresist；And
Being formed in the photoresist has various sizes of opening, wherein the size of the opening is along from the grid to the drain electrode Direction be gradually reduced.
17. method as claimed in claim 13, wherein
Substrate includes silicon Si, sapphire, silicon carbide SiC or bulk single crystalline gallium nitride GaN；
Channel carrier transport layer on the substrate includes GaN layer；And
The carrier accommodating layer includes the AlGaN layer in the channel carrier transport layer.
18. method as claimed in claim 17, further includes：
Passivation layer is formed above the AlGaN layer；And
Form grid comprising following steps：
Form the groove for extending through the passivation layer and entering the AlGaN layer；
Gate insulating layer is deposited in the trench；And
Gate metal is formed on the gate insulating layer.
19. method as claimed in claim 18 extends through the passivation layer and enters the AlGaN layer wherein being formed The step of groove further includes：
Form the groove for extending into the GaN layer.
20. method as claimed in claim 18, wherein lattice damage edge in the drift region is exhausted from the grid The direction of edge layer to the drain electrode is gradually less.
21. method as claimed in claim 13, wherein the step of damaging the lattice of the carrier accommodating layer includes：
Two-dimensional electron gas 2DEG, the two-dimensional electron gas are formed in the drift region between the grid and the drain electrode 2DEG has in the drift region along gradually increased non-homogeneous laterally two-dimentional from the grid to the direction of the drain electrode Electron gas 2DEG distributions.
CN201380024745.5A 2012-05-23 2013-05-09 High electron mobility field-effect transistor and preparation method thereof Expired - Fee Related CN105103296B (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US13/478,402 US9000484B2 (en) 2012-05-23 2012-05-23 Non-uniform lateral profile of two-dimensional electron gas charge density in type III nitride HEMT devices using ion implantation through gray scale mask
US13/478,609 US9379195B2 (en) 2012-05-23 2012-05-23 HEMT GaN device with a non-uniform lateral two dimensional electron gas profile and method of manufacturing the same
US13/478,609 2012-05-23
US13/479,018 US8680536B2 (en) 2012-05-23 2012-05-23 Non-uniform two dimensional electron gas profile in III-Nitride HEMT devices
US13/479,018 2012-05-23
US13/478,402 2012-05-23
PCT/US2013/040441 WO2013176905A1 (en) 2012-05-23 2013-05-09 A high electron mobility field effect transistor and method of manufacturing the same

Publications (2)

Publication Number Publication Date
CN105103296A CN105103296A (en) 2015-11-25
CN105103296B true CN105103296B (en) 2018-08-28

Family

ID=49624250

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380024745.5A Expired - Fee Related CN105103296B (en) 2012-05-23 2013-05-09 High electron mobility field-effect transistor and preparation method thereof

Country Status (3)

Country Link
EP (1) EP2852979A4 (en)
CN (1) CN105103296B (en)
WO (1) WO2013176905A1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010016993A1 (en) * 2010-05-18 2011-11-24 United Monolithic Semiconductors Gmbh Semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5093991B2 (en) * 2005-03-31 2012-12-12 住友電工デバイス・イノベーション株式会社 Semiconductor device
JP5555985B2 (en) * 2008-06-23 2014-07-23 サンケン電気株式会社 Semiconductor device
US7985986B2 (en) * 2008-07-31 2011-07-26 Cree, Inc. Normally-off semiconductor devices
US7759186B2 (en) * 2008-09-03 2010-07-20 The United States Of America As Represented By The Secretary Of The Navy Method for fabricating junction termination extension with formation of photosensitive dopant mask to control doping profile and lateral width for high-voltage electronic devices
US20100219452A1 (en) * 2009-02-27 2010-09-02 Brierley Steven K GaN HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) STRUCTURES
US20120098599A1 (en) * 2009-06-30 2012-04-26 Univeristy Of Florida Research Foundation Inc. Enhancement mode hemt for digital and analog applications
US8878246B2 (en) * 2010-06-14 2014-11-04 Samsung Electronics Co., Ltd. High electron mobility transistors and methods of fabricating the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010016993A1 (en) * 2010-05-18 2011-11-24 United Monolithic Semiconductors Gmbh Semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"Normally-off AlGaN/GaN Low-Density-Drain HEMTs (LDD-HEMT) with Enhanced Breakdown Voltage and Suppressed Current Collapse";Di Song;《Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs》;20070530;第257页，摘要，第II部分，图1 *

Also Published As

Publication number Publication date
EP2852979A4 (en) 2015-11-18
CN105103296A (en) 2015-11-25
EP2852979A1 (en) 2015-04-01
WO2013176905A1 (en) 2013-11-28
WO2013176905A4 (en) 2014-01-23

Similar Documents

Publication Publication Date Title
JP7473638B2 (en) STEP FIELD PLATE ADJACENT TO A CONDUCTING CHANNEL AND RELATED FABRICATION METHODS - Patent application
US9941399B2 (en) Enhancement mode III-N HEMTs
US20220209000A1 (en) High-threshold-voltage normally-off high-electron-mobility transistor and preparation method therefor
US8933487B2 (en) Controlling lateral two-dimensional electron hole gas HEMT in type III nitride devices using ion implantation through gray scale mask
WO2007136401A2 (en) N-polar aluminum gallium nitride/gallium nitride enhancement-mode field effect transistor
CN108447907A (en) Transistor and preparation method thereof
US11594625B2 (en) III-N transistor structures with stepped cap layers
KR20190112526A (en) Heterostructure Field Effect Transistor and production method thereof
CN104412388B (en) HEMT device and manufacturing method thereof
CN104350601B (en) The method of HEMT devices and manufacture HEMT devices
US20200395447A1 (en) Semiconductor Device and Method for Fabricating a Wafer
CN112018176A (en) Semiconductor device and manufacturing method thereof
CN105103296B (en) High electron mobility field-effect transistor and preparation method thereof
US20220406927A1 (en) Two-dimensional electron gas charge density control
US11869963B2 (en) Semiconductor device and method of fabricating a semiconductor device
CN110085662A (en) A kind of high voltage bearing HEMT device and preparation method
US10804387B1 (en) Vertical superlattice transistors
CN107369708B (en) Gallium nitride high electron mobility transistor and preparation and use methods thereof
JP7382558B2 (en) Trench type MOSFET
US20240079487A1 (en) Charge balanced power transistors
US11417757B2 (en) Ohmic contacts in semiconductor devices
EP2747144A1 (en) Gate leakage of GaN HEMTs and GaN diodes
JP2018037567A (en) Method of manufacturing semiconductor device, and semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20180828

CF01 Termination of patent right due to non-payment of annual fee