JP7382558B2 - Trench type MOSFET - Google Patents

Description

The present invention relates to a trench MOSFET.

Conventionally, a trench-type Ga ₂ O ₃ -based MOSFET in which a gate electrode is buried in a semiconductor layer is known (for example, see Patent Document 1). Trench type MOSFETs have high breakdown voltage characteristics due to their trench gate structure.

Unexamined Japanese Patent Publication No. 2016-15503

In a trench MOSFET, the breakdown voltage characteristics vary depending on the shape and size of each member constituting the trench structure, but a specific structure for obtaining excellent breakdown voltage characteristics is not known.

An object of the present invention is to provide a trench MOSFET having a trench gate structure that can achieve high breakdown voltage and low loss at a high level.

In order to achieve the above object, one aspect of the present invention provides the following trench MOSFETs [1] to [7].

[1] An n-type semiconductor layer made of a Ga ₂ O ₃ single crystal and having a plurality of trenches opened on one surface; a gate insulating film provided in contact with the inner surface of each of the plurality of trenches; a gate electrode buried in each of the plurality of trenches while covered with a gate insulating film; a source electrode connected to a mesa-shaped portion between adjacent trenches of the n-type semiconductor layer; a drain electrode connected directly or indirectly to the opposite side of the source electrode of the semiconductor layer, and the radius of curvature at the apex of the curve of the bottom edge of the trench in the cross section in the width direction of the trench is A trench type MOSFET whose value divided by the width is within the range of 0.0125 or more and 0.25 or less.
[2] When the channel concentration, which is the donor concentration in the region between the two adjacent gate electrodes in the n-type semiconductor layer, is 1×10 ¹⁵ cm ^-3 or less, the mesa width, which is the width of the mesa-shaped portion, is is 0.5 μm or less, and the channel concentration is greater than 1×10 ¹⁵ cm- ³ and less than 1×10 ¹⁶ cm- ³ , the mesa width is 0.4 μm or less, and the channel concentration is 1× When the mesa width is greater than 10 ¹⁶ cm- ³ and less than or equal to 2×10 ¹⁶ cm- ³ , the mesa width is less than or equal to 0.3 μm, and the channel concentration is greater than 2×10 ¹⁶ cm- ³ and less than or equal to 6×10 ¹⁶ cm- ³ . The trench MOSFET according to [1] above, wherein the mesa width is 0.2 μm or less.
[3] The trench MOSFET according to [1] or [2] above, wherein the gate electrode has a work function of 5.0 eV or more.
[4] The trench MOSFET according to any one of [1] to [3] above, wherein the gate length of the gate electrode is 1 μm or more.
[5] The n-type semiconductor layer has a contact layer near the interface with the source electrode for making an ohmic connection between the n-type semiconductor layer and the source electrode, and the distance between the gate electrode and the contact layer is The trench MOSFET according to any one of [1] to [4] above, wherein the trench type MOSFET is 0.1 μm or more.
[6] The thickness of the portion of the gate insulating film that is in contact with the center of the bottom of the trench is within the range of 0.2 μm or more and 0.5 μm or less, or within the range of 0.1 μm or more and less than 0.2 μm. , the trench MOSFET according to any one of [1] to [5] above.
[7] Any one of [1] to [6] above, wherein the n-type semiconductor layer has a mesa shape with a depression provided at the upper edge, and the gate electrode is exposed on the inner surface of the depression. The trench type MOSFET described in .

According to the present invention, it is possible to provide a trench MOSFET having a trench gate structure that can achieve high breakdown voltage and low loss at a high level.

FIG. 1 is a vertical cross-sectional view of a trench MOSFET according to a first embodiment. FIG. 2 is a partially enlarged view of FIG. 1 showing the vicinity of the bottom of the trench of the trench MOSFET. FIG. 3 is a partially enlarged vertical cross-sectional view of a modification of the trench MOSFET according to the first embodiment. 4(a) to (c) are graphs showing the relationship between the voltage applied between the source electrode and the drain electrode and the off-leakage current when the channel concentration of the channel layer and the mesa width are changed. be. 5(a) to (c) are graphs showing the relationship between the voltage applied between the source electrode and the drain electrode and the off-leakage current when the channel concentration of the channel layer and the mesa width are changed. be. FIG. 6 is a graph showing the relationship between the voltage applied between the source electrode and the drain electrode and the off-leakage current when the work function of the gate electrode is changed. FIG. 7 is a graph showing the relationship between the voltage applied between the source electrode and the drain electrode and the off-leakage current when the gate length of the gate electrode is changed. FIG. 8 is a graph showing the relationship between the voltage applied between the source electrode and the drain electrode and the off-leakage current when the distance between the gate electrode and the contact layer is changed. FIG. 9 is a graph showing the relationship between the thickness of the gate insulating film and the maximum electric field strength in the n-type semiconductor layer. FIGS. 10A and 10B are graphs showing the relationship between the mesa depth and the maximum electric field strength in the n-type semiconductor layer. FIGS. 11A and 11B are graphs showing the relationship between the mesa depth and the maximum electric field strength in the n-type semiconductor layer.

[Embodiment]
(Configuration of trench type MOSFET)
FIG. 1 is a vertical cross-sectional view of a trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 1 according to the first embodiment. Trench MOSFET 1 is a vertical field effect transistor having a trench gate structure. Note that the trench MOSFET 1 of this embodiment also includes a configuration in which the gate insulating film 13, which will be described later, is made of a material other than oxide.

The trench type MOSFET 1 is an n-type semiconductor having an n-type semiconductor substrate 10 and a plurality of trenches 16 that are laminated on the n-type semiconductor substrate 10 and open on a surface 18 opposite to the n-type semiconductor substrate 10. layer 11, a gate insulating film 13 provided in contact with the inner surface of each of the plurality of trenches 16, a gate electrode 12 buried in each of the plurality of trenches 16 while covered with the gate insulating film 13, a source electrode 14 connected to a mesa-shaped portion 17 between adjacent trenches 16 of the type semiconductor layer 11; and a drain electrode 15 formed on the surface of the n-type semiconductor substrate 10 opposite to the n-type semiconductor layer 11. , is provided.

The trench MOSFET 1 may be either a normally-off type or a normally-on type, but when used as a power device, it is usually manufactured as a normally-off type from the viewpoint of safety. This is to prevent conduction between the source electrode 14 and the drain electrode 15 when the gate becomes uncontrollable due to disconnection of the gate circuit or the like.

In the normally-off trench MOSFET 1, by applying a voltage equal to or higher than the threshold voltage between the gate electrode 12 and the source electrode 14, a channel is formed in the mesa-shaped portion 17, and a channel is formed from the drain electrode 15 to the source electrode 14. A current flows through.

The n-type semiconductor substrate 10 is made of an n-type Ga ₂ O ₃ single crystal containing group IV elements such as Si and Sn as donors. The donor concentration of the n-type semiconductor substrate 10 is, for example, 1.0×10 ¹⁸ cm ⁻³ or more and 1.0×10 ²⁰ cm ⁻³ or less. The thickness of the n-type semiconductor substrate 10 is, for example, 10 μm or more and 600 μm or less.

Here, the Ga ₂ O ₃ single crystal refers to a Ga ₂ O ₃ single crystal or a Ga ₂ O ₃ single crystal to which elements such as Al and In are added. For example, Ga ₂ O ₃ single crystal doped with Al and In (Ga _x Al _y In _(1-x-y) ) ₂ O ₃ (0<x≦1, 0≦y<1, 0<x+y ≦1) It may be a single crystal. When Al is added, the band gap is widened, and when In is added, the band gap is narrowed. Note that the Ga ₂ O ₃ single crystal described above has, for example, a β-type crystal structure.

Although the plane orientation of the n-type semiconductor substrate 10 is not particularly limited, it is preferably the (001) plane, which increases the growth rate of the Ga ₂ O ₃ -based single crystal forming the n-type semiconductor layer 11 . Alternatively, it is preferable that the surface is a (011) plane that allows growth of a Ga ₂ O ₃ single crystal film with a flat surface.

The n-type semiconductor layer 11 is made of an n-type Ga ₂ O ₃ single crystal containing group IV elements such as Si and Sn as donors.

The n-type semiconductor layer 11 includes a channel layer 11b in which a gate electrode 12 is embedded and a channel is formed when a gate voltage is applied, a breakdown voltage layer 11a for maintaining a breakdown voltage under the channel layer 11b, and a source electrode. The contact layer 11c is formed near the interface with the n-type semiconductor layer 11 by ion implantation or epitaxial growth, and is used to ohmically connect the source electrode 14 to the n-type semiconductor layer 11.

Here, a region of the n-type semiconductor layer 11 below the height of the bottom of the trench 16 (on the n-type semiconductor substrate 10 side) is a breakdown voltage layer 11a, and its thickness is defined as _Tp . Further, in the n-type semiconductor layer 11, a region above the height of the bottom of the trench 16 (on the source electrode 14 side) is a channel layer 11b, and a contact layer 11c is provided near the upper end of the channel layer 11b.

The thickness T _p of the breakdown voltage layer 11a is one of the parameters that determines the breakdown voltage characteristics of the trench MOSFET 1, and it is assumed that the breakdown electric field strength of Ga ₂ O ₃ is constant at 8 MV/cm, which is the estimated value from the band gap. For example, in order to obtain performance with a withstand voltage of 600 V used in home appliances and automobiles, it is necessary to have a thickness of at least 1 to 2 μm, and in order to obtain a withstand voltage of 1200 V used in industrial equipment, it is necessary to have a thickness of approximately 3 μm or more. In order to obtain a withstand voltage of 3,300V used in transportation equipment, it is necessary to have a voltage of approximately 8 to 9 μm or more, and to obtain a withstand voltage of 6,600 V for large power applications such as power transmission, it is approximately 16 to 17 μm or more, and a withstand voltage of 1. In order to obtain 20,000 V, it is necessary to have a thickness of about 30 μm or more, and to obtain a withstand voltage of 100,000 V in a high-voltage circuit breaker, it is necessary to have a thickness of about 250 μm or more.

Note that the maximum dielectric breakdown electric field strength of Ga ₂ O ₃ has not been measured at this time, and if it were about 4 MV/cm, which is the maximum value among those actually measured, the above film thickness would need to be twice as large. Become. For example, in order to obtain a breakdown voltage of 100,000 V, a thickness of about 500 μm is required. In order to obtain a withstand voltage lower than 600V for small home appliances, the thickness T _p may be thinner than 1 μm, but from the viewpoint of manufacturing stability, it is preferably at least about 1 μm. Therefore, the thickness T _p is preferably 1 μm or more and 500 μm or less.

The donor concentration of the breakdown voltage layer 11a is one of the parameters that determines the breakdown voltage characteristics of the trench MOSFET 1. Assuming that the dielectric breakdown field strength of Ga ₂ O ₃ is constant at 8 MV/cm, the donor concentration of the breakdown voltage layer 11a is 1. .8 x 10 ¹⁷ cm ^-3 or less, to obtain a withstand voltage of 1200V, it should be about 9 x 10 ¹⁶ cm ^-3 or less, to obtain a withstand voltage of 3300V, it should be about 3 x 10 ¹⁶ cm ^-3 or less, a withstand voltage of 10,000 V. In order to achieve this, it is preferable to have a particle diameter of about 1×10 ¹⁶ cm ⁻³ or less. In order to obtain a breakdown voltage lower than 600V or higher than 10,000V, appropriate concentrations may be set. Further, when the maximum dielectric breakdown field strength of Ga ₂ O ₃ is about 4 MV/cm, each of the above concentrations becomes about one-fifth or less.

The channel concentration of the channel layer 11b (the donor concentration in the region between two adjacent gate electrodes 12) and the mesa width _Wm , which is the width of the mesa-shaped portion 17, are determined depending on whether the trench MOSFET 1 is a normally-off type or a normally-on type. When forming a normally-off type, the channel concentration is low and the mesa width W _m is narrow; when forming a normally-on type, the channel concentration is high and the mesa width W _m is wide. do it.

When the trench type MOSFET 1 is a normally-off type, in order to suppress off-leakage current, for example, when the channel concentration of the channel layer 11b is 1×10 ¹⁵ cm ^-3 or less, the mesa width W _m is set to 0.5 μm or less. , when the channel concentration of the channel layer 11b is greater than 1×10 ¹⁵ cm- ³ and less than 1×10 ¹⁶ cm- ³ , the mesa width W _m is 0.4 μm or less, and the channel concentration of the channel layer 11b is 1×10 When the mesa width W m is greater than ¹⁶ cm- ³ and less than or equal to 2×10 ¹⁶ cm- ³ , the mesa width W _m is less than or equal to 0.3 μm, and when the channel concentration of the channel layer 11b is greater than 2×10 ¹⁶ cm- ³ and less than 6×10 ¹⁶ cm. - ³ or less, the mesa width W _m is preferably 0.2 μm or less.

Furthermore, the smaller the width W _m of the mesa-shaped region, the higher the channel concentration can be, and therefore the on-resistance of the channel layer 11b can be reduced. On the other hand, there is a problem in that the narrower the width W _m is, the more difficult it is to manufacture, resulting in a lower manufacturing yield.

For this reason, for example, when forming the trench 16 by patterning using a general stepper, the width W _m of the mesa-shaped region is preferably 0.5 μm or more and 2 μm or less, and the EB ( When the trench 16 is formed by patterning using (electron beam) drawing, the width W _m of the mesa-shaped region is preferably 0.1 μm or more and 2 μm or less.

The width W _t of the trench 16 also depends on the resolution of the exposure apparatus, so it is preferably set within the same numerical range as the width W _m of the mesa-shaped region, depending on the type of exposure apparatus used.

The thickness of the contact layer 11c is, for example, 10 nm or more and 5 μm or less. The donor concentration of the contact layer 11c is higher than the channel concentration of the channel layer 11b, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less.

The gate electrode 12 is made of a conductor, that is, a metal such as Ni or a semiconductor containing a high concentration of donors. In order to suppress off-leak current, the work function of the gate electrode 12 is preferably 5.0 eV or more, and the gate length (length in the thickness direction of the n-type semiconductor layer 11) L _g of the gate electrode 12 is 1 μm or more, for example. The distance _Lc between the gate electrode 12 and the contact layer 11c is preferably 0.1 μm or more.

The gate insulating film 13 covers, for example, the side and bottom surfaces of the gate electrode 12 , covers a portion 13 a that insulates the gate electrode 12 from the n-type semiconductor layer 11 , and the upper surface of the gate electrode 12 , and insulates the gate electrode 12 from the source electrode 14 . It has an insulating portion 13b. The portion 13a and the portion 13b of the gate insulating film 13 are made of, for example, HfO ₂ and SiO ₂ , respectively. The portion 13a of the gate insulating film 13 is a single film, and is formed integrally from one material in one process, for example. The thickness of the portion 13b of the gate insulating film 13 is, for example, 50 nm or more and 2000 nm or less.

The n-type semiconductor layer 11 is made of, for example, an epitaxially grown film formed by HVPE method or the like. When forming the n- _type semiconductor layer _{11 by the HVPE method, chloride gas is used as the Ga 2 O 3} single crystal raw material or dopant raw material. Contains Cl derived from dopant raw materials.

When using the HVPE method, since the crystal growth rate is fast, it is possible to shorten the film formation time and reduce costs. This point is particularly advantageous when forming the n-type semiconductor layer 11 thickly. Further, when using the HVPE method, the n-type semiconductor layer 11 with good crystal quality can be formed, so that the manufacturing yield can be improved. Furthermore, since the n-type semiconductor layer 11 with high purity can be formed, the donor concentration can be controlled with high precision.

Note that the contact layer 11c may be formed by _implanting a donor into the upper part _of the channel layer 11b formed by epitaxial growth using an ion implantation method; By forming by crystal growth of a single crystal, manufacturing costs can be suppressed.

Source electrode 14 is formed on top surface 18 of n-type semiconductor layer 11 and connected to mesa-shaped portion 17 . As shown in FIG. 1, the drain electrode 15 is connected to the surface of the n-type semiconductor substrate 10 opposite to the n-type semiconductor layer 11, but when the trench MOSFET 1 does not include the n-type semiconductor substrate 10, , may be connected to the surface of the n-type semiconductor layer 11 opposite to the source electrode 14. That is, the drain electrode 15 is directly or indirectly connected to the side of the n-type semiconductor layer 11 opposite to the source electrode 14.

The source electrode 14 and the drain electrode 15 are ohmically connected to the contact layer 11c of the n-type semiconductor layer 11 and the n-type semiconductor substrate 10, respectively. The source electrode 14 and the drain electrode 15 have, for example, a Ti/Au stacked structure.

FIG. 2 is a partially enlarged view of FIG. 1 showing the vicinity of the bottom of the trench 16 of the trench MOSFET 1. As shown in FIG. In FIG. 2, an example of the electric field distribution in the n-type semiconductor layer 11 is schematically shown by equipotential lines (dotted lines). Further, the region indicated by "E _max " in the electric field distribution in FIG. 2 is a region where the electric field strength takes the maximum value E _max .

The magnitude of the maximum electric field strength E _max in the n-type semiconductor layer 11 is determined from the edge of the bottom of the trench 16 (the edge in the width direction) in the cross section of the trench 16 in the width direction (width W _t direction) shown in FIG. ) 160 depends on the radius of curvature R ₁ at the apex of the curve.

The circle _C1 shown in FIG. 2 is a circle that includes an arc when the vicinity of the apex of the curve of the bottom edge 160 of the trench 16 is approximated as a circular arc in the cross section in the width direction of the trench 16, and the circle _C1 shown in FIG. The radius corresponds to the radius of curvature _R1 . Further, a circle _C2 shown in FIG. 2 is a circle that includes an arc when the vicinity of the apex of the curve of the bottom edge 120 of the gate electrode 12 is approximated as a circular arc in the cross section of the trench 16 in the width direction. Let _R2 be the radius of curvature at the apex of the curve of the bottom edge 120 of the gate electrode 12, which corresponds to the radius of _C2 .

In order to keep the maximum electric field strength _Emax in the n-type semiconductor layer 11 low, this radius of curvature _R1 is normalized by the width _Wt of the trench 16, that is, divided by the width _Wt of the trench 16. The value is preferably in the range of 0.0125 or more and 0.25 or less.

Here, the radius of curvature R ₁ is normalized by the width W _t of the trench 16 because even if the radius of curvature R ₁ is the same, the maximum electric field strength E _max may change depending on the width W _t of the trench 16. be. For example, when the width W _t of the trench 16 with respect to the radius of curvature R ₁ is small, the electric fields near the edges 160 on both sides of the bottom of the trench 16 are combined, and the maximum electric field strength E _max becomes large.

The thickness _T1 of the portion of the gate insulating film 13 (portion 13a) that is in contact with the center of the bottom of the trench 16 is set to, for example, 0.05 mm in order to keep the electric field strength in the n-type semiconductor layer 11 (mainly the breakdown voltage layer 11a) low. It is preferably within the range of 2 μm or more and 0.5 μm or less. Further, from the viewpoint of ease of forming the gate insulating film 13, the thickness _T1 is preferably in a range of 0.1 μm or more and less than 0.2 μm.

The thickness _T2 of the portion of the gate insulating film 13 (portion 13a) in contact with the side of the trench 16 is preferably, for example, 0.02 μm or more in order to suppress gate leakage current.

The gate insulating film 13 is formed by, for example, atomic layer deposition (ALD). When the portion 13a of the gate insulating film 13 is formed by a general process using ALD or the like, its thickness becomes uniform. For example, when the thickness T ₃ of the gate insulating film 13 (portion 13a) at the portion in contact with the apex of the curved portion of the edge 160 at the bottom of the trench 16 is made to be different from the thickness T ₁ , for example, an anisotropic method such as sputtering may be used. It is possible to use a two-step film formation that combines a strong film formation method and ALD, or an etching process after film formation.

FIG. 3 is a partially enlarged vertical cross-sectional view of a modification of the trench MOSFET 1 according to the first embodiment. In the modification shown in FIG. 3, the n-type semiconductor layer 11 has a recess 110 at its upper edge, and the entire recess has a mesa shape. In this mesa shape, as shown in FIG. 3, the upper edge of the n-type semiconductor layer 11 is removed by the depression 110 along with the gate electrode 12 included therein and a part of the gate insulating film 13 covering it. The gate electrode 12 is exposed on the inner surface of the recess 110. Although not shown, an insulating film is usually formed on the inner surface of the recess 110 where the gate electrode 12 is exposed to protect the surface.

When the n-type semiconductor layer 11 has a mesa shape, an electric field is concentrated near the inner edge 111 of the bottom of the recess 110, and the magnitude of this electric field is equal to the depth of the mesa from the bottom of the trench 16 of the recess 110. Depends on the depth D _m . Therefore, by setting the mesa depth _Dm to an appropriate size depending on the magnitude of the voltage applied between the source electrode 14 and the drain electrode 15, the n-type semiconductor layer 11 (mainly the voltage resistance layer The electric field strength in 11a) can be kept low.

(Effects of embodiment)
According to the trench MOSFET 1 according to the embodiment described above, since excellent breakdown voltage characteristics can be obtained due to the shape of the trench 16, a desired breakdown voltage can be obtained without increasing the resistance of the n-type semiconductor layer 11. Therefore, it is possible to achieve both high breakdown voltage and low loss at a high level.

Regarding the trench MOSFET 1 according to the above embodiment, the radius of curvature R ₁ at the apex of the curve of the bottom edge 160 of the trench 16 in the cross section in the width direction of the trench 16 and the maximum value E _max of the electric field strength in the n-type semiconductor layer 11 We investigated the relationship between

In this simulation, the material (mother crystal) of the n-type semiconductor layer 11 is Ga ₂ O ₃ single crystal, the material of the gate insulating film 13 is HfO ₂ , and the thickness of the portion of the gate insulating film 13 in contact with the bottom of the trench 16 is T. ₁ is 0.05 μm, the width W _m of the mesa-shaped portion 17 is 0.4 μm, and the thickness T _p of the breakdown voltage layer 11a (from the bottom of the trench 16 in the n-type semiconductor layer 11 to the interface with the n-type semiconductor substrate 10 The donor concentration of the breakdown voltage layer 11a is set to 8×10 ¹⁵ cm ⁻³ and the donor concentration of the channel layer 11b is set to 1×10 ¹⁶ cm ⁻³ , and the source electrode 14 and gate electrode are grounded (0 V is applied). ), and a voltage of 10 kV was applied to the drain electrode 15.

The following Table 1 shows the radius of curvature R 1 at the apex of the curve of the bottom edge 160 of the trench 16 and the radius of curvature R ₂ at the apex of the curve of the bottom edge 120 of the _gate electrode 12 in the cross section of the trench 16 in the width direction. The maximum value E max (MV/cm) of the electric field strength in the n-type semiconductor layer 11 is shown when changing the value of E _max (MV/cm).

The following Table 2 is a table in which the radius of curvature R ₁ and the radius of curvature R ₂ in Table 1 are replaced with the radius of curvature R _n1 and the radius of curvature R _n2 , respectively, which are normalized by the width W _t of the trench 16. Note that the thickness T ₁ of the gate insulating film 13 is 0.125 due to the standardization based on the width W _t .

According to Table 2, when the radius of curvature R _n1 , which is the radius of curvature R ₁ normalized by the width W _t of the trench 16, is within the range of 0.0125 or more and 0.25 or less, the The maximum value E _max of electric field strength is suppressed to 8 MV/cm or less. As mentioned above, 8 MV/cm is the dielectric breakdown field strength of Ga ₂ O ₃ estimated from the size of the band gap.

From this result, in order to keep the maximum value E _max of the electric field in the n-type semiconductor layer 11 low, the radius of curvature R ₁ must be normalized by the width W _t of the trench 16, that is, the width of the trench 16. It can be said that it is preferable that the value divided by W _t is within the range of 0.0125 or more and 0.25 or less.

Note that, in general, charges in a conductor repel each other and therefore concentrate at the corners of the conductor, and the smaller the radius of curvature of the corner, the easier it is for the electric field to concentrate. For this reason, it has conventionally been thought that the larger the radius of curvature of the bottom edge of the gate electrode in a trench MOSFET, the more the electric field concentration can be suppressed. However, as a result of intensive research by the present inventors, as shown in Table 1, the radius of curvature _R2 , which is equal to the radius of curvature at the apex of the curve at the bottom edge of the gate electrode 12, does not have a large effect on the electric field strength. The radius of curvature _R1 at the apex of the curve of the edge 160 at the bottom of the trench 16, which was previously thought to have a weak relationship with the electric field strength, has a large effect on the electric field strength.This result is difficult to predict from the conventional idea. Obtained.

The following Table 3 shows the contact with the apex of the curved part of the edge 160 at the bottom of the trench 16 in the gate insulating film 13 (portion 13a) when the radius of curvature _R1 and the radius of curvature _R2 are varied within the ranges shown in Table 1. Indicates the value of the thickness T ₃ of the part.

The following Table 4 is a table in which the radius of curvature R ₁ and the radius of curvature R ₂ in Table 3 are replaced with the radius of curvature R _n1 and the radius of curvature R _n2 , respectively, which are normalized by the width W _t of the trench 16.

Note that in the simulation of this example, the material (mother crystal) of the n-type semiconductor layer 11 was set to Ga ₂ O ₃ single crystal, but similar results would be obtained even if other Ga ₂ O ₃ type single crystals were used. is obtained. Similarly, although the material of the gate insulating film 13 is set to HfO ₂ , similar results can be obtained even if it is set to SiO ₂ .

Regarding the trench MOSFET 1 according to the above embodiment, the channel concentration of the channel layer 11b (donor concentration in the region between two adjacent gate electrodes 12) and the mesa width W when the trench MOSFET 1 is a normally-off type. The effect of _m on the magnitude of off-leakage current (leakage current that occurs in the off-state) was investigated by simulation.

In this simulation, the material (mother crystal) of the n-type semiconductor layer 11 is Ga ₂ O ₃ single crystal, the material of the gate insulating film 13 is HfO ₂ , and the thickness of the portion of the gate insulating film 13 in contact with the bottom of the trench 16 is T. ₁ is set to 0.05 μm, the thickness T _p of the breakdown voltage layer 11a (the distance from the bottom of the trench 16 to the interface with the n-type semiconductor substrate 10 in the n-type semiconductor layer 11) is set to 50 μm, and the source electrode 14 and gate The electrode was grounded (0 V was applied), and a voltage of 10 kV was applied to the drain electrode 15.

4(a) to (c) and FIG. 5(a) to (c) show the relationship between the source electrode 14 and the drain electrode 15 when the channel concentration of the channel layer 11b and the mesa width W _m are changed. It is a graph showing the relationship between applied voltage and off-leakage current. In each of Figures 4(a) to (c) and 5(a) to (c), the dotted line indicates the magnitude of off-leakage current, 1×10 ^-4 A/ ^cm2 , which is an indicator of channel opening/closing. It is shown.

4(a), (b), and (c) show the case where the channel concentration of the channel layer 11b is 1×10 ¹⁵ cm- ³ , 5×10 ¹⁵ cm- ³ , and 1×10 ¹⁶ cm- ^3, respectively. Show characteristics. 5(a), (b), and (c) show the case where the channel concentration of the channel layer 11b is 2×10 ¹⁶ cm- ³ , 4×10 ¹⁶ cm- ³ , and 6×10 ¹⁶ cm- ^3, respectively. Show characteristics.

According to FIG. 4(a), when the channel concentration of the channel layer 11b is 1×10 ¹⁵ cm- ³ , if the mesa width W _m is 0.5 μm or less, there is a gap between the source electrode 14 and the drain electrode 15. Even when a voltage of 10 kV is applied to the channel, the magnitude of the off-leakage current does not reach 1×10 ⁻⁴ A/cm ² , and it can be said that the channel is closed.

According to FIG. 4(b), when the channel concentration of the channel layer 11b is 5×10 ¹⁵ cm- ³ , if the mesa width W _m is 0.4 μm or less, there is a gap between the source electrode 14 and the drain electrode 15. Even when a voltage of 10 kV is applied to the channel, the magnitude of the off-leakage current does not reach 1×10 ⁻⁴ A/cm ² , and it can be said that the channel is closed.

According to FIG. 4(c), when the channel concentration of the channel layer 11b is 1×10 ¹⁶ cm- ³ , if the mesa width W _m is 0.4 μm or less, there is a gap between the source electrode 14 and the drain electrode 15. Even when a voltage of 10 kV is applied to the channel, the magnitude of the off-leakage current does not reach 1×10 ⁻⁴ A/cm ² , and it can be said that the channel is closed.

According to FIG. 5(a), when the channel concentration of the channel layer 11b is 2×10 ¹⁶ cm- ³ , if the mesa width W _m is 0.3 μm or less, there is a gap between the source electrode 14 and the drain electrode 15. Even when a voltage of 10 kV is applied to the channel, the magnitude of the off-leakage current does not reach 1×10 ⁻⁴ A/cm ² , and it can be said that the channel is closed.

According to FIG. 5(b), when the channel concentration of the channel layer 11b is 4×10 ¹⁶ cm- ³ , if the mesa width W _m is 0.2 μm or less, there is a gap between the source electrode 14 and the drain electrode 15. Even when a voltage of 10 kV is applied to the channel, the magnitude of the off-leakage current does not reach 1×10 ⁻⁴ A/cm ² , and it can be said that the channel is closed.

According to FIG. 5(c), when the channel concentration of the channel layer 11b is 6×10 ¹⁶ cm- ³ , if the mesa width W _m is 0.2 μm or less, there is a gap between the source electrode 14 and the drain electrode 15. Even when a voltage of 10 kV is applied to the channel, the magnitude of the off-leakage current does not reach 1×10 ⁻⁴ A/cm ² , and it can be said that the channel is closed.

From these results, when the trench type MOSFET 1 is a normally-off type, in order to suppress off-leakage current, the mesa width W _m is set to 0 when the channel concentration of the channel layer 11b is 1×10 ¹⁵ cm- ³ or less. When the channel concentration of the channel layer 11b is greater than 1×10 ¹⁵ cm- ³ and less than 1×10 ¹⁶ cm- ³ , the mesa width W _m is 0.4 μm or less, and the channel concentration of the channel layer 11b is less than 0.5 μm. When the mesa width W m is greater than 1×10 ¹⁶ cm- ³ and less than 2×10 ¹⁶ cm- ³ , the mesa width W _m is 0.3 μm or less, and when the channel concentration of the channel layer 11b is greater than 2×10 ¹⁶ cm- ³ and 6× When it is 10 ¹⁶ cm ^-3 or less, it is preferable that the mesa width W _m is 0.2 μm or less.

Note that in the simulation of this example, the material (mother crystal) of the n-type semiconductor layer 11 was set to Ga ₂ O ₃ single crystal, but similar results would be obtained even if other Ga ₂ O ₃ type single crystals were used. is obtained. Similarly, although the material of the gate insulating film 13 is set to HfO ₂ , similar results can be obtained even if it is set to SiO ₂ .

Regarding the trench MOSFET 1 according to the above embodiment, the effect of the work function of the gate electrode 12 on the magnitude of off-leakage current was investigated by simulation when the trench MOSFET 1 is a normally-off type.

In this simulation, the material (mother crystal) of the n-type semiconductor layer 11 is Ga ₂ O ₃ single crystal, the material of the gate insulating film 13 is HfO ₂ , and the thickness of the portion of the gate insulating film 13 in contact with the bottom of the trench 16 is T. ₁ is 0.05 μm, the width W _m of the mesa-shaped portion 17 is 0.4 μm, and the thickness T _p of the breakdown voltage layer 11a (from the bottom of the trench 16 in the n-type semiconductor layer 11 to the interface with the n-type semiconductor substrate 10 The donor concentration of the breakdown voltage layer 11a is set to 1×10 ¹⁶ cm ⁻³ and the donor concentration of the channel layer 11b is set to 1×10 ¹⁶ cm ⁻³ , and the source electrode 14 and gate electrode are grounded (0 V). ), and a voltage of 10 kV was applied to the drain electrode 15.

FIG. 6 is a graph showing the relationship between the voltage applied between the source electrode 14 and the drain electrode 15 and the off-leakage current when the work function W of the gate electrode 12 is changed. In FIG. 6, the dotted line indicates the magnitude of off-leakage current, which is an indicator of channel opening/closing, of 1×10 ⁻⁴ A/cm ² .

According to FIG. 6, if the work function W of the gate electrode 12 is 5.0 eV or more, even if a voltage of 10 kV is applied between the source electrode 14 and the drain electrode 15, the magnitude of the off-leakage current is 1× It does not reach 10 ^-4 A/cm ² and it can be said that the channel is closed.

From this result, it can be said that when the trench MOSFET 1 is a normally-off type, the work function of the gate electrode 12 is preferably 5.0 eV or more in order to suppress off-leakage current.

Note that in the simulation of this example, the material (mother crystal) of the n-type semiconductor layer 11 was set to Ga ₂ O ₃ single crystal, but similar results would be obtained even if other Ga ₂ O ₃ type single crystals were used. is obtained. Similarly, although the material of the gate insulating film 13 is set to HfO ₂ , similar results can be obtained even if it is set to SiO ₂ .

Regarding the trench MOSFET 1 according to the embodiment described above, the influence of the gate length L _g of the gate electrode 12 on the magnitude of off-leakage current was investigated by simulation when the trench MOSFET 1 is a normally-off type.

In this simulation, the material (mother crystal) of the n-type semiconductor layer 11 is Ga ₂ O ₃ single crystal, the material of the gate insulating film 13 is HfO ₂ , and the thickness of the portion of the gate insulating film 13 in contact with the bottom of the trench 16 is T. ₁ is 0.05 μm, the width W _m of the mesa-shaped portion 17 is 0.4 μm, and the thickness T _p of the breakdown voltage layer 11a (from the bottom of the trench 16 in the n-type semiconductor layer 11 to the interface with the n-type semiconductor substrate 10 The donor concentration of the breakdown voltage layer 11a is set to 1.2×10 ¹⁶ cm ⁻³ and the donor concentration of the channel layer 11b is set to 1×10 ¹⁶ cm ⁻³ , and the source electrode 14 and gate electrode are grounded. (0 V was applied), and a voltage of 10 kV was applied to the drain electrode 15.

FIG. 7 is a graph showing the relationship between the voltage applied between the source electrode 14 and the drain electrode 15 and the off-leakage current when the gate length L _g of the gate electrode 12 is changed. In FIG. 7, 1×10 ⁻⁴ A/cm ² , which is the magnitude of off-leakage current that is an indicator of channel opening/closing, is indicated by a dotted line.

According to FIG. 7, if the gate length L _g of the gate electrode 12 is 1 μm or more, even if a voltage of 10 kV is applied between the source electrode 14 and the drain electrode 15, the magnitude of the off-leakage current is 1×10 ^-4 A/cm ² is not reached, and it can be said that the channel is closed.

From this result, it can be said that when the trench MOSFET 1 is a normally-off type, the gate length L _g of the gate electrode 12 is preferably 1 μm or more in order to suppress off-leakage current.

Note that in the simulation of this example, the material (mother crystal) of the n-type semiconductor layer 11 was set to Ga ₂ O ₃ single crystal, but similar results would be obtained even if other Ga ₂ O ₃ type single crystals were used. is obtained. Similarly, although the material of the gate insulating film 13 is set to HfO ₂ , similar results can be obtained even if it is set to SiO ₂ .

Regarding the trench MOSFET 1 according to the above embodiment, the effect of the distance L _c between the gate electrode 12 and the contact layer 11c on the magnitude of off-leakage current was investigated by simulation when the trench MOSFET 1 is a normally-off type. .

In this simulation, the material (mother crystal) of the n-type semiconductor layer 11 is Ga ₂ O ₃ single crystal, the material of the gate insulating film 13 is HfO ₂ , and the thickness of the portion of the gate insulating film 13 in contact with the bottom of the trench 16 is T. ₁ is 0.05 μm, the width W _m of the mesa-shaped portion 17 is 0.4 μm, and the thickness T _p of the breakdown voltage layer 11a (from the bottom of the trench 16 in the n-type semiconductor layer 11 to the interface with the n-type semiconductor substrate 10 The donor concentration of the breakdown voltage layer 11a is set to 1.2×10 ¹⁶ cm ⁻³ and the donor concentration of the channel layer 11b is set to 1×10 ¹⁶ cm ⁻³ , and the source electrode 14 and gate electrode are grounded. (0 V was applied), and a voltage of 10 kV was applied to the drain electrode 15.

FIG. 8 is a graph showing the relationship between the voltage applied between the source electrode 14 and the drain electrode 15 and the off-leakage current when the distance _Lc between the gate electrode 12 and the contact layer 11c is changed. . In FIG. 8, 1×10 ⁻⁴ A/cm ² , which is the magnitude of off-leakage current that is an indicator of channel opening/closing, is indicated by a dotted line.

According to FIG. 8, if the distance _Lc between the gate electrode 12 and the contact layer 11c is 0.1 μm or more, even if a voltage of 10 kV is applied between the source electrode 14 and the drain electrode 15, the off-leakage current will decrease. The size does not reach 1×10 ⁻⁴ A/cm ² and it can be said that the channel is closed.

From this result, it can be said that when the trench MOSFET 1 is a normally-off type, the distance L _c between the gate electrode 12 and the contact layer 11c is preferably 0.1 μm or more in order to suppress off-leakage current.

Note that in the simulation of this example, the material (mother crystal) of the n-type semiconductor layer 11 was set to Ga ₂ O ₃ single crystal, but similar results would be obtained even if other Ga ₂ O ₃ type single crystals were used. is obtained. Similarly, although the material of the gate insulating film 13 is set to HfO ₂ , similar results can be obtained even if it is set to SiO ₂ .

Regarding the trench MOSFET 1 according to the embodiment described above, the relationship between the thickness T ₁ of the portion of the gate insulating film 13 (portion 13a) in contact with the center of the bottom of the trench 16 and the maximum electric field strength E _max in the n-type semiconductor layer 11 was investigated by simulation.

In this simulation, the material (mother crystal) of the n-type semiconductor layer 11 is Ga ₂ O ₃ single crystal, the material of the gate insulating film 13 is HfO ₂ , the width W _m of the mesa-shaped portion 17 is 0.4 μm, and the breakdown voltage layer 11a is The thickness T _p (distance from the bottom of the trench 16 to the interface with the n-type semiconductor substrate 10 in the n-type semiconductor layer 11) is 45 μm, the donor concentration of the breakdown voltage layer 11a is 8×10 ¹⁵ cm ⁻³ , and the channel layer The donor concentration of 11b was set at 1×10 ¹⁶ cm ⁻³ , the source electrode 14 and the gate electrode were grounded (0 V was applied), and a voltage of 10 kV was applied to the drain electrode 15 .

FIG. 9 is a graph showing the relationship between the thickness T ₁ of the gate insulating film 13 and the maximum electric field strength E _max in the n-type semiconductor layer 11. Table 5 below shows the numerical values of the plot points in FIG.

According to FIG. 9, as the thickness T ₁ increases, the maximum electric field strength E _max rapidly decreases to approximately 0.5 μm. Therefore, in order to keep the electric field strength in the n-type semiconductor layer 11 low, the thickness _T1 is preferably in the range of 0.2 μm or more and 0.5 μm or less.

On the other hand, the larger the thickness _T1 , the more difficult it becomes to form the gate insulating film 13 (portion 13a) inside the trench 16. Therefore, from the viewpoint of ease of forming the gate insulating film 13, the thickness _T1 is preferably in the range of 0.1 μm or more and less than 0.2 μm.

Note that in the simulation of this example, the material (mother crystal) of the n-type semiconductor layer 11 was set to Ga ₂ O ₃ single crystal, but similar results would be obtained even if other Ga ₂ O ₃ type single crystals were used. is obtained. Similarly, although the material of the gate insulating film 13 is set to HfO ₂ , similar results can be obtained even if it is set to SiO ₂ .

Regarding the trench MOSFET 1 according to the above embodiment, the relationship between the mesa depth D _m and the maximum electric field strength E _max in the n-type semiconductor layer 11 when the n-type semiconductor layer 11 has the mesa shape shown in FIG. was investigated by simulation.

In this simulation, the material (mother crystal) of the n-type semiconductor layer 11 is Ga ₂ O ₃ single crystal, the material of the gate insulating film 13 is HfO ₂ , and the thickness of the portion of the gate insulating film 13 in contact with the bottom of the trench 16 is T. ₁ is 0.15 μm, the width W _m of the mesa-shaped portion 17 is 0.4 μm, and the width W m of the mesa-shaped portion 17 is 0.4 μm. The radius of curvature was set to 0.2 μm, the source electrode 14 and the gate electrode were grounded (0 V was applied), and a voltage of 0.6 to 10 kV was applied to the drain electrode 15.

First, simulation results will be shown when a voltage of 10 kV is applied to the drain electrode 15. The thickness T _p (distance from the bottom of the trench 16 to the interface with the n-type semiconductor substrate 10 in the n-type semiconductor layer 11) of the voltage-resistant layer 11a is 33.4 μm, and the donor concentration of the voltage-resistant layer 11a is 8×10 ¹⁵ cm. ⁻³ , and the donor concentration of the channel layer 11b was set to 1×10 ¹⁶ cm ⁻³ .

FIG. 10A is a graph showing the relationship between the mesa depth D _m and the maximum electric field strength E _max in the n-type semiconductor layer 11 when a voltage of 10 kV is applied to the drain electrode 15. Table 6 below shows the numerical values of the plot points in FIG. 10(a).

According to FIG. 10(a), as the mesa depth D _m increases, the maximum electric field strength E _max in the n-type semiconductor layer 11 decreases, and at approximately 10 μm or more, Ga ₂ estimated from the band gap size decreases. It is lower than 8 eV, which is the dielectric breakdown field strength of _O3 .

Next, simulation results when a voltage of 3.3 kV is applied to the drain electrode 15 will be shown. The thickness T _p of the breakdown voltage layer 11a (the distance from the bottom of the trench 16 to the interface with the n-type semiconductor substrate 10 in the n-type semiconductor layer 11) is 10.4 μm, and the donor concentration of the breakdown voltage layer 11a is 3×10 ¹⁶ cm. ⁻³ , and the donor concentration of the channel layer 11b was set to 1×10 ¹⁶ cm ⁻³ .

FIG. 10B is a graph showing the relationship between the mesa depth D _m and the maximum electric field strength E _max in the n-type semiconductor layer 11 when a voltage of 3.3 kV is applied to the drain electrode 15. Table 7 below shows the numerical values of the plot points in FIG. 10(b).

According to FIG. 10(b), the maximum electric field strength E _max in the n-type semiconductor layer 11 decreases as the mesa depth D _m increases, and is estimated from the band gap size at approximately 0.8 μm or more. It is lower than 8 eV, which is the dielectric breakdown field strength of Ga ₂ O ₃ .

Next, simulation results when a voltage of 1.2 kV is applied to the drain electrode 15 will be shown. The thickness T _p of the breakdown voltage layer 11a (distance from the bottom of the trench 16 to the interface with the n-type semiconductor substrate 10 in the n-type semiconductor layer 11) is 3.5 μm, and the donor concentration of the breakdown voltage layer 11a is 9×10 ¹⁶ cm. ⁻³ , and the donor concentration of the channel layer 11b was set to 1×10 ¹⁶ cm ⁻³ .

FIG. 11A is a graph showing the relationship between the mesa depth D _m and the maximum electric field strength E _max in the n-type semiconductor layer 11 when a voltage of 1.2 kV is applied to the drain electrode 15. Table 8 below shows the numerical values of the plot points in FIG. 11(a).

According to FIG. 11(a), the maximum electric field strength E _max in the n-type semiconductor layer 11 decreases as the mesa depth D _m increases, and is estimated from the band gap size at approximately 0.4 μm or more. It is lower than 8 eV, which is the dielectric breakdown field strength of Ga ₂ O ₃ .

Next, simulation results when a voltage of 0.6 kV is applied to the drain electrode 15 will be shown. The thickness T _p of the breakdown voltage layer 11a (the distance from the bottom of the trench 16 to the interface with the n-type semiconductor substrate 10 in the n-type semiconductor layer 11) is 2.9 μm, and the donor concentration of the breakdown voltage layer 11a is 1.8×10 ¹⁷ cm ^-3 and the donor concentration of the channel layer 11b was set to 1×10 ¹⁶ cm ^-3 .

FIG. 11B is a graph showing the relationship between the mesa depth D _m and the maximum electric field strength E _max in the n-type semiconductor layer 11 when a voltage of 0.6 kV is applied to the drain electrode 15. Table 9 below shows the numerical values of the plot points in FIG. 11(b).

According to FIG. 11(b), the maximum electric field strength E _max in the n-type semiconductor layer 11 decreases as the mesa depth D _m increases, and is estimated from the band gap size at approximately 0.6 μm or more. It is lower than 8 eV, which is the dielectric breakdown field strength of Ga ₂ O ₃ .

From the above results, when the voltage applied to the drain electrode 15 is 0.6 to 10 kV, the electric field strength in the n-type semiconductor layer 11 can be lowered by providing a mesa shape with an appropriate mesa depth D _m . It was confirmed that it can be suppressed.

Note that in the simulation of this example, the material (mother crystal) of the n-type semiconductor layer 11 was set to Ga ₂ O ₃ single crystal, but similar results would be obtained even if other Ga ₂ O ₃ type single crystals were used. is obtained. Similarly, although the material of the gate insulating film 13 is set to HfO ₂ , similar results can be obtained even if it is set to SiO ₂ .

Regarding the trench MOSFET 1 according to the embodiment described above, the relationship between the donor concentration and the thickness T _p of the breakdown voltage layer 11a to obtain a desired breakdown voltage was investigated by simulation.

In this simulation, the material (mother crystal) of the n-type semiconductor layer 11 of the trench MOSFET 1 is Ga ₂ O ₃ single crystal, the material of the gate insulating film 13 is HfO ₂ , and the thickness of the portion of the gate insulating film 13 in contact with the bottom of the trench 16 is The radius of curvature R ₁ at the apex of the curve of the bottom edge 160 of the trench 16 in the cross section in the width direction of the _trench 16 is 0.06 μm, the apex of the curve of the bottom edge 120 of the gate electrode 12 The radius of curvature R ₂ in the gate electrode 12 is 0.2 μm, the gate length L _g of the gate electrode 12 is 0.9 μm, the width W _m of the mesa-shaped portion 17 is 0.4 μm, and the donor concentration of the channel layer 11b is 1×10 ¹⁶ cm ⁻³ The source electrode 14 and the gate electrode were grounded (0 V was applied), and a desired voltage was applied to the drain electrode 15.

The following Table 10 shows suitable values for the donor concentration and thickness T _p of the breakdown voltage layer 11a to obtain the desired breakdown voltage, assuming that the dielectric breakdown field strength of Ga ₂ O ₃ is 8 MV/cm. .

The following Table 11 shows suitable values for the donor concentration and thickness T _p of the breakdown voltage layer 11a to obtain the desired breakdown voltage, assuming that the dielectric breakdown field strength of Ga ₂ O ₃ is 7 MV/cm. .

The following Table 12 shows suitable values for the donor concentration and thickness T _p of the breakdown voltage layer 11a to obtain the desired breakdown voltage, assuming that the dielectric breakdown field strength of Ga ₂ O ₃ is 6 MV/cm. .

Table 13 below shows suitable values for the donor concentration and thickness T _p of the breakdown voltage layer 11a to obtain the desired breakdown voltage, assuming that the dielectric breakdown field strength of Ga ₂ O ₃ is 5 MV/cm. .

Table 14 below shows suitable values for the donor concentration and thickness T _p of the breakdown voltage layer 11a to obtain the desired breakdown voltage, assuming that the dielectric breakdown field strength of Ga ₂ O ₃ is 4 MV/cm. .

Note that in the simulation of this example, the material (mother crystal) of the n-type semiconductor layer 11 was set to Ga ₂ O ₃ single crystal, but similar results would be obtained even if other Ga ₂ O ₃ type single crystals were used. is obtained. Similarly, although the material of the gate insulating film 13 is set to HfO ₂ , similar results can be obtained even if it is set to SiO ₂ .

Although the embodiments and examples of the present invention have been described above, the present invention is not limited to the above embodiments and examples, and various modifications can be made without departing from the gist of the invention. For example, the trench structure of the trench type MOSFET of the present invention can also be applied to a trench MOS type SBD (Schottky Barrier Diode).

Moreover, the embodiments and examples described above do not limit the invention according to the claims. Furthermore, it should be noted that not all combinations of features described in the embodiments and examples are essential for solving the problems of the invention.

DESCRIPTION OF SYMBOLS 1... Trench type MOSFET, 10... N-type semiconductor substrate, 11... N-type semiconductor layer, 12... Date electrode, 13... Gate insulating film, 14... Source electrode, 15... Drain electrode, 16... Trench, 17... Mesa shape part

Claims (7)

an n-type semiconductor layer made of Ga ₂ O ₃ single crystal and having a plurality of trenches opened on one surface;
a gate insulating film provided in contact with the inner surface of each of the plurality of trenches;
a gate electrode buried in each of the plurality of trenches while being covered with the gate insulating film;
a source electrode connected to a mesa-shaped portion between the adjacent trenches of the n-type semiconductor layer;
a drain electrode connected directly or indirectly to the side opposite to the source electrode of the n-type semiconductor layer;
Equipped with
The value obtained by dividing the radius of curvature at the apex of the curve of the bottom edge of the trench by the width of the trench in a cross section in the width direction of the trench is within the range of 0.0125 or more and 0.25 or less.
Trench type MOSFET. When the channel concentration, which is the donor concentration, in the region between the two adjacent gate electrodes in the n-type semiconductor layer is 1×10 ¹⁵ cm ⁻³ or less, the mesa width, which is the width of the mesa-shaped portion, is 0.5 cm. 5 μm or less,
When the channel concentration is greater than 1×10 ¹⁵ cm- ³ and less than 1×10 ¹⁶ cm- ³ , the mesa width is 0.4 μm or less,
When the channel concentration is greater than 1×10 ¹⁶ cm- ³ and less than 2×10 ¹⁶ cm- ³ , the mesa width is 0.3 μm or less,
When the channel concentration is greater than 2×10 ¹⁶ cm and ^less than 6×10 ¹⁶ cm, the mesa width is less than ^or equal to 0.2 μm.
Trench type MOSFET according to claim 1. The work function of the gate electrode is 5.0 eV or more.
Trench type MOSFET according to claim 1 or 2. The gate length of the gate electrode is 1 μm or more,
Trench type MOSFET according to any one of claims 1 to 3. The n-type semiconductor layer has a contact layer near the interface with the source electrode for making an ohmic connection between the n-type semiconductor layer and the source electrode,
The distance between the gate electrode and the contact layer is 0.1 μm or more,
Trench type MOSFET according to any one of claims 1 to 4. The thickness of the portion of the gate insulating film that is in contact with the center of the bottom of the trench is within the range of 0.2 μm or more and 0.5 μm or less, or within the range of 0.1 μm or more and less than 0.2 μm.
Trench type MOSFET according to any one of claims 1 to 5. The n-type semiconductor layer has a mesa shape with a depression provided at an upper edge,
the gate electrode is exposed on the inner surface of the recess;
Trench type MOSFET according to any one of claims 1 to 6.

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