CN105100654B - A kind of pixel unit circuit and pixel read chip - Google Patents
A kind of pixel unit circuit and pixel read chip Download PDFInfo
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- CN105100654B CN105100654B CN201510599716.2A CN201510599716A CN105100654B CN 105100654 B CN105100654 B CN 105100654B CN 201510599716 A CN201510599716 A CN 201510599716A CN 105100654 B CN105100654 B CN 105100654B
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Abstract
The embodiment of the invention discloses a kind of pixel unit circuit and pixel to read chip, and pixel unit circuit includes：One charge sensitive preamplifier, low noise amplification is carried out to the detector signal of pixel；One discriminator, for the detectable signal after progress low noise amplification to be compared with threshold value, examination judgement is carried out to useful signal；One counter chain, including N-bit counter, for being the integer more than 1 to useful signal progress counting statistics, wherein N according to judged result is screened；One shift register chain, including N-bit register, are connected with the counter chain respectively, and when frame refreshing signal arrives, the counting statistics result in the counter chain is carried out displacement reading by the shift register chain.The technical scheme of the embodiment of the present invention, which can reduce, reads the dead time, lifts the frame refresh rate index of chip.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of pixel unit circuit and pixel read chip.
Background technology
Traditional pixel reads chip or pixel detection system, and the mode for being based primarily upon charge integration is completed to letter
Number detection.Such as CCD (Charge-coupled Device, charge coupled cell), a kind of CMOS (typical solid state images
Sensor) camera etc., the electric capacity being connected by same feeling optical diode is integrated to electric charge, and the amplitude after integration is carried out
Read, as depicted in figs. 1 and 2, so as to realize detection to the semaphore in a period of time.This mode can not effective resoluting signal
And noise, signal to noise ratio be not high.
In order to effectively be differentiated to single photon or incoming particle, one kind is developed based on single photon signal processing
Pixel reads chip form.As shown in figure 3, this kind of chip is by charge sensitive preamplifier, first by single incoming signal
Low noise amplification is carried out, afterwards by given threshold, noise signal of the amplitude less than the threshold value is rejected, so as to obtain nothing
The real detector signal of noise.To crossing threshold discriminator signal, simplest processing mode is exactly to crossing threshold thing in a period of time
Number of cases is counted, and so as to obtain the statistics of luminance signals in this period indirectly, this mode is referred to as single-photon counting mode.
Thereafter, chip needs that the count results of each pixel are read and reset by certain refreshing frequency, to start a new round
Counting.If using the counting of each pixel as brightness of image, the position of the two-dimensional position corresponding diagram picture point of pixel is read-out
Data are formed a two field picture, i.e. chip is usually operated under frame refreshing pattern.
Some the existing development of single photon counting type pixel chip, are mainly used in synchrotron radiation or imaging of medical application.Wherein
The structured flowchart difference of the pixel unit circuit of two kinds of representative main products is as shown in Figure 4, Figure 5.From the figure, it can be seen that two
The analog front circuit part of kind product is similar, defeated to detector by the charge sensitive preamplifier being described above
Enter signal and carry out low noise amplification, afterwards by discriminator (in Figure 5 be referred to as discriminator, Discriminator) by signal width
Degree is compared with given threshold, is counted using counter to crossing threshold signal.
Two kinds of products have some differences on playback mode.In Fig. 4, the count results of counter are gated by ranks
Mode, read by way of column bus.I.e. in the readout process, the count results of counter are locked, by row,
Array selecting signal enables pixel successively, count results is connected on data/address bus, is read so as to realize.And in Figure 5, read
It is to be completed by way of linear feedback shift register, i.e., in counting stage, the part logic is as a pseudo random number
Counter works, counted to screening threshold signal；And will be with front and rear adjacent pixel phase in the stage of reading, the part logic
Even, it is operated as one section in shift register long-chain, by global clock, the count results of each pixel are moved successively
Position is to chip pin and exports.
It can be seen that two kinds of main product playback modes have the shortcomings that common：Reading hour counter can not be carried out simultaneously
Count.In Fig. 4, counter needs to wait by carry to data/address bus, therefore result needs to be in latch mode, until a frame knot
Fruit is read, and can be just cleared and be continued next task；And in Fig. 5, counter circuit is occupied when reading to be turned into
Shift register, also only it can just switch back into count mode after the completion of frame reading.Therefore the readout time of both structures
The detection dead time will all be turned into, while the working method also limit the raising of frame refresh rate：I.e. if to improve frame refresh rate,
Readout time is only reduced, therefore high-frequency clock and high speed readout logic certainly will be used, such one side high-speed digital circuit
Design difficulty greatly promotes, while the introducing of high-speed digital signal also will cause more crosstalks to sensitive analog circuit.
Two kinds of reading methods that Fig. 4, Fig. 5 are discussed, it is the main representative of single photon counting type pixel chip various product
Property reading out structure.Thus the limitation of structure and operation principle, the frame refresh rate index of both main flow series latest edition products are equal
The only level in tens frame per second to 100 frame per second, and need to use the high-frequency clock of about 100MHz or so clock frequencies,
Nevertheless, the dead time is still up to per frame 3ms or so.The frame refresh rate and dead time index can not meet latest generation synchronization
The demand of radiation application, and the product for meeting to require can not be also found in the market.This kind of application requirement is ensureing performance
On the premise of, the refresh rate for being better than 1,000 frame per second is realized, so as to which some short life samples are observed with its dynamic response.Therefore
The single photon counting type pixel for developing a kind of high frame refresh rate reads chip design method, turns into and promotes the technology in more high-end field
Close the key of application.
Further, since being operated under radiation condition, the design for reading chip must take into consideration Flouride-resistani acid phesphatase design.Produced in each main flow
In the pixel cell configuration register of product, generally using classical triplication redundancy circuit, to single-particle inversion example (Single
Event Upset, SEU) carry out a certain degree of radiation hardened.As shown in Figure 6 and Figure 7, configuration register typically each uses
Certain Redundancy Design.For every pixel cell usually requires the even more pixels reading chips in 5,6 deposit positions, this
Substantial amounts of space will be taken.For playback mode proposed by the invention on the premise of performance is ensured, can also take into account reduces the part
Design complexities, save pixel space.
The content of the invention
In view of this, the embodiment of the present invention provides a kind of pixel unit circuit and pixel reads chip, is read with realizing to reduce
Go out the dead time, lift the frame refresh rate index of chip.
Other characteristics and advantage of the disclosure will be apparent from by following detailed description, or partially by the disclosure
Practice and acquistion.
In a first aspect, the embodiments of the invention provide a kind of pixel unit circuit, including：
One charge sensitive preamplifier, low noise amplification is carried out to the detector signal of pixel；
One discriminator, for the detectable signal after progress low noise amplification to be compared with threshold value, useful signal is entered
Row, which is screened, to be judged；
One counter chain, including N-bit counter, for carrying out counting statistics to useful signal according to examination judged result,
Wherein N is the integer more than 1；
One shift register chain, including N-bit register, it is connected respectively with the counter chain, when frame refreshing signal arrives
When, the counting statistics result in the counter chain is carried out displacement reading by the shift register chain.
Further, the pixel unit circuit also includes a configuration register module, connects with the shift register chain
Connect；
When frame refreshing signal arrives, under the configuration register module inputs to the input of the shift register chain
The configuration information of one frame, while the shift register chain exports the counting statistics result of previous frame from output end, it is described to match somebody with somebody
Confidence ceases and the counting statistics result does not pass through the shift register chain overlappingly.
Further, when frame refreshing signal arrives, specifically include：
When frame refreshing signal arrives in rising edge clock, the discriminator is shielded with the counter chain signal path
Cover, so that the counting statistics result of the previous frame in the counter chain is blocked；
Since in first clock cycle subsequent clock falling edge：The configuration register module is changed into transparent lock
Deposit state, the configuration information on the shift register chain is refreshed to corresponding to each in the configuration register module and configured
Register, the working condition as the next frame of pixel cell corresponding to the pixel unit circuit define；
Since in second clock cycle the clock falling edge：The previous frame in the counter chain being blocked
Counting statistics result be loaded in the shift register chain；
Since in the 3rd clock cycle the clock falling edge：The counting statistics result of the counter chain
It is cleared, while the block of the counter chain is released from.
Further, also include after the block of the counter chain is released from：
N-bit counter in the counter chain starts to carry out counting statistics to the useful signal for crossing threshold in a new frame,
The configuration information of a new frame inputs from the input of the shift register chain, while the enumeration data of previous frame is from displacement
Chain output end is exported, and configuration data stream and enumeration data stream are just nonoverlapping to be flowed by shift chain.
Further, between the charge sensitive preamplifier and the discriminator, in addition to shaping/amplification mould
Block, for the detectable signal after the progress low noise amplification further to be amplified into filtering；
The discriminator, for the filtered detectable signal of amplification to be compared with threshold value, useful signal is entered
Row, which is screened, to be judged.
Further, the N is the integer more than or equal to 4, and less than or equal to 20.
Second aspect, the embodiment of the present invention additionally provide a kind of pixel and read chip, including it is multiple as described in relation to the first aspect
Pixel unit circuit.
Further, the pixel reads chip and included：
104 row X72 row pel arrays；
9 pixel unit circuits as described in claim any one of 1-5；
The pixel of 104 row X72 row is included in every pixel unit circuit, pixel depth is 20.
Further, the frame refreshing frequency of the pixel reading chip is more than or equal to 1.2 KHzs, and the pixel is read
The clock frequency of chip is more than or equal to 20 megahertzs.
The advantageous effects of technical scheme that the embodiment of the present invention proposes are：
Pixel unit circuit described in the embodiment of the present invention includes a counter chain of N-bit counter, for pixel cell
In by screen judge useful signal carry out counting statistics；The register being connected respectively with the counter chain including N positions
One shift register chain, when frame refreshing signal arrives, the shift register chain is by the counting statistics in the counter chain
As a result displacement reading is carried out.Frame refresh rate can be significantly improved.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, institute in being described below to the embodiment of the present invention
The accompanying drawing needed to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, it can also be implemented according to the present invention
The content of example and these accompanying drawings obtain other accompanying drawings.
Fig. 1 is a kind of integral voltage playback mode circuit theory diagrams described in background of invention；
Fig. 2 is work schedule corresponding to integral voltage playback mode circuit theory diagrams described in background of invention
Figure；
Fig. 3 is a kind of single photon counting type pixel playback mode theory diagram described in background of invention；
Fig. 4 is that a kind of main flow single photon counting type pixel described in background of invention reads one of chip product
Pixel unit circuit structured flowchart；
Fig. 5 is the two pixel list that a kind of main flow single photon counting type pixel reads chip product in background of invention
First circuit structure block diagram；
Fig. 6 is the triplication redundancy and arbitrated logic block diagram described in background of invention；
Fig. 7 is the transistor-level schematic of DICE Latch described in background of invention a kind of；
Fig. 8 is the pixel unit circuit structured flowchart described in the embodiment of the present invention one；
Fig. 9 is the gate leve structured flowchart of the pixel unit circuit reading section described in the embodiment of the present invention one；
Working timing figure when Figure 10 is the pixel unit circuit reading section frame refreshing described in the embodiment of the present invention one；
Figure 11 is the overall structure block diagram of a single photon counting type pixel reading chip described in the embodiment of the present invention two.
Embodiment
For make present invention solves the technical problem that, the technical scheme that uses and the technique effect that reaches it is clearer, below
The technical scheme of the embodiment of the present invention will be described in further detail with reference to accompanying drawing, it is clear that described embodiment is only
It is part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those skilled in the art exist
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
Further illustrate technical scheme below in conjunction with the accompanying drawings and by embodiment.
Embodiment one
Fig. 8 is the pixel unit circuit described in the present embodiment, as shown in figure 8, the pixel unit circuit described in the present embodiment
Including：
One charge sensitive preamplifier 1, low noise amplification is carried out to the detector signal of pixel；
One discriminator 2, for the detectable signal after progress low noise amplification to be compared with threshold value, useful signal is entered
Row, which is screened, to be judged；
One counter chain 3, including N-bit counter, for carrying out counting statistics to useful signal according to examination judged result；
One shift register chain 4, including N-bit register, it is connected respectively with the counter chain 3, when frame refreshing signal
During arrival, the counting statistics result in the counter chain 3 is carried out displacement reading by the shift register chain 4.
It should be noted that the pixel unit circuit described in the present embodiment is preposition using charge-sensitive in AFE(analog front end) part
Amplifier 1 carries out low noise amplification to detector signal, can guarantee that pixel reads the low-noise performance of chip.Discriminator 2 is by before
Put output to be compared with threshold value, judge so as to complete to screen to useful signal；Examination result gives counter and carries out counting system
Meter.
In order to which signal further to be amplified to filtering, it is easy to screen, the present embodiment can also be in the preposition amplification of the charge-sensitive
It is using shaping/amplification module 5 that the detectable signal after the progress low noise amplification is further between device 1 and the discriminator 2
Amplification filtering.Now, the discriminator 2, for the filtered detectable signal of amplification to be compared with threshold value, to useful
Signal carries out examination judgement.
Pixel unit circuit described in the embodiment of the present invention includes a counter chain 3 of N-bit counter, for pixel cell
In by screen judge useful signal carry out counting statistics；The register being connected respectively with the counter chain 3 including N positions
One shift register chain 4, when frame refreshing signal arrives, the shift register chain 4 unites the counting in the counter chain 3
Meter result carries out displacement reading.It can reduce and read the dead time, lift the frame refresh rate index of chip.
Wherein, N is the integer more than 1, and preferably N is more than or equal to 4 integers for being less than or equal to 20.Such as N is 20, institute
State counter chain 3 includes 20 digit counters in each pixel cell, i.e., according to the counting rate of each 1 megahertz of pixel,
Refreshed with the refresh rate of 1 frame per second, just 20 of the full counter of meter.If refreshed with faster refresh rate, that
Number of counter bits needed under same counting rate will be reduced accordingly.Accordingly, the shift register chain 4 is also each
Pixel cell includes 20 bit shift information, and each counter position connects with corresponding shift register bit respectively.
Further, there is larger difference with each like product in reading section, the embodiment of the present invention.In order to avoid data are read
Go out occupancy of the stage to counter, need to design work and digit phase independently of one another in the pixel unit circuit described in the present embodiment
Same counter chain 3 and shift register chain 4 each one.Data exchange only occurs when frame refreshing signal arrives between the two, its
Holding time is a clock cycle.
In addition, the pixel unit circuit also includes a configuration register module, it is connected with the shift register chain 4.
When frame refreshing signal arrives, the configuration register module inputs next frame to the input of the shift register chain 4
Configuration information, while the shift register chain 4 exports the counting statistics result of previous frame from output end, the configuration information
Do not pass through the shift register chain 4 overlappingly with the counting statistics result.
The configuration information of pixel unit circuit described in the present embodiment will be inputted using same shift chain, when frame brush
When new signal arrives, the configuration information on shift chain is flushed in the configuration register that each pixel cell corresponds to position.For example, work as
When frame refreshing signal arrives, the specific works details of reading section is as follows：
When frame refreshing signal arrives in rising edge clock, the discriminator 2 is shielded with the signal path of counter chain 3
Cover, so that the counting statistics result of the previous frame in the counter chain 3 is blocked；
Since in first clock cycle subsequent clock falling edge：The configuration register module is changed into transparent lock
Deposit state, the configuration information on the shift register chain 4, which is refreshed to corresponding to each in the configuration register module, matches somebody with somebody
Register is put, the working condition as the next frame of pixel cell corresponding to the pixel unit circuit defines；
Since in second clock cycle the clock falling edge：Described upper one in the counter chain 3 being blocked
The counting statistics result of frame is loaded in the shift register chain 4；
Since in the 3rd clock cycle the clock falling edge：The counting statistics knot of the counter chain 3
Fruit is cleared, while the block of the counter chain 3 is released from；
Counter, shift register and configuration register independently work afterwards.
Aforesaid operations are circulated until reading all frames of pixel cell corresponding to the pixel unit circuit.
Fig. 9 gives reading section more specifically gate level circuit structured flowchart.Wherein each several part circuit is only most basic with its
Part signal, show mentality of designing, but be not limited to the physical circuit form shown in figure.It is every to be based on the structure
Derivative circuit structure, in covering scope of the present invention.Figure 10 gives pixel unit circuit before the arrival of frame refreshing signal
Key job sequential afterwards.
As shown in Figure 9, Figure 10, in normal operating conditions, counter persistently counts to screening pulse, and shift LD
One section as integral shift of device, the displacement for participating in enumeration data is read, while configuration information is carried out into displacement input；When frame brush
When rising edge clock arrives the action of four steps occurs successively for new signal (frame signals in figure)：The same data of counter
The output of source, i.e. discriminator is disconnected, and data are blocked, pixel_down signals in corresponding diagram；Since subsequent clock falling edge
A clock cycle in, the configuration register in pixel unit circuit is changed into transparent latch mode, matches somebody with somebody confidence on shift chain
Breath is refreshed in each corresponding configuration register of pixel cell, and refresh signals in corresponding diagram are next as the pixel cell
The working condition definition of frame；An ensuing clock cycle (still since clock falling edge), the counter counts being blocked
Number data, which are latched, to be loaded onto in shift chain, load_shiftb signals in corresponding diagram；(from clock in the 3rd clock cycle
Trailing edge starts), counter results are cleared, while data locking is released from, counter_clear signals in corresponding diagram.Extremely
After this, counter and shift chain can be completely independent work again：Counter starts to count to screening threshold signal in a new frame；
The configuration information of next frame inputs from shift chain input, while the enumeration data of previous frame exports from shift chain output end, matches somebody with somebody
Put that data flow and enumeration data stream are just nonoverlapping to be flowed by shift chain.When frame refreshing signal arrives again,
Repeat above-mentioned process.
, wherein it is desired to which explanation, configuration register are mainly used in storing the mode of operation control bit information of each pixel, wrap
Containing threshold information, pixel enables information and charge polarity information etc..During every frame works, configuration information is with dead level
Mode controls the working condition of the analog circuits such as discriminator, so as to which the examination to signal judges to be adjusted control, thus can shadow
Ring count results；Refresh the configuration status for next frame when frame refreshing signal arrives, so as to control the Counts of a new round
Pattern.Each of shift chain can carry a configuration register or zero load, during the refresh signals that frame signal arrives
Refreshed.The digit that each pixel corresponds to configuration register is determined by concrete application demand, but not more than shift register chain
Length, this example be eight.Shift register chain is not more than in digit in configuration register, and is corresponded with displacement chain element
On the premise of can be in any combination with shift register chain link.
According to such playback mode, start the meter of a new frame again after the completion of every frame Counter is without waiting for reading
Number, that is, count and reading is completely self-contained.In every frame time, counter is only in 3.5 clocks of frame refreshing signal arrival
It is occupied in cycle, therefore the dead time is only 3.5 times of clock cycle.Calculated according to 20MHz typical clock, that is, often
The dead time of frame is only 175ns, and compared to current newest main product typically per frame 3ms dead time, its performance indications is at least
Improve ten times.And when clock frequency improves, the dead time will also accordingly reduce.
Because readout time and dead time are unrelated, therefore high-frequency clock need not be recycled, need not also rechallenged at a high speed
Design of Digital Circuit reduces readout time as far as possible.According to reading out structure of the present invention, the shift LD in pixel cell
Device length needs and counter depth is completely the same, while show also the clock periodicity of every frame time.Assuming that counter is deep
Spend for N positions, the number of pixel cells on shift chain is M, clock frequency F, then the clock periodicity per frame is (M*N+1), also
It is that frame refresh rate is F/ (M*N+1).Wherein counting depth N is generally less than 20, and number of pixel cells M is usually 1000, therefore
Under 20MHz clock frequency, frame refresh rate is just up to 1kHz, compared to current frame refreshing of the newest main product less than 100Hz
Rate is horizontal, and performance indications also improve ten times.In the process, not using high-frequency clock, therefore the crosstalk between modulus will
It can be effectively controlled；It is simultaneously strong also without the circuit design of complexity, exploitativeness.In view of in high frame refresh rate index
Under, counting depth can typically shorten, such as 10, then frame refresh rate index also will increase further.
According to working method of the present invention, configuration information of each pixel cell per frame will be defeated by shift register
Enter, and realize the renewal per frame.So, once single example rollover event occurs, certain configuration information latched bit is caused just
Often the mistake upset during work, erroneous effects caused by it will be also corrected in back to back next frame.Due to realizing simultaneously
High frame refresh rate, therefore it is very limited amount of to influence.So, configuration register can use more conventional latch
Device is designed, and avoids designing complex redundancy logic, and a large amount of versions are taken in this very limited amount of pixel unit circuit
Map space.On the other hand, the configuration information of conventional pixel chip generally only in power up phase loading once, one during normal work
As do not update, and triplication redundancy circuit for twice mistake upset will be unable to detect.Therefore once the mistake of identical point twice occurs
By mistake overturn, pixel chip will in the state of mistake continuous firing, persistently obtain wrong data.The present invention is using frame refreshing
Mode thoroughly avoids the generation of such case, by erroneous effects limitation within a very short time, ensures circuit in the overwhelming majority
It is interior to be all operated in normal operating conditions.
By the counter chain 3 and shift chain of two autonomous workings, reduce and read the dead time, while to the frame refreshing of chip
Rate index is obviously improved.By way of configuration register frame refreshing, the latch radiation hardened design of complexity is avoided.
The present invention has the features such as structure is reliable, and exploitativeness is strong, and scalability is strong.
Embodiment two
On the basis of embodiment one, the present embodiment proposes a kind of pixel and reads chip, including multiple such as embodiment
Pixel unit circuit described in one.Figure 11 is that a single photon counting type pixel described in the embodiment of the present invention two reads chip
Overall structure block diagram, as shown in figure 11, the pixel read chip and use multiple pixel unit circuits as described in embodiment one,
Pixel in all pixels display that can be achieved to include chip carries out pixel reading.
In order that those skilled in the art are better understood from technical scheme, with reference to embodiment and accompanying drawing
Product of the present invention is further described.
According to working method of the present invention, inventor completes a single photon counting type pixel and reads setting for chip
Meter.Chip includes the row pel array of 104 rows × 72, the shift chains by column split into 9 autonomous workings, i.e. is wrapped in every shift chain
Containing 104 rows × 8 row totally 832 pixels, pixel counts depth is 20.By actual flow and test, chip energy works fine
Under the system clock frequency of 20MHz even more highs, and the crosstalk between modulus circuit is not found.This shows to read chip energy
It is operated under 1.2kHz frame refresh rate frequency, is less than 175ns per the frame dead time.The scale of the pixel chip is the same as in the market
Mainstream chip it is suitable, the measured performance index of analog portion also maintains an equal level with such chip, however frame refresh rate index and it is dead when
Between index improve nearly 10 times compared to mainstream chip, and chip and do not rely on high-frequency clock or High-speed Board Design.This card
Bright structure of the present invention and design method have good exploitativeness.
Detector small-signal can be handled to ensure that pixel reads chip, should be ensured that pixel cell electricity first
The design of good analog front circuit, particularly charge sensitive preamplifier in road, it determines whole pixel chip
The signal of noise level and minimum detectable.The design of analog front circuit can follow the classical circuit design side of nuclear electronics
Method, input pipe size is put before carefully designing charge-sensitive, so as to obtain optimal signal noise ratio level.Because high frame refresh rate is usual
Mean that high example rate is horizontal, therefore need to carefully design the feedback arrangement put before charge-sensitive so that output signal bottom width expires
The required counting rate of foot is horizontal.Discriminator circuit requirement can be finely adjusted to discriminator, generally can be by the number of 4~6
Touch translation circuit realization.
Unit digital circuit on the whole can be as shown in Figure 9 counter, shift register and latch three parts composition.
In the case that pixel cell area allows, each digital gate level circuit can use standard cell lib to realize.Preferably, each numeric door
Level circuit can also use the method for full custom to design, and this will effectively save pixel cell area, but also imply that design efforts would
Be obviously improved, while it is horizontal to sacrifice certain highest frame refresh rate.It is short between each unit when frame refreshing signal arrives
Time will carry out mass data exchange, therefore need the careful planning part sequential, sufficiently be emulated, avoid race hazard from showing
The generation of elephant.
As it was noted above, unit inside counting device should be identical with the digit of displacement latch.Digit N should be by target frame
The horizontal M of the peak count rate of refresh rate Fr and pixel cell is determined, i.e., should cause：2NFr>M, i.e. N>log2(M/Fr).Count
Depth should take round up integer or the increase by 1 of the minimum value, and deeper counting depth would be impossible to be used, and meaningless drop
Low frame refresh rate index.Preferably, counter depth can contemplate be designed to it is optional, then can be under different counting rate levels
Obtain highest frame refresh rate index.
The laying out pattern of unit digital circuit needs careful planning, avoids digital circuit from producing string to analog circuit when overturning
Disturb.Preferably, by working frequency the partial circuit can be made mutually remote with analog circuit successively from low to high, so as to increase with spirit
The physical isolation of quick analog circuit.Should generally have latch, counter, shift register working frequency successively from low to high
Distribution.
The input and output of the shift register chain of adjacent pixel will be sequentially connected with, generally according to row to distribution, so as to every
Row pixel forms a longer shift register chain.Because frame refresh rate is the same as the direct phase of number of pixels on every shift chain
Close, in the case where pel array scale is certain, in order to improve frame refresh rate level, preferably by pel array by row
It is divided into several independent groups, each group shares a shift chain, and the shift chain between different groups works independently of one another, so as to
Concurrency is added, shortens the length of shift chain.But can not unrestrictedly increase shift chain and line number, otherwise will take big
Measure chip pin resource.
The present embodiment for current single photon counting type pixel read the chip various product dead time is big, frame refresh rate can not
Meet to require, and because structure limitation is difficult the problem of further raising, a kind of pixel proposed reads chip, has height
Frame refresh rate, the pixel, which reads chip, to make frame refresh rate in current master on the premise of ensureing that other performance indications are constant
Flow and more than ten times are lifted on Product Level, and substantially reduce the dead time, while reduce the requirement to system clock frequency.Except this it
Outside, the radiation hardened design requirement of single example upset can also be taken into account, the design complexities of configuration register are reduced, very
In limited pixel unit circuit area, save as the space shared by the register circuit of bulk redundancy.
The foregoing is only a preferred embodiment of the present invention, not makees any formal limitation to the present invention；It is all
The those of ordinary skill of the industry can be shown in by specification accompanying drawing and described above and swimmingly implement the present invention；It is but all
Those skilled in the art without departing from the scope of the present invention, using disclosed above technology contents
The equivalent variations for a little variation, modification and evolution made, it is the equivalent embodiment of the present invention；It is meanwhile all according to the present invention
The variation, modification and evolution of any equivalent variations made to above example of substantial technological etc., still fall within the present invention's
Within the protection domain of technical scheme.
Pay attention to, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although being carried out by above example to the present invention
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
Other more equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (8)
- A kind of 1. pixel unit circuit, it is characterised in that including：One charge sensitive preamplifier, low noise amplification is carried out to the detector signal of pixel；One discriminator, for the detectable signal after progress low noise amplification to be compared with threshold value, useful signal is discriminated Do not judge；One counter chain, including N-bit counter, for carrying out counting statistics, wherein N to useful signal according to examination judged result For the integer more than 1；One shift register chain, including N-bit register, respectively the N-bit counter with the counter chain be connected, when frame refreshing believe After number arriving, the enumeration data in the N-bit counter of the counter chain is latched and is loaded onto the N positions of the shift register chain In register；One configuration register module, with the shift register chain link；The N of wherein described counter and the register by target frame refresh rate Fr and pixel cell the horizontal M of peak count rate It is determined that N ＞ log2(M/Fr)；When frame refreshing signal arrives, specifically include：When frame refreshing signal arrives in rising edge clock, the discriminator is shielded with the counter chain signal path, with It is blocked the counting statistics result of the previous frame in the counter chain；Since in first clock cycle subsequent clock falling edge：The configuration register module is changed into transparent latch shape State, the configuration information on the shift register chain are refreshed to configuration deposit corresponding to each in the configuration register module Device, the working condition as the next frame of pixel cell corresponding to the pixel unit circuit define；Since in second clock cycle the clock falling edge：The meter of the previous frame in the counter chain being blocked Number statistical result is loaded in the shift register chain；Since in the 3rd clock cycle the clock falling edge：The counting statistics result of the counter chain is clear Zero, while the block of the counter chain is released from.
- 2. pixel unit circuit as claimed in claim 1, it is characterised in that when frame refreshing signal arrives, specifically include：The configuration register module inputs the configuration information of next frame to the input of the shift register chain, while described Shift register chain exports the counting statistics result of previous frame from output end, the configuration information and the counting statistics result Do not pass through the shift register chain overlappingly.
- 3. pixel unit circuit as claimed in claim 1, it is characterised in that after the block of the counter chain is released from Also include：N-bit counter in the counter chain starts to carry out counting statistics to the useful signal for crossing threshold in a new frame, described The configuration information of a new frame inputs from the input of the shift register chain, while the enumeration data of previous frame is defeated from shift chain Go out end output, configuration data stream and enumeration data stream are just nonoverlapping to be flowed by shift chain.
- 4. pixel unit circuit as claimed in claim 1, it is characterised in that the charge sensitive preamplifier with it is described Between discriminator, in addition to shaping/amplification module, for the detectable signal after the progress low noise amplification further to be amplified Filtering；The discriminator, for the filtered detectable signal of amplification to be compared with threshold value, useful signal is discriminated Do not judge.
- 5. pixel unit circuit as claimed in claim 1, it is characterised in that the N is more than or equal to 4 and is less than or equal to 20 integer.
- 6. a kind of pixel reads chip, it is characterised in that including multiple pixel cell electricity as described in claim any one of 1-5 Road.
- 7. pixel as claimed in claim 6 reads chip, it is characterised in that including：The row pel array of 104 rows × 72；9 pixel unit circuits as described in claim any one of 1-5；The pixel that 104 rows × 72 arrange is included in each pixel unit circuit, pixel depth is 20.
- 8. pixel as claimed in claim 7 reads chip, it is characterised in that the frame refreshing frequency that the pixel reads chip is big In or equal to 1.2 KHzs, the clock frequency of the pixel reading chip is more than or equal to 20 megahertzs.
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| DE102018222118A1 (en) * | 2018-12-18 | 2020-06-18 | Robert Bosch Gmbh | CCD photodetector and associated method of operation |
| CN110579460B (en) * | 2019-10-14 | 2023-04-18 | 深圳大学 | Addressing scanning rapid fluorescence lifetime microscopic imaging system and method |
| CN110852981B (en) * | 2019-11-19 | 2023-08-22 | 中智科仪（北京）科技有限公司 | Single photon imaging image processing method |
| CN112188127B (en) * | 2020-09-29 | 2021-08-24 | 中国科学院高能物理研究所 | Method, device, medium and equipment for calibrating integral pixel array detector |
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