CN105099620B - Algebra switching system, assembling and decoding algorithm thereof and decoding algorithm of data packet - Google Patents
Algebra switching system, assembling and decoding algorithm thereof and decoding algorithm of data packet Download PDFInfo
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- CN105099620B CN105099620B CN201510298834.XA CN201510298834A CN105099620B CN 105099620 B CN105099620 B CN 105099620B CN 201510298834 A CN201510298834 A CN 201510298834A CN 105099620 B CN105099620 B CN 105099620B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0076—Distributed coding, e.g. network coding, involving channel coding
Abstract
The invention belongs to the technical field of communication, relates to the fields of algebraic exchange, network coding and the like, and particularly relates to an algebraic exchange system, an assembling and decoding algorithm thereof and a decoding algorithm of a data packet. The invention is a decoding algorithm in an algebraic switching (i.e. multipath self-routing) system with network coding function. It features that the lost cells in the switch fabric, which are caused by the contention of ports when the cells pass through the switch fabric, can be recovered according to the redundant information in the coded cells. The decoding function can reduce the loss rate of data packets in the exchange process, thereby achieving the aims of increasing the network throughput, improving the communication efficiency and the like.
Description
Technical Field
The invention belongs to the technical field of communication, and relates to the fields of algebraic exchange, network coding and the like, in particular to an algebraic exchange system, an assembling and decoding algorithm thereof and a decoding algorithm of a data packet.
Background
In recent years, with the rapid increase of the number of internet users, the network scale is continuously enlarged, the popularity of rich network applications, especially network video services, and the data traffic of the existing network is continuously and rapidly increased, which presents a great challenge to the router as an important hub for network interconnection. The expansion of Internet scale, the proliferation of network traffic and the continuous emergence of new network applications put new demands on network devices such as routers and the like. The high-performance router is required to have strong capability, good expansibility, and high stability, reliability and safety.
As far as now, high performance routers typically have the following characteristics:
the system has a high enough packet handling capacity to achieve a forwarding capacity of millions of packets per second (Mp/s);
distributed large capacity matrix switching fabric;
high density, multiport and its scalability;
hardware lookup routing tables;
comprehensive redundancy design, high reliability;
efficient QoS means to meet the customer requirements for different quality of service on different occasions.
The development of high performance routers to meet the demands of network technology is imminent. To improve the performance of routers and reduce the implementation costs, a number of switching fabrics have been proposed internationally, among which again a shared bus structure is attractive [1 ]]Shared Memory 2]Cross matrix (Crossbar) [4 ]]And the like. The shared bus architecture is easy to scale and easier to implement, but at a lower rate. Although the shared storage structure can reach a higher speed, the speed of the shared storage structure is still limited by the speed of a memory, and the performance bottleneck of the bandwidth of the memory is that when the number of ports is large, the bandwidth requirement of the memory is large, and the condition of large-scale expansion application cannot be met. The crossbar, which is the most typically used and most common switching fabric, is a simple space-division switch that arbitrarily interconnects N input ports and N output ports. When the number of ports N is small, the cross matrix is an ideal switching fabric for realizing non-blocking and self-routing. But the number of switching units required for this architecture is N2The hardware implementation complexity is O (N)2) When N is large, the cost becomes unacceptable and does not meet the requirement of large-scale expansion.
To construct a switching fabric suitable for large scale expansion, He Wei et al proposed a multipath self-routing switching fabric [3], which applies algebraic lattice theory to self-routing models, with the advantages of fully distributed self-routing, no internal buffering, no buffering delay, and no jitter [3 ]. Under the condition of ensuring to provide QoS, the method is suitable for large-scale expansion and well meets the requirements of users.
However, this structure has a certain packet loss caused by internal blocking, and this defect seriously hinders the development and application of the structure. The invention provides a multi-path routing switching system, which is added with a network coding module on the basis of the multi-path routing switching system, and designs a set of data exchange and coding algorithm to better realize each function of the multi-path routing switching system. The core of the method is that the loss rate of the data packet in the transmission process is reduced by encoding the data packet, adding effective redundant information and decoding and recovering lost information, thereby achieving the aims of increasing the network throughput, improving the communication quality and the like and reducing the cost of data retransmission.
Cited documents:
[1]Cheng T D,Franaszek P A,Georgiou C J,et al.Dynamic switchprotocols on a shared medium network:U.S.Patent 5,235,592[P].1993-8-10.11s.
[2]Andrade P,Cooperman M,Sieber R W.ATM shared memory switch withcontent addressing:U.S.Patent 5,513,134[P].1996-4-30.
[3]Hui Li,Wei He,Xi CHEN,Peng Yi,Binqiang Wang,“Multi-path Self-routing Switching Structure by Interconnection of Multistage SortingConcentrators”,IEEE CHINACOM2007，Aug.2007,Shanghai.
[4]B.Prabhakar，N.McKeown，R.Ahuja；“Multicast scheduling for input-queued switches”，IEEE J.Selected Areas Commun，vol.15，no.5，p855-866，1997.
disclosure of Invention
An algebraic exchange system with network coding function mainly comprises the following modules: n input ports (1-1-1, 1-1-N), a data preprocessing module (1-2), an encoding module (1-3), N VOQ scheduling modules (1-4-1,1-4-2, 1, 4-N), an algebraic exchange module (1-5), an assembling module (1-6-1, 6-N), a decoding module (1-7-1, 7-N), N output ports (1-8-1, 8-N); the modules cooperate with each other to complete the operations of cutting, encoding, exchanging, assembling, decoding and the like of the data packet in the system.
An assembly and decoding algorithm for an algebraic switching system with network coding capability, comprising: the data cells pass through an algebraic exchange module in a parallel form, an assembly module writes the parallel data cells into a parallel-serial cache firstly, then reads the serial data cells out of the parallel-serial cache, and then an input state machine in the assembly module respectively performs operations of cell header extraction, cell header identification, access address determination, storage in the assembly cache, data packet integrity judgment and the like; wherein, the data packet integrity judgment sends the judgment result to the output state machine; the function of assembly is mainly realized by an output state machine, and the receiving and query of a data packet integrity judgment structure, the taking of an integral packet or the discarding or decoding and the data packet output are respectively carried out; if the data packet is complete, decoding is not needed, and the data packet is directly sent to an output cache; if a data cell is lost in the data packet, the lost data cell can be decoded by combining the remaining data cell and the coding cell; if two or more packets are lost, the packet is discarded directly.
A decoding algorithm for data packets of an algebraic switching system with network coding, comprising: after the cell is switched, it may be lost, the cut cell is coded according to a certain rule in the data coding module, the newly generated coded cell and other original cells are sent to the VOQ module and the switching structure together, after the switching is finished, if the cell is lost, the original data information is recovered in the decoding module and the assembling module by a specific decoding algorithm, and the whole process is as shown in fig. 2 and fig. 3.
The decoding function of the invention can reduce the loss rate of the data packet in the exchange process, thereby achieving the aims of increasing the network throughput, improving the communication efficiency and the like.
Drawings
FIG. 1 is a diagram of an algebraic switching system with network coding.
Fig. 2 shows the processing procedure of the Packet1 in the system.
Figure 3 is a cell assembly and decoding scheme.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings.
The invention provides a coding algorithm suitable for algebraic exchange in an algebraic exchange system with a network coding function. The algorithm uses cell as unit to encode, and sends the encoded data to VOQ scheduling module and algebraic exchange structure, and finally recovers the original data packet in decoding and assembling module.
The structure of the entire network coding-based algebraic switching system involved in the present invention is shown in fig. 1. A standard IP packet enters from N input ports 11(1-1-1, 1-1-N), and in the data preprocessing module 12 (1-2), a synchronization control signal is added, and the packet is cut into data pieces with equal length and header control information is added. The black bold arrows in fig. 1 represent packets, i.e., standard ethernet packets; after the data packet enters the data preprocessing module 12, the gray thick arrow indicates the data slice after being cut, i.e. the cell; the thin grey arrows indicate the flow control, i.e. the data synchronization signal. The coding module 13(1-3) codes the cells, and the generated redundant information enters the subsequent module along with the original data packet. The N parallel VOQ modules 14(1-4-1, 1.., 1-4-N) shunt data according to output ports, and simultaneously send data packets to the switching fabric 15(1-5) according to a certain scheduling algorithm, where the switching fabric 15 is an algebraic switching module. In the assembling module 16 (1-6-1., 1-6-N), the system reassembles the cells belonging to the same data packet according to a certain sequence to recover the original data packet. Only when a cell loss is detected in the assembly process, the decoding module (1-7-1, 1-7-N) is started, and the lost cell is recovered through decoding. Output ports 18(1-8-1, 1.., 1-8-N) are used to output data packets.
With reference to fig. 3, the assembly module includes two functions: parallel-serial (3-1) and assembly output. The parallel-to-serial part (i.e. the parallel-to-serial state machine 31) serializes the data cells that have been processed by the switch: in the first half of the switching interval, parallel data cells are stored in the cell buffer 32(3-2), while cell headers are extracted, the validity of the cells is checked and placed in the cell header buffer 33(3-3), in the second half of the switching interval, the cells are read out in a serial manner, and control signals are added and sent to the assembly part together with the cell header buffer.
In the assembly output part, the input state machine carries out the operations of extracting the cell head, identifying the cell head, determining the access address, storing in the packet head buffer 34(3-4), judging the integrity of the data packet and the like, and because the data packet is cut into a plurality of cells, the data packet identification word and the data cell identification word allocated to each cell are stored in the cell head. After the cell header is extracted, the address of cell storage is determined according to the data packet identifier and the data cell identifier. After the data cells are stored in the data packet buffer 36(3-6), whether the data packet is complete or not is checked, and if the data packet is complete or incomplete and exceeds the maximum waiting time, the data packet integrity judgment result (including the data packet is complete, the data packet is lost, but the data packet can be decoded and recovered, and the data packet is lost, but the data packet cannot be decoded and recovered) is sent to the output state machine.
The function of assembly is mainly realized by an output decoding state machine 35(3-5), and the functions of receiving and inquiring, taking a complete packet or discarding or decoding and outputting a data packet are respectively carried out on a data packet complete judging structure. If the data packet is complete, decoding is not needed, and the data packet is directly sent to an output buffer 37 (3-7); if a cell is lost in the data packet, the lost data cell can be decoded by combining the remaining cell and the coding cell; if two or more packets are lost, the packet is directly discarded for exception handling, and the storage space is emptied.
Decoding is the inverse process of encoding, and the idea is as shown in fig. 2, Packet1 is composed of N cells, and after encoding, there are N +1 cells, if the nth Cell in Packet1 is lost in the process of switching, the decoding module is started to recover the lost data, and the decoding algorithm is that Cell _ N is Cell _1 ⊕ Cell _2 ⊕ … ⊕ Cell _ N-1 ⊕ Cell _ N +1 ⊕ … ⊕ Cell _ N + 1.
And finally, the output cache sends the assembled data packet to a network interface for output.
Specifically, fig. 2 shows that data Packet1 is first subjected to data preprocessing 21 to obtain cut cells 22, and then these cells are subjected to encoding operation 23 to obtain new cells 24, and then the new cells are processed by VOQ scheduler 25 and switching module 26 to complete assembling and decoding step 27.
The foregoing is a more detailed description of the present invention that is presented in conjunction with specific embodiments, and the practice of the invention is not to be considered limited to those descriptions. It will be apparent to those skilled in the art that a number of simple derivations or substitutions can be made without departing from the inventive concept.
Claims (3)
1. An algebraic exchange system with network coding function,
the system comprises the following modules: the system comprises N input ports, a data preprocessing module, an encoding module, N VOQ scheduling modules, an algebraic exchange module, an assembling module, a decoding module and N output ports;
the system is characterized in that the modules are mutually matched to finish the operations of cutting, coding, exchanging, assembling and decoding of a data packet in the system;
the N input ports are used for receiving IP data packets;
the data preprocessing module is used for cutting the IP data packet into data pieces with equal length and adding packet header control information;
the coding module is used for coding the cell;
the N VOQ scheduling modules are used for shunting data according to output ports and sending data packets to the algebraic exchange module according to a scheduling algorithm;
the assembling module is used for writing the parallel data cells into the parallel-serial buffer firstly, then reading the serial data cells from the parallel-serial buffer, and then an input state machine in the assembling module respectively carries out cell head extraction, cell head identification, access address determination, storage to the assembling buffer and data packet integrity judgment operation; wherein, the data packet integrity judgment sends the judgment result to the output state machine; the function of assembly is mainly realized by an output state machine, and the receiving and query of a data packet integrity judgment structure, the taking of an integral packet or the discarding or decoding and the data packet output are respectively carried out; if the data packet is complete, decoding is not needed, and the data packet is directly sent to an output cache; if a data cell is lost in the data packet, the lost data cell can be decoded by combining the remaining data cell and the coding cell; if two or more packets are lost, the packet is discarded directly.
2. A method for assembling and decoding an algebraic switching system with network coding capability,
the method comprises the following steps: the data cells pass through an algebraic exchange module in a parallel form, an assembly module writes the parallel data cells into a parallel-serial buffer firstly, then reads the serial data cells out of the parallel-serial buffer, and then an input state machine in the assembly module respectively carries out cell head extraction, cell head identification, access address determination, storage to the assembly buffer and data packet integrity judgment; wherein, the data packet integrity judgment sends the judgment result to the output state machine;
the function of assembly is mainly realized by an output state machine, and the receiving and query of a data packet integrity judgment structure, the taking of an integral packet or the discarding or decoding and the data packet output are respectively carried out; if the data packet is complete, decoding is not needed, and the data packet is directly sent to an output cache; if a data cell is lost in the data packet, the lost data cell can be decoded by combining the remaining data cell and the coding cell; if two or more packets are lost, the packet is discarded directly.
3. A method for decoding packets in an algebraic switching system with network coding, comprising: after the cell is exchanged, the cell may be lost, the cut cell is encoded according to a certain rule in the data encoding module, the newly generated encoded cell and other original cells are sent to the VOQ module and the exchange structure together, after the exchange is finished, if the cell is lost, the original data information is recovered in the decoding module and the assembling module through a specific decoding algorithm;
the decoding algorithm is that Cell _ N is Cell _1 ⊕ Cell _2 ⊕ … ⊕ Cell _ N-1 ⊕ Cell _ N +1 ⊕ … ⊕ Cell _ N + 1;
wherein the nth cell is a lost cell.
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