CN104917702A - Algebra commutation system with network encoding function and preprocessing algorithm of algebra commutation system - Google Patents
Algebra commutation system with network encoding function and preprocessing algorithm of algebra commutation system Download PDFInfo
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- CN104917702A CN104917702A CN201510299587.5A CN201510299587A CN104917702A CN 104917702 A CN104917702 A CN 104917702A CN 201510299587 A CN201510299587 A CN 201510299587A CN 104917702 A CN104917702 A CN 104917702A
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Abstract
The invention belongs to the communication technical field and relates to network encoding and algebra commutation, in particular to an algebra commutation system with a network encoding function and a preprocessing algorithm of the algebra commutation system. The algebra commutation system with the network encoding function comprises a data preprocessing module. The data preprocessing module is characterized in that the data preprocessing module is used to execute data encoding and decoding better and more fast in the system. According to the algebra commutation system with the network encoding function and the preprocessing algorithm of the algebra commutation system of the invention, the data are preprocessed before entering a encoding module, and a packet header is added for entered data, and a data packet is segmented into cells with fixed length, and the cells are transmitted to a scheduler and an encoder, and therefore, encoding and decoding processing processes can be greatly accelerated, and the throughput and communication efficiency of the system can be improved.
Description
Technical field
The invention belongs to communication technical field, relate to the scopes such as algebraically exchange and network code, be specifically related to a kind of algebraically switching system and the Preprocessing Algorithm thereof with network code function.
Background technology
Along with the development of the Internet is advanced by leaps and bounds, network technology has penetrated into the various aspects of human lives, and profound influence the working and learning mode of people.Expansion and the number of users of internet scale sharply increase, and network complexity is day by day obvious.The data traffic of existing network continues rapid growth, and this gives IP is that the Internet of core brings more and more serious technological challenge.Existing network is primarily of switching equipment and transmission equipment composition.Be at present that the core exchange capacity of the switching equipment of representative seriously lags behind the wide development of transmission line cassette tape with router, router has become the bottleneck that restriction network further develops.Meanwhile, Internet is based on TCP/IP architecture, and its network layer only provides the service of Best-Effort not provide service quality (QoS) to promise to undertake.Therefore, the key that the more efficient and switching fabric of guaranteed qos is the business making full use of existing transmittability and provide QoS to ensure for next generation network is worked out.
Cost is realized in order to the performance improving router also reduces, international and domesticly propose many switching fabrics, wherein noticeable again have shared bus structure [1], share and store (Shared Memory) [2], structures such as cross matrix (Crossbar) [4].
Shared bus structure is easy to expansion and also realizes than being easier to, but its speed is lower.Although share storage organization can reach higher speed, but its speed is still subject to the restriction of memory speed, its bandwidth of memory performance bottleneck makes when port number is more, and memory bandwidth requirements is comparatively large, can not meet the condition of extensive expanded application.Cross matrix is the most general switching fabric of most typical use, and it is a kind of simple space switching switch, N number of input port and N number of output port is interconnected arbitrarily.When port number N is less, cross matrix be a kind of realize clog-free, from the desirable switching fabric of route.But the quantity of the crosspoint that this structure needs is N
2, hardware implementing complexity is O (N
2), when n is large, its cost becomes unacceptable, is difficult to the requirement meeting extensive expansion.
Algebraically exchange be a kind of multipath from route switching structure [3], algebraically distributive lattice theory is applied to from route matrix by this structure, and this structure has completely distributed from route, without advantages [3] such as inner buffer, linear speed and non-jitters.Under guarantee provides the condition of QoS, be applicable to extensive expansion.But this structure can produce internal contention and external blocking, thus result in certain packet loss.In order to reduce packet loss and improve data throughput in the transmission, a kind of effective method is merged network code and algebraically switching fabric, utilizes network code to recover the packet lost, thus the packet loss of effective reduction system.The present invention is exactly for the preprocessing algorithms in the algebraically switching system of coding Network Based.
Citing document:
[1]Cheng T D,Franaszek P A,Georgiou C J,et al.Dynamic switch protocols on a shared medium network:U.S.Patent 5,235,592[P].1993-8-10.11s.
[2]Andrade P,Cooperman M,Sieber R W.ATM shared memory switch with content addressing:U.S.Patent 5,513,134[P].1996-4-30.
[3]Hui Li,Wei He,Xi CHEN,Peng Yi,Binqiang Wang,“Multi-path Self-routing Switching Structure by Interconnection of Multistage Sorting Concentrators”,IEEE CHINACOM2007，Aug.2007,Shanghai.
[4]B.Prabhakar，N.McKeown，R.Ahuja；“Multicast scheduling for input-queued switches”，IEEE J.Selected Areas Commun，vol.15，no.5，p855-866，1997.
Summary of the invention
A kind of algebraically switching system with network code function, mainly comprise with lower module: N number of input port (1-1-1, ..., 1-1-N), data preprocessing module (1-2), coding module (1-3), N number of VOQ scheduler module (1-4-1,1-4-2, ..., 1-4-N), algebraically Switching Module (1-5), Knockdown block (1-6-1, ..., 1-6-N), decoder module (1-7-1, ..., 1-7-N), N number of output port (1-8-1 ..., 1-8-N);
Above-mentioned modules has cooperatively interacted the operations such as packet cutting in systems in which, coding, exchange, assembling, decoding.
A kind of Preprocessing Algorithm with the algebraically switching system of network code function, comprise: from raw data packets, extract the port numbers that destination address and data enter, then according to length and the cell length of packet, judge that this packet is the need of cutting, the words of if desired cutting, calculate the number of the cell that will cut into and need the byte number of filling, and then all these information storage are cut into multiple cell to packet according to judgement above and result of calculation in the cell packet header (Fig. 2), the cell finally packet header being attached to each cutting sends to coding module below,
Contain various control information, coding module below in the cell packet header that pretreatment module produces, the information that switching fabric and decoder module all will comprise according to this packet header completes a series of function of specifying.
The present invention carried out preliminary treatment before data enter coding module, a packet header be with the addition of to the packet entered, and packet is carried out being cut into the fixing cell of length, and then be sent in scheduler and encoder, greatly accelerate the processing procedure of Code And Decode, thus improve throughput and the communication efficiency of system.
Accompanying drawing explanation
Fig. 1 is the algebraically switching system schematic diagram with network code function of embodiment one.
The data/address bus that Fig. 2 (a) is embodiment one and control bus form.
The header packet information that Fig. 2 (b) is embodiment one defines.
Embodiment
By reference to the accompanying drawings the present invention is described in further detail below by embodiment.
The present embodiment proposes the encryption algorithm that the applicable algebraically in a kind of algebraically switching system having network code function exchanges.This algorithm is encoded in units of cell, and the data after coding are sent in VOQ scheduler module device and algebraically switching fabric, finally in decoding and Knockdown block, recovers original packet.
The structure of the algebraically switching system of coding whole Network Based involved in the present embodiment as shown in Figure 1.The IP packet of standard is from N number of input port 11 (1-1-1, ..., 1-1-N) enter, 12 (1-2) in data preprocessing module, to synchronous control signal be added, and packet is cut into the equal data slice of length and adds packet header control information.In Fig. 1, the thick arrow of black represents package, i.e. the Ethernet data bag of standard; After packet enters data preprocessing module 12, the thick arrow of grey represents the data slice after being cut, i.e. cell; The thin arrow of grey represents Flow Control, i.e. data synchronizing signal.Coding module 13 (1-3) is to coding for information element, and the redundant information of generation enters post-module with raw data packets.N number of parallel VOQ module 14 (1-4-1 ..., 1-4-N) data are shunted according to output port, packet is sent into algebraically switching fabric 15 (1-5) by certain dispatching algorithm, algebraically switching fabric and algebraically Switching Module simultaneously.In Knockdown block 16 (1-6-1 ..., 1-6-N), the cell belonging to same packet re-assemblies by system in a certain order, recovers original packet.Only have when having monitored a cell loss concealment in assembling process, just can start decoder module (1-7-1 ..., 1-7-N), recover the cell of loss by decoding.Output port 18 (1-8-1 ..., 1-8-N) for exporting packet.
In data preprocessing module 12, conveniently data identification and process, first data preprocessing module 12 with the addition of to the data of input the synchronous control signal that bit wide is 2.When control bus signal is 2 ' b11, under expression present clock, the data synchronous with it are the initial sum packet header of whole packet; When control bus signal is 2 ' b00, represent that current sync data are the payload in original system input packet; When control bus signal is 2 ' b10, represent that current data is the end of whole packet.Assuming that the bit wide of the data/address bus of system is 64, so the form of packet is as shown in Fig. 2 (a).
After adding synchronous control signal, packet is divided into 2 steps in the process of data preprocessing module: the quantity 1) judging whether the cell of needs cutting and cutting according to the length of packet and the length of cell; 2) grouping is cut into cell also for each cell adds packet header.
In the 1st step, according to the length of the physical length of packet and the cell of predefined, first can judge that this packet is the need of cutting: if the length of packet is less than the length of cell, then do not need cutting, and need the slack byte of packet being filled some to make it the length that length equals a cell; If the length of packet is greater than cell length, then calculate the length of the slack byte of quantity and last cell needs filling needing the cell cut into.If the length of packet is the integral multiple of the length of cell just, then without the need to filling slack byte after cutting.Finally these information to be kept in the self-defined packet header of packet and data to be sent in the functional module of execution the 2nd step.
In the 2nd step, the operation that packet will launch cutting to packet, fill according to the information of the 1st step middle wrapping head.If packet without the need to cutting, then fills packet with the length that some slack bytes make it to reach cell, and upgrade header packet information according to the package head format of Fig. 2 (b); If packets need is cut, then first the payload of packet is cut into multiple cell in order, add the packet header shown in Fig. 2 (b) then to the beginning of each cell.
In the processing procedure of whole data, each step is shared out the work and helped one another, or extraction packet internal information generates self-defined packet header, or the information that the packet header utilizing prime to generate provides completes self predefined function.Self-defining packet header has played huge effect, and in the present invention, self-defined packet header comprises information such as grouping significant notation, coded markings, destination interface number etc., as shown in Fig. 2 (b), introduces the function in packet header and their information that comprises below in detail.
Grouping significant notation: for distinguishing effectively grouping and invalid cell, such header packet information is used in algebraically switching system, if there is contention, then invalid cell priority is lower, and the possibility that valid cell is lost is less.
Retain position: temporarily retain, supplement for the information after system extension.
Package tail cell marks: whether mark this cell in raw data packets is last cell.If so, then this information is 1, otherwise is 0.
Network code marks: this field is that coding module uses, and whether mark this cell is the cell that coding produces, for assemble and decoder module time, recovery raw data packets.
Grouping fills up several: a packet is cut into the fixing cell of length, if the length of this packet is not the integral multiple of cell length, then in the end need the invalid information filling up some in a cell, this packet header record needs the quantity of the invalid information of supplementing, and unit is byte.After recover raw data packets in assembling and decode procedure, abandon invalid information simultaneously.
Source of packets port and destination interface: for recording source address and the destination interface address of cell.
Total number packets: for the cell quantity received being compared with this header packet information in assembling process, judged whether cell loss concealment.
Packet identification number: for recording the position of cell in raw data packets, for assembling and decoder module.
Identification of data packets number: the cell of identical data packet identifier fits together, recovering can raw data packets.
Above content is in conjunction with concrete execution mode further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made.
Claims (2)
1. there is an algebraically switching system for network code function,
Mainly comprise with lower module: N number of input port, data preprocessing module, coding module, N number of VOQ scheduler module, algebraically Switching Module, Knockdown block, decoder module, N number of output port;
It is characterized in that, above-mentioned modules has cooperatively interacted the operations such as packet cutting in systems in which, coding, exchange, assembling, decoding.
2. there is a Preprocessing Algorithm for the algebraically switching system of network code function, it is characterized in that,
Comprise: from raw data packets, extract the port numbers that destination address and data enter, then according to length and the cell length of packet, judge that this packet is the need of cutting, the words of if desired cutting, calculate the number of the cell that will cut into and need the byte number of filling, and then all these information storage are cut into multiple cell to packet according to judgement above and result of calculation in a cell packet header, the cell finally packet header being attached to each cutting sends to coding module below.
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Cited By (3)
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| CN105262562A (en) * | 2015-09-07 | 2016-01-20 | 香港中文大学深圳研究院 | Preprocessing method for grouping and recombining algebraic exchange engine data packets |
| CN112100169A (en) * | 2020-08-05 | 2020-12-18 | 中科驭数（北京）科技有限公司 | Database interaction data encoding method and device |
| WO2021110056A1 (en) * | 2019-12-06 | 2021-06-10 | 中兴通讯股份有限公司 | Data processing method, apparatus and device and storage medium |
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| WO2021110056A1 (en) * | 2019-12-06 | 2021-06-10 | 中兴通讯股份有限公司 | Data processing method, apparatus and device and storage medium |
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