CN101141373A - One-station type buffering storage packet switching structure and method capable of vast scale parallel access - Google Patents
One-station type buffering storage packet switching structure and method capable of vast scale parallel access Download PDFInfo
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- CN101141373A CN101141373A CNA2006100624532A CN200610062453A CN101141373A CN 101141373 A CN101141373 A CN 101141373A CN A2006100624532 A CNA2006100624532 A CN A2006100624532A CN 200610062453 A CN200610062453 A CN 200610062453A CN 101141373 A CN101141373 A CN 101141373A
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Abstract
The present invention relates to a structure and a method for broadband packet exchange. The exchanging method stores all the packets arrived within the same frame to the different regions of a one step packet buffer area module in a way of real-time bit-stream and through an input exchange module; each packet stops on the selected specific area till leaving the buffer area through an output exchange module. The access to the memorizer where the packet buffer area exists is not realized through a storage bus, therefore, the large-scale parallel access and expansion can be supported.
Description
[technical field]
The present invention relates to a kind of Switching Module, particularly a kind of packet switching construction and control method are wherein divided into groups with pipeline system by come in and go out one-stop packet buffer in the memory of bit serial, and this buffering area allows large-scale parallel visit.
[background technology]
Buffer storage is commonly used in packet switching, to alleviate the packet loss that produces owing to packet collisions, for example has the grouping of same target address in gap at the same time.At this moment, about several different strategies of disposing of buffering of packets memory, as the output buffering, crosspoint buffering, and input buffering.Following discussion for convenience can be imagined a kind of representative form of grouping, i.e. (the having specific bit or byte number) of a fixed length, the data cell of being made up of an exchange head and load.The exchange head of grouping has provided destination address, and service quality (the QoS:Quality of Serivce) rank of grouping.For an empty grouping, exchange head and load are 0 Bit String.
Especially, the output buffering disposes a packet buffer for each OPADD, is called one " output buffer ".It in the output buffer packet queue.In general, in output buffering switching fabric, for each output buffer distributes an independent memory block, this piece is divided into the register of specifying number, grouping of each register-stored.On the other hand, the length of packet queue is dynamic change in the buffering area.When registers all in the output buffer was all occupied, other grouping of attempting to enter this buffering area got clogged.Even when other output buffer that is associated with other OPADD less than the time, the obstruction of an output buffer also may take place.
The shared buffer-stored pattern of switching fabric is dynamically shared a big register pond by allowing all packet queues (each formation is corresponding with an output), solves the problems referred to above.Such shared structure requires multiple source can visit common storage area, and an input port of input grouping is accepted in source-representation here.The direct realization of sort memory multiple access is by the time-division shared bus between the source, and for example, each input port transmits data in different time slots; The time division multiplexing of the input grouping from different input ports to bus realizes by a packet multiplexer.Therefore, the Bit Transmission Rate of bus and storage inlet is necessary for M times of single input rate, and M is total number of input here.They are generally 16,32, or 64 parallel bits, because the restriction of single line transfer bandwidth, each bit has independent transmission line.Corresponding therewith, packet multiplexer must carry out the serial parallel conversion of packet format.Symmetry, at output, a grouping demodulation multiplexer is by another parallel bit bus, grouping demultiplexing that will be from the shared buffer to the output port, and carry out the parallel-to-serial conversion of packet format.
The throughput of sharing the exchange of buffer-stored formula is to be stored the device bus width to limit, and this also is an aspect that possible go wrong.Therefore, for large numbers of broadbands I/O port, the scale of this shared buffer-stored pattern of switching fabric can not well be expanded in proportion.For the application of high-throughput, a kind of new-type shared buffer-stored switching fabric that can expand in proportion is very necessary.Simultaneously, if can save multiplexing, the demultiplexing of memory bus, the serial-parallel conversion, the cost of parallel serial conversion will have bigger advantage.
In field of packet switching, packet buffer of one " one-stop buffering area " expression makes that whenever a grouping has occupied certain zone, as a register in the buffering area, it just rests on this zone, leaves this Switching Module up to it.In packet switching, because real-time mobile buffering packets has high cost, one-stop buffering is very desirable.Main feature of the present invention relates to one-stop buffering area.
[summary of the invention]
In order to have overcome some limitation and the shortcoming of aforementioned device and composition, but one of purpose of the present invention is the method that has proposed a kind of one-stop buffer-stored packet switching construction of large-scale parallel visit, it uses a M * N PSM packet switching module, and M the input that arrives in series of frames each frame time in the time with exchange is grouped into N output port.This method comprises: M input of a. exchange is grouped into B the M in the output, with in each time frame, produces M exchange grouping; B. in each time frame, exchange packet memory in M available register, to generate M stores packets with M; C. in each frame time, according to the destination address that is included in each stores packets, from being grouped into output port by maximum N of transmission the register that occupies.And in each frame time, from B register, transmit N
1The individual N that is grouped into
2The individual output port of representing with the formation identifier must satisfy condition N between parameter
1≤ N
2≤ N.
Method of the present invention, also comprise following operating process: (a) before M input grouping of each frame time arrives, M available register of selection in the packet buffer that comprises B register (B＞M), to be stored in M the grouping that arrives in the next frame time; (b), be grouped into M available register with M input of exchange for input module connects; (c) address with M available register is sent to the header memory; (d) use the connection that input module is set up, M input grouping transmitted and store in M the available register; (e) head with M input grouping is sent in the header memory.And, the register address of stores packets is sent in N the formation according to the destination address of M input packets headers; (f) header that provides according to the header memory upgrades formation; (g) register finder that sends control information, with in each time frame, the destination address that M input of notice register finder divided into groups; (h) according to the formation content, for each destination address is selected 1 stores packets in the packet buffer at most; (i) maximum N stores packets will selecting are sent to output, and upgrade register finder, to handle the residue destination address of each stores packets; (j) in next or a plurality of backward time frames, transmit remaining stores packets to N output, to empty the residue stores packets.
Another object of the present invention is to have realized a kind of M * N PSM packet switching module, be used for exchanging M the input that in each time frame of series of frames time, arrives and be grouped into N output port, this PSM packet switching module comprises: (a) input exchanging module that M * exchange of B cross type constitutes, B＞M, be used for exchanging M input and be grouped into B M that exports, in each time frame, to produce M exchange grouping; (b) one-stop shared buffer storage comprises B the register that the input exchanging module that constitutes with cross type exchange is coupled, be used in each frame time, with M exchange packet memory in the individual available register of M, with M stores packets of generation; (c) the output Switching Module that B * exchange of N cross type constitutes is coupled with packet buffer, is used in each frame time, according to the destination address of stores packets, from being grouped into output port by maximum N of transmission the register that occupies; (d) register finder is used in each frame time, selects M from B register, to produce the register of M appointment in B register; (e) M stature information-storing device exchanges the input exchanging module that constitutes with cross type and is coupled, and is used to store the header of M input grouping in each frame time, and is this M the address of importing M specified register of grouping; (f) N formation, in each frame time, M stature information-storing device will be sent in this N formation for the register address that these groupings are distributed according to the destination address in the packets headers information.And in this PSM packet switching module, each in B register is circulating register; Wherein header memory, register finder in addition, and link to each other by multi-user's bus between the formation.
Main feature of the present invention is: (1) is not to finish by memory bus to the visit of packet buffer place memory.A memory bus can only allow the once visit in the same time, and the mode that the present invention adopts allows large-scale concurrent access.(2) visit to memory does not need multiplexing and demultiplexing.Grouping flowing water is undertaken by the mode of serial data all the time, does not therefore need to carry out the serial-parallel conversion of packet format here.(3) structure with general is different, and the expansion of new construction of the present invention can not limited by bus bandwidth and bandwidth of memory.
[description of drawings]
Fig. 1 is the structured flowchart of PSM packet switching module of the present invention.
Fig. 2 A is the block diagram that enters the form of a grouping in the packet switching shown in Figure 1.Fig. 2 B is many data packet flows that will be exchanged by PSM packet switching module shown in Figure 1.
Fig. 3 is the structured flowchart of PSM packet switching module one embodiment of the present invention, has 3 input ports, 4 output ports, the packet buffer with 10 registers.
Fig. 4 is the structured flowchart of input module one embodiment among the present invention.
Fig. 5 is the structured flowchart of output module one embodiment among the present invention.
Fig. 6 is the block diagram of a register in the packet buffer among the present invention.
Fig. 7 is a process chart of the present invention.
For the ease of understanding, use identical reference numerals as far as possible for part identical among the different figure.
[embodiment]
The present invention is further elaborated below in conjunction with drawings and Examples.
1. overall structure
The block diagram 100 of Fig. 1 is a M * N PSM packet switching module consistent with the present invention (promptly one has M input, the Switching Module of N output).The packet transaction process is made up of following three switching parts: (a) packet buffer 106, and (b) input module 112, and (c) output module 114.
Four additional parts that are used to exchange control are arranged here: (a) the header memory 132 of M input, (b) formation 138 of N output, (c) register finder 134, (d) communication medium 140 that these control sections are linked to each other.These control sections link to each other in twos, and link to each other with above-mentioned three switching parts.
The relation of each part and other part will be discussed in more detail below.When describing these parts, grouping 200 among Fig. 2 A and the frame among Fig. 2 B will be quoted.Say that in essence a grouping is exactly a fixed-length data unit of being made up of serial data, by 204 and load 206 form.The exchange head has been indicated the QoS rank (reference numerals 202) of export target address (having reference numerals 201) and grouping.For an empty grouping, exchange head and load all are 0 Bit Strings.
Grouping appears at M input channel place of input 102 in the mode of synchronization frame.For instance, Fig. 2 B has described four independently stream of packets, and at frame t-1, t and t+1 (having reference numerals 211,212 and 213 respectively) are grouped in each appearance in 4 inputs.Be without loss of generality, suppose that the grouping among Fig. 2 A and the 2B is numbered in the following way: (t m) (sees Fig. 2 A, for the reference numerals 203 of any grouping) to P, and t refers to t time frame here, and m has specified input channel.For example, time frame 212 arrive input 102 the 3rd passage be grouped into P (t, 3); Similarly, frame 213 arrive input 102 the 4th passage be grouped into P (t+1,4).
For parallel stream of packets, frame synchronization is undertaken by frame commutator pulse sequence, 220-1 for example, 220-2,220-3,220-4.......In addition, a relevant bit clock signal flow 230 is arranged, the bit stream that passes PSM packet switching module 100 is carried out timing.Frame clock that pulse 220-1...... is represented and the relation between the bit clock signal 230 are shown in Fig. 2 B bottom.
In header memory set 132, M input respectively has a corresponding header memory.By connecting the communication medium 140 of control section 132,134 and 138, each memory in the header memory 132 receives a register address from register finder 134, and this address is to be this frame and the appointment of dividing into groups in advance.When some new groupings arrived Switching Modules, each header memory also received the new exchange that arrives grouping 204 from corresponding input; In detailed design, this reception can be undertaken by input module 112.Exchange 204 comprises the destination address and the QoS rank of grouping.After this, each the header memory in the header memory 132 is sent to formation 138 according to new each destination address that arrives grouping with register address and QoS rank.This transmission is to be undertaken by the communication medium in the control section 140.An empty grouping does not have destination address.
Each formation in the formation 138 all with N output in one corresponding.The formation of an appointment from the beginning stature information-storing device in the information-storing device 132 receives and corresponding new register address and its QoS rank that arrives grouping in this queue object address.At each frame time, each formation from the beginning in the information-storing device 132 each the header memory in the M stature information-storing device receive this type of information of maximum groupings, when identical a plurality of of destination address are grouped in when arriving in the same frame time, the register address of these groupings will enter with the corresponding formation of this destination address in.Generally speaking, the transmission of register address is to realize by the communication medium between the control section 140.Register address enter with the corresponding formation of each destination address of dividing into groups in, and the QoS rank is used to priority resolution in formation.Here it is emphasized that the register address of only preserving grouping in the formation, rather than grouping itself.In addition, special, if N
2Equate N with the number of non-empty queue in the frame time
1With this N
2The N of individual non-empty queue
2Different address numbers in the individual leading address equate in each frame time, N is arranged so
1Individual grouping is from being transferred to N by the register that occupies
2The individual OPADD that indicates by queue identifier, wherein N
1≤ N
2≤ N.
Register finder 134
Before the parallel stream of packets of input 102 arrives (for example for t frame, be duration) at (t-1) individual frame, an available register is selected in each grouping that register finder 134 arrives for M the input 102 by input module 112 in advance in packet buffer 106.When available the number of registers during less than M, register finder 134 may force to discharge the register that has been occupied, and is available to make it to become, and also may not adopt in such a way, takes which kind of mechanism then to depend on concrete design.Register finder 134 is sent to the address that is selected register in certain header memory in the header memory 132 also according to input 102; In detailed design, this transmission can be finished by input module 112.
The communication medium 140 that connects control section
The user of communication medium 140 is control sections, comprises header memory 132, formation 138, and register finder 134.The easy realization of communication medium is to use multi-user's bus, and different user can be sent to bus with data in the different time.
The example of structure 100
Fig. 3 has provided the example consistent with the present invention 3 * 4 Switching Modules, and 10 registers are arranged in the packet buffer 106.Consider the processing of a grouping, for example the 3rd of frame 212 the grouping P (t, 3) among Fig. 2 B.Before the grouping of frame 212 arrives, suppose that register finder 134 can be used for distributing at frame 211 definite registers 9, and register 9 will be as receiving the register of the 3rd grouping at next frame 212, and its identifier is transferred to header memory 332-3 at frame 211.When then new grouping arrives in frame 212, register finder 134 is by path 142, notice input module 112 is packet-switching to register 9 with the 3rd arrival, i.e. the bit clock 230 of frame 212 is adopted in the grouping that arrives at the passage 3 of input 302, deposits register 9 with the bit stream form.In addition, the head of this 3rd grouping is sent to header memory 332-3 by input module 112.The back will provide a brief description finishing this process.Attach, input module 112 can be 4 * 10 cross types exchange of a routine.
A determined destination address of supposing this 3rd grouping has only the output channel 1 in the output 310.So under the control of header memory 332-3, register address 9 and QoS information by communication medium 140 from the beginning information-storing device 332-3 be sent to formation 338-1, be the formation of handling output channel 1 in the formation 138.Further supposition QoS information has determined this 3rd grouping put into the head of formation 338-1, is the first term that register address 9 becomes this formation.This moment is for this 3rd grouping that enters in the register 9, because it, will become the next one grouping that is sent to output channel 1 via output module 310 from packet buffer 106 in the first term of formation 338-1.At frame 212, after formation 138 head of a quilt information-storing devices 132 filled up, which grouping register finder 134 follows the tracks of was ready to, thereby can be sent to output 310 in the next round operation of output module 114.Attach, output module 114 can be 10 * 3 cross types exchange of a routine.
Certain time point that the next round of output module 114 operates in the present frame 212 begins, and this time point may be positioned at grouping 3 and enter fully before the register 9.Register finder 134 is notified output modules 114 with the exchanged form between the input and output by path 144, so that transmit required grouping.In case setting completed for output module 114, promptly begin its next round operation, the content of register 9 begins to use bit clocks 230 by output module 114, is sent to output channel 1 in the mode of bit stream.Also synchronous by other grouping that the state and the register finder 134 of formation 138 are selected with grouping 3, pursue bit to output by output module 114.Register 9 becomes available now, can be grouped selector 134 at frame 213 and be reused for distribution.For grouping 3, may work as new being grouped in when frame 213 begins and enter in the register 9, still be in the process that withdraws from register 9.
By expanding top example, the destination address of supposing the 3rd grouping now is more than one, and might as well suppose has increased output 3 on the basis of output 1.Then at frame 212, header memory 332-3 will be with this information, will send formation 338-1 and 338-3 respectively to by register 9 canned datas together with input grouping 3.Supposing has a grouping with higher QoS priority in formation 338, make the 3rd grouping not to be transmitted when the next round operation of output module 114, and need be put off frame subsequently.During frame 212, the content of register 9 will be transmitted into the output channel of exporting in 310 1 by output module 114 under the control of register finder 134 so.Now, because the 3rd grouping also needs to be sent to output channel 3, register 9 can't be used to redistribute.If adjacent at 212, the three groupings of frame and formation 338-3, when frame 213, it is located in the head of formation so, thereby can be transmitted at frame 213.Finish in case transmit, register 9 just can be used for redistributing so.
The processing procedure of content can provide a kind of explanation by " allocation table " in 134 pairs of registers of register finder, and is as shown below.Table 1 has been represented a kind of situation, and before the output function of frame 212 was carried out, the destination address of the 3rd grouping is passage 1 and 3, and was as shown in table 1, and output 1 and 3 is marked as active.After this, suppose that before frame 212 finished, the content of register 9 had begun to send to passage 1, exports 1 like this and just can be marked as " removing ", as shown in table 2 as the example of expansion.At last, when register 9 after frame 213 begins its content sent to passage 3, output 3 can be marked as " removing ", this expression register 9 can be reallocated now.
| | Output | 1 | |
|
|
| 1 | |||||
| ... | |||||
| 9 | Enliven | Enliven | |||
| ... |
Table 1
| | Output | 1 | |
|
|
| 1 | |||||
| ... | |||||
| 9 | Remove | Enliven | |||
| ... |
Table 2
Operating process
By the utilization repeatedly based on the ordinary circumstance of last example, according to Fig. 1, in each frame time, each input 102 mode with serial bit stream of exchange receive a grouping, and the grouping that arrives in all inputs is synchronous.The processing procedure of a collection of grouping that arrives in same frame time comprises: at some setting operation of previous frame time, when grouping arrives, it is write packet buffer 106, and in follow-up frame time, these groupings are 110 routing operations from packet buffer 106 to destination address.These operating procedures are described below:
1. at the previous frame time of grouping arrival, register finder 134 is the available register of each selection in M the input in packet buffer 106.
2. register finder 134 is provided with the exchanged form of input module 112.Register finder 134 also according to input 102, is sent to the register address that has chosen in the header memory 132.
3. by path 141, the exchange of setting up input module 112 inside connects.
4.M individual grouping arrives PSM packet switching module 100.Wherein each grouping is written in the different registers in the packet buffer 106 all via input module 112.Simultaneously, exchange 204 input port 102 according to its arrival of each input grouping are sent in the corresponding header memory 132.
5. each the header memory in the header memory 132 all according to new each destination address that arrives grouping, is transferred to register address and QoS rank in the formation 138.Transmission is to finish by the communication medium 140 of connection control unit.
6. according to the information that receives, formation 138 is upgraded.
7. depend on concrete design, the information that header memory or formation will newly arrive grouping sends to register finder 134, so that it learns the destination address set of each new arrival grouping.
8. by path 144, for each destination address, select the buffering packets of corresponding non-empty queue head in the formation 138, and it is sent to output 110 by output module 114.
9. register finder 134 is upgraded in the residue destination address set of each the transmission grouping that is transmitted according to needs still.When a residual set that has transmitted grouping was combined into sky, the register address that register finder 134 will divide into groups was labeled as available, so that this register joins in the available register pond that can store following grouping.
This switching fabric designs at broadband application, finishes the exchange control that distributes by MPP.B parameter may be more many greatly than M and N.In addition, design is during controlling mechanism, should guarantee its time complexity be not directly and B proportional, but have littler ratio (as log
2B).
2. input module 112 specifies
Fig. 4 has provided a realization of input module 112, and by cross type exchange 405 formations of a M * B, the packet forward that is used for arriving is sent to packet buffer 106.After in importing for M each is selected available register, control signal from register finder 134 on the path 142 is used for a closed M crosspoint (this example has shown a determined closed crosspoint 411, the path, crosspoint that is illustrated by the broken lines, and it connects input channel 3 and register m).Other crosspoint in the cross type exchange is still out.In the head of one of input input grouping is written to corresponding header memory in the header memory 132 by a branch circuit 410, by path 116.
3. output module 114 specifies
Fig. 5 has provided a realization of output module 114, and this realizes adopting a B * N cross type exchange, and wherein the crosspoint is to be provided with by control path, crosspoint (dot, its reference numerals is 510).Control signal from register finder 134 on the path 144 is used for closed N crosspoint at most, is routed to (in this example, the crosspoint 511 that connects input channel 3 and output N-2 is closed) in the output 110 with a set with content of registers.Other crosspoint is still out in the cross type exchange.
4. packet buffer 106 specifies
As shown in Figure 6, an example register 600 in the packet buffer 106 is bit endless-chains, with bit storage device 600-1, and 600-2 ..., the mode of the shift register that 600-P forms realizes.By the bit of master clock definition in the time, all bits in the chain are displaced to the next bit position in the endless-chain at each.Multiplexer 603 is controlled by path 141 by register finder 134, to determine receiving newly arrived grouping (output of input module 112 is represented in such grouping) from passage 602, the buffering packets that still allows to have stored circulates so that be grouped in next time frame and still stay in the register.Shifted bits in the register also is sent to output module 114 by output 606, an input of expression output module 114.If begin to leave packet buffer 106 in the time frame that is grouped in its arrival, from the process of bit storage device 600-1 to 600-C, still can introduce delay so.For the 4th to 8 step of operating process, this delay is essential.
5. process chart
Fig. 7 has provided by PSM packet switching module 100 determined handling processes shown in Figure 1, is summarized as follows:
Step 705: before the grouping of next frame arrives, select the available register in the packet buffer 106, to be stored in the grouping that arrives in the next frame.
Step 710: by register finder 134 input module 112 is set, and the address transfer that will be used to store the register that will arrive grouping is given header memory 132.
Step 715: determine exchange for input module 112 and connect (for example crosspoint).
Step 720: the packet memory that will enter from input module 112 and sends to header memory 132 with packets headers to the register that has distributed.
Step 725: according to the destination address of packets headers, with register address and header (for example QoS) from the beginning information-storing device 132 be transferred in the formation 138.
Step 730: the register address and the header (QoS) that receive according to information-storing device 132 from the beginning upgrade formation 138.
Step 735: the register controller 134 that sends control information, with the destination address notice register controller of arrive grouping.
Step 740:, from packet buffer 106,, these groupings of selecting are sent to output 110 by output module 114 for each destination address is elected to many buffering packets according to the content of formation 138.
Step 745: according to the residue destination address of each stores packets, upgrade register finder 134, after the transmission of all destination addresses of stores packets was all finished, the register that mark should grouping correspondence was available.
Although provided detailed description of the present invention herein, those skilled in the art can design many other various embodiments, so the description of front only is for principle of the present invention is described.And one of ordinary skill in the art can provide multiple different design arrangement, for these designs, although there is not explicit description herein, has still embodied principle of the present invention, does not break away from the scope and spirit that invention is protected.Furtherly, the example of all references and condition are just for better the present invention will be described on principle, so that the notion of the autgmentability that the easier understanding of reader principle of the present invention and inventor are proposed, the example of these particularity and condition are not to be restriction of the present invention.In addition, all here recitation, certain aspect of problem, the specializing of invention, and special case all are at the angle of 26S Proteasome Structure and Function equivalence.Such equivalence had both comprised current known equivalent, also comprised following equivalent, was any unit of finishing this function, no matter and structure.
For persons skilled in the art, the block diagram has here only provided the exemplary description that embodies the principle of the invention.
Claims (6)
1. M * N PSM packet switching module is used for exchanging M the input that arrives and is grouped into N output port in each time frame of series of frames time, it is characterized in that described PSM packet switching module comprises:
A. a M * B cross type exchanges the input exchanging module that constitutes, and B＞M is used for exchanging M input and is grouped into B M that exports, with M exchange grouping of generation in each time frame;
B. one-stop shared buffer storage comprises B the register that the input exchanging module that constitutes with the cross type exchange is coupled,, be used in each frame time, with M exchange packet memory in the individual available register of M, with M stores packets of generation;
C. the output Switching Module that B * exchange of N cross type constitutes is coupled with packet buffer, is used in each frame time, according to the destination address of stores packets, from being grouped into output port by maximum N of transmission the register that occupies;
D. a register finder is used in each frame time, selects M from B register, to produce the register of M appointment in B register;
E.M stature information-storing device exchanges the input exchanging module that constitutes with cross type and is coupled, and is used to store the header of M input grouping in each frame time, and is this M the address of importing M specified register of grouping;
F.N formation, in each frame time, M stature information-storing device will be sent in this N formation for the register address that these groupings are distributed according to the destination address in the packets headers information.
2. PSM packet switching module according to claim 1, wherein each in B register is circulating register.
3. PSM packet switching module according to claim 1, wherein header memory, register finder, and link to each other by multi-user's bus between the formation.
4. method, it uses a M * N PSM packet switching module, and M the input that arrives in series of frames each frame time in the time with exchange is grouped into N output port, it is characterized in that described method comprises:
A. exchange M input and be grouped into B the M in the output,, produce M exchange grouping with in each time frame;
B. in each time frame, exchange packet memory in M available register, to generate M stores packets with M;
C. in each frame time, according to the destination address that is included in each stores packets, from being grouped into output port by maximum N of transmission the register that occupies.
5. method according to claim 4, wherein hop is included in each frame time, transmits N from B register
1The individual N that is grouped into
2The individual output port of representing with the formation identifier, N
1≤ N
2≤ N.
6. method according to claim 4 is characterized in that comprising following operating process:
A. before M of each frame time input grouping arrives, (B＞M) is to be stored in M the grouping that arrives in the next frame time to select the individual available register of M in the packet buffer that comprises B register;
B. for input module connects, be grouped into M available register with M input of exchange;
C. the address with M available register is sent to the header memory;
D. use the connection that input module is set up, M input grouping transmitted and store in M the available register;
E. the head with M input grouping is sent in the header memory, and according to M the destination address of importing packets headers, and the register address of stores packets is sent in N the formation;
F. the header that provides according to the header memory upgrades formation;
G. the register finder that sends control information, with in each time frame, the destination address that M input of notice register finder divided into groups;
H. according to the formation content, for each destination address is selected 1 stores packets in the packet buffer at most;
I. maximum N stores packets will selecting are sent to output, and upgrade register finder, to handle the residue destination address of each stores packets;
J. in next or a plurality of backward time frames, transmit remaining stores packets to N output, to empty the residue stores packets.
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| CN108885573A (en) * | 2016-01-27 | 2018-11-23 | Wago管理有限责任公司 | Safety device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104917702A (en) * | 2015-06-03 | 2015-09-16 | 香港中文大学深圳研究院 | Algebra commutation system with network encoding function and preprocessing algorithm of algebra commutation system |
| CN104917702B (en) * | 2015-06-03 | 2020-04-28 | 香港中文大学深圳研究院 | Algebraic exchange system with network coding function and preprocessing algorithm thereof |
| CN108885573A (en) * | 2016-01-27 | 2018-11-23 | Wago管理有限责任公司 | Safety device |
| CN108885573B (en) * | 2016-01-27 | 2022-02-18 | Wago管理有限责任公司 | Safety device |
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