CN105097912A - Semiconductor device - Google Patents
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- CN105097912A CN105097912A CN201410172667.XA CN201410172667A CN105097912A CN 105097912 A CN105097912 A CN 105097912A CN 201410172667 A CN201410172667 A CN 201410172667A CN 105097912 A CN105097912 A CN 105097912A
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Abstract
The invention discloses a semiconductor device. The semiconductor device comprises an active region and a pseudo-active region. The pseudo-active region is located outside the active region, and is spaced from the active region. The pseudo-active region comprises a first pseudo-active region. The first pseudo-active region extends outside the active region to form a continuous strip. Compared with a semiconductor device of the same size, the semiconductor device provided by the invention has the advantages that due to the fact that an original blank region corresponding to the active region is cancelled, the first pseudo-active region which extends into the continuous strip can produce more stress on the active region; the requirement of the stress reinforcement semiconductor device is met; and the performance of the semiconductor device is improved.
Description
Technical field
The application relates to technical field of manufacturing semiconductors, in particular to the setting of a kind of active area of semiconductor device and pseudo-active area.
Background technology
In technical field of manufacturing semiconductors, along with the progress gradually of technology, characteristic size (criticaldimension is called for short CD) becomes more and more less, and pseudo-pattern (patterndummy) becomes more and more important.
For the semiconductor device of the prior art shown in Fig. 1, in FIG, active area 1 ' (activearea, be called for short AA) devices function region is provided with grid 2 ' (GT), the relative both sides of grid 2 ' are furnished with multiple dummy grid 3 ' (DummyGT) respectively.Have multiple pseudo-active area 4 ' (AADummy) in active area 1 ' arranged outside, interval, multiple pseudo-active area 4 ' is arranged and is looped around the surrounding in source region 1 '.Pseudo-active area 4 ' and dummy grid 3 ' all belong to the one in pseudo-pattern.
Each pseudo-active area 4 ' of the prior art is generally very little square or rectangle, be the stress (stress) that active area 1 ' provides required for the formation of stressor layers, the distortion phenomenon of the active area 1 ' of semiconductor device (MOS) can be improved and improve chemico-mechanical polishing (CMP) effect of active area 1 '.Especially for the semiconductor device of below 45nm, stress has increasing impact for the performance of semiconductor device, and therefore how the pseudo-active area 4 ' of appropriate design becomes an important problem.
The defect that the pseudo-active area 4 ' of this spaced apart fritter of the prior art exists is: at the bearing of trend perpendicular to grid 2 ', the relative both sides of active area 1 ' are respectively arranged with five pseudo-active areas 4 ', and in five pseudo-active areas 4 ' of every side, only have the pseudo-active area 4 ', three, centre corresponding to active area 1 ' mainly to produce stress to active area 1 ', remaining two pseudo-active areas 4 ' can not produce stress to active area 1 ' substantially; And middle three pseudo-active areas 4 ' are for arranging at interval, the white space often formed between adjacent two pseudo-active areas 4 ' can not produce stress to active area 1 ', and the stress so just making the pseudo-active area 4 ' of this side produce is in the requirement that can not reach active area 1 ' in some cases.
Same, at the bearing of trend along grid 2 ', the relative both sides of active area 1 ' are respectively arranged with six pseudo-active areas 4 ', and although six pseudo-active areas 4 ' of every side all correspond to active area 1 ' layout, but the white space often formed between adjacent two pseudo-active areas 4 ' can not produce stress to active area 1 ', and the stress making the pseudo-active area 4 ' of this side produce is in the requirement that can not reach active area 1 ' in some cases.
Certainly, the number of the pseudo-active area 4 ' shown in Fig. 1 and adjusting to some extent in actual applications with the corresponding relation of active area 1 ', namely the active area 1 ' of different size is corresponded to, at the bearing of trend perpendicular to grid 2 ', the relative both sides of active area 1 ' may be respectively arranged with the pseudo-active area 4 ' of other quantity, at the bearing of trend along grid 2 ', the relative both sides of active area 1 ' also may be respectively arranged with the pseudo-active area 4 ' of other quantity, and concrete quantity should design according to the size of active area 1 '.In any case but adjustment, the spaced apart pseudo-active area 4 ' of this bulk, owing to forming white space between any two, all can impact in the generation of counter stress, and existence can not reach the situation that the required stress in active area 1 ' requires.
Summary of the invention
The application aims to provide a kind of semiconductor device, can increase the stress produced active area, meet the needs of active area.
To achieve these goals, according to an aspect of the application, provide a kind of semiconductor device, comprising: active area; And pseudo-active area, pseudo-active area be positioned at active area outside and and interval, active area arrange; Pseudo-active area comprises the first pseudo-active area, and the first pseudo-active area extends to form continuous strip in the outside of active area.
Further, the first pseudo-active area is concordant with the opposite end of active area respectively along the opposite end of its bearing of trend.
Further, semiconductor device also comprises grid, and grid is arranged on the active area.
Further, the first pseudo-active area extends along the bearing of trend of grid.
Further, two the first pseudo-active areas are arranged in the relative both sides of active area along the bearing of trend perpendicular to grid.
Further, the bearing of trend of the first pseudo-active area is perpendicular to the bearing of trend of grid.
Further, two the first pseudo-active areas are arranged in the relative both sides of active area along the bearing of trend of grid.
Further, the first pseudo-active area has four, and the surrounding corresponding to active area is arranged.
Further, four the first intervals, pseudo-active area are arranged.
Further, four the first pseudo-active area head and the tail connect in turn.
Further, semiconductor device also comprises dummy grid, dummy grid and gate parallel.
Further, multiple dummy grid is arranged along the bearing of trend interval perpendicular to grid.
Further, pseudo-active area also comprises the second pseudo-active area, and the second interval, pseudo-active area is arranged in the relative both sides of the first pseudo-active area.
Further, pseudo-active area also comprises the 3rd pseudo-active area group, and the multiple 3rd pseudo-active areas in the 3rd pseudo-active area group are arranged along the bearing of trend interval perpendicular to the first pseudo-active area.
Further, two the 3rd pseudo-active area groups are arranged in the relative both sides of active area along the bearing of trend of the first pseudo-active area.
The technical scheme of application the application, semiconductor device includes source region and pseudo-active area, wherein pseudo-active area be positioned at active area outside and and interval, active area arrange, pseudo-active area comprises the first pseudo-active area, and this first pseudo-active area extends to form continuous strip in the outside of active area.Owing to being extend continuously and correspond to active area to arrange, compared to block structure of the prior art, the first pseudo-active area can increase the stress that produces active area to reach the requirement of active area.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the schematic diagram of the semiconductor device of prior art;
Fig. 2 shows the schematic diagram of the semiconductor device of first embodiment of the application;
Fig. 3 shows the schematic diagram of the semiconductor device of second embodiment of the application;
Fig. 4 shows the schematic diagram of the semiconductor device of the 3rd embodiment of the application; And
Fig. 5 shows the schematic diagram of the semiconductor device of the 4th embodiment of the application.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
As what introduce in background technology, the stress that the block spaced apart pseudo-active area of prior art existence produces is difficult to meet the technical problem of active area requirement in any case.For solving this technical problem, in the pseudo-active area 4 that arranged outside the application of active area 1 provides.Wherein pseudo-active area 4 and interval, active area 1 are arranged, and pseudo-active area 4 comprises the first pseudo-active area 41, pseudo-active area 41, first and extends to form continuous strip in the outside of active area 1.
For onesize semiconductor device, the first pseudo-active area 41 extending into continuous strip of the application is owing to eliminating the white space originally corresponding to active area 1, so more effect of stress can be produced on active area 1, meet the requirement of the reinforced semiconductor device of stress, improve the performance of semiconductor device.
Illustrative embodiments according to the application will be described in more detail below.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
Below in conjunction with the first embodiment shown in Fig. 2 to Fig. 5 to the 4th embodiment, further illustrate the semiconductor device that the application provides.
Fig. 2 shows the semiconductor device schematic diagram that the application's first embodiment provides.As shown in Figure 2, active area 1 is rectangular configuration, and active area 1 is provided with grid 2, and the relative both sides of grid 2 are respectively furnished with multiple dummy grid 3, each dummy grid 3 is parallel with grid 2, and multiple dummy grids 3 of every side are arranged along the bearing of trend interval perpendicular to grid 2.Pseudo-active area 4 be positioned at active area 1 outside and and interval, active area 1 arrange, pseudo-active area 4 comprises the first pseudo-active area 41, first pseudo-active area 41 extends to form continuous strip in the outside of active area 1, and the bearing of trend of the first pseudo-active area 41 is parallel to the bearing of trend of grid 2.First pseudo-active area 41 of the continuous strip of this bearing of trend, for providing the stress of the bearing of trend perpendicular to grid 2 for active area 1, meets the stress requirement of active area 1 on the bearing of trend perpendicular to grid 2.
Preferably, multiple dummy grids 3 uniform intervals being positioned at the every side of grid 2 is arranged, and arranged direction is perpendicular to the bearing of trend of grid 2.
Preferably, first pseudo-active area 41 is concordant with the opposite end of active area 1 respectively along the opposite end of its bearing of trend, in the present embodiment, the top edge being embodied as the first pseudo-active area 41 is concordant with the top edge of active area 1, and the lower limb of the first pseudo-active area 41 is concordant with the lower limb of active area 1.This setup is used for the first pseudo-active area 41 is aligned with active area 1, and the stress that the first pseudo-active area 41 produces acts on active area 1 completely.Certainly, the top edge of the first pseudo-active area 41 and lower limb also can exceed top edge and the lower limb setting of active area 1, can produce the enough stress required for active area 1 equally; Or according to actual needs, also can be that top edge or the lower limb of the first pseudo-active area 41 is concordant with the corresponding edge of pseudo-active area 1, the corresponding edge of Bu Yuwei active area, another edge 1 be concordant; Under the prerequisite meeting active area 1 stress requirement, the top edge of the first pseudo-active area 41 and lower limb also can between the top edges of active area 1 and lower limb.As long as the strip of this continuous extension, just can produce compared to the more stress of prior art to meet active area 1 requirement.
Preferably, two the first pseudo-active areas 41 are arranged in the left and right sides of active area 1, its arranged direction, perpendicular to the bearing of trend of grid 2, makes two the first pseudo-active areas 41 can give the stress of the bearing of trend of active area 1 perpendicular to grid 2 from relative both direction.This arrangement is for making stress suffered by active area 1 more average, and active area 1 one lateral stress avoiding the pseudo-active area of single-sided arrangement first 41 to cause is comparatively large and problem that opposite side stress is less.
Although according to Fig. 2 display, all dummy grids 3 are all arranged on active area 1, do not mean that dummy grid 3 only has this kind of arrangement.In fact, in actual applications, according to varying in size of active area 1, dummy grid 3 can be arranged on active area 1, also can be arranged in outside active area 1.
As shown in Figure 2, respectively the second pseudo-active area 42 can also be set at interval in the upper side and lower side of the first pseudo-active area 41, second pseudo-active area 42 can produce along the component of stress of the bearing of trend of grid 2 and along the component of stress perpendicular to the bearing of trend of grid 2, these two kinds of components of stress some can act on active area 1, the stress produced with the first pseudo-active area 41 matches, and strengthens the stress produced active area 1 further.
As shown in Figure 2, pseudo-active area 4 can also comprise the 3rd pseudo-active area group 43,3rd pseudo-active area group 43 comprises multiple 3rd pseudo-active area 431, and multiple 3rd pseudo-active area 431 is arranged perpendicular to the bearing of trend interval of grid 2, and the bearing of trend interval namely perpendicular to the first pseudo-active area 41 is arranged.3rd pseudo-active area group 43 of this arrangement is for providing the stress of the bearing of trend along grid 2 for active area 1.Owing to there is white space between the multiple 3rd pseudo-active areas 431 in the 3rd pseudo-active area group 43, so the stress that the 3rd pseudo-active area group 43 produces weakens to some extent compared to the first pseudo-active area 41, and then the arrangement of this first pseudo-active area 41 shown in Fig. 2 and the 3rd pseudo-active area group 43 is applicable to require that the bearing of trend perpendicular to grid 2 increases stress, and do not require at the bearing of trend of grid 2 active area 1 increasing stress.
Preferably, two the 3rd pseudo-active area groups 43 are arranged in the both sides up and down of active area 1 along the bearing of trend of the first pseudo-active area 41, give the stress of the bearing of trend of active area 1 along grid 2 from relative both direction.This arrangement is for making stress suffered by active area 1 more average, and active area 1 one lateral stress avoiding single-sided arrangement the 3rd pseudo-active area group 43 to cause is comparatively large and problem that opposite side stress is less.
Shown in Fig. 2 first embodiment only shows the structure of semiconductor device in an illustrative manner, and the concrete quantity of the 3rd pseudo-active area 431 in the grid 2 shown in it, the pseudo-active area 42 of dummy grid 3, second and the 3rd pseudo-active area group 43 does not represent the restriction to the application.In actual applications, the grid 2 of respective numbers, the pseudo-active area 42 of dummy grid 3, second and the 3rd pseudo-active area 431 can be designed according to actual needs.
Because the extend into continuous strip first pseudo-active area 41 and spaced apart multiple 3rd pseudo-active area 431 can provide for active area 1 stress varied in size, so can select and arrange the first pseudo-active area 41 and the 3rd pseudo-active area group 43 according to active area 1 selectively in the stress demand of different directions, to meet the stress requirement of active area 1 at different directions.
Following second embodiment to the 4th embodiment only illustrates the change that these are selected and cloth is set up by way of example.
Fig. 3 shows the schematic diagram of the semiconductor device of second embodiment of the application.As shown in Figure 3, the in second embodiment first pseudo-active area 41 extends into continuous strip in the outside of active area 1, and the bearing of trend of the first pseudo-active area 41 is perpendicular to the bearing of trend of grid 2.First pseudo-active area 41 of this bearing of trend, for providing the stress of the bearing of trend along grid 2 for active area 1, meets the stress requirement of active area 1 on the bearing of trend along grid 2.
Preferably, first pseudo-active area 41 is concordant with the opposite end of active area 1 respectively along the opposite end of its bearing of trend, in the present embodiment, the left hand edge being embodied as the first pseudo-active area 41 is concordant with the left hand edge of active area 1, and the right hand edge of the first pseudo-active area 41 is concordant with the right hand edge of active area 1.This setup is used for the first pseudo-active area 41 is aligned with active area 1, and the stress that the first pseudo-active area 41 produces acts on active area 1 completely.Certainly, the left hand edge of the first pseudo-active area 41 and right hand edge also can exceed left hand edge and the right hand edge setting of active area 1, can produce the enough stress required for active area 1 equally; Or according to actual needs, also can be that left hand edge or the right hand edge of the first pseudo-active area 41 is concordant with the corresponding edge of pseudo-active area 1, the corresponding edge of Bu Yuwei active area, another edge 1 be concordant; Under the prerequisite meeting active area 1 stress requirement, the left hand edge of the first pseudo-active area 41 and right hand edge also can between the left hand edges of active area 1 and right hand edge.As long as the strip of this continuous extension, just can produce compared to the more stress of prior art to meet active area 1 requirement.
Preferably, two the first pseudo-active areas 41 are arranged in the both sides up and down of active area 1 along the bearing of trend of grid 2, give the stress of the bearing of trend of active area 1 along grid 2 from relative both direction.This arrangement is for making stress suffered by active area 1 more average, and active area 1 one lateral stress avoiding the pseudo-active area of single-sided arrangement first 41 to cause is comparatively large and problem that opposite side stress is less.
As shown in Figure 3, in second embodiment, the multiple 3rd pseudo-active areas 431 in each 3rd pseudo-active area group 43 are arranged along the bearing of trend interval of grid 2, namely arrange along the bearing of trend interval perpendicular to the first pseudo-active area 41.3rd pseudo-active area group 43 of this arrangement is for providing the stress of the bearing of trend perpendicular to grid 2 for active area 1.Owing to there is white space between the multiple 3rd pseudo-active areas 431 in the 3rd pseudo-active area group 43, so the stress that the 3rd pseudo-active area group 43 produces weakens to some extent compared to the first pseudo-active area 41 of continuous strip, and then the arrangement of this first pseudo-active area 41 shown in Fig. 3 and the 3rd pseudo-active area group 43 is applicable to require that the bearing of trend along grid 2 increases stress, and do not require at the bearing of trend perpendicular to grid 2 active area 1 increasing stress.
Preferably, two the 3rd pseudo-active area groups 43 are arranged in the left and right sides of active area 1, arranged direction, perpendicular to the bearing of trend of the first pseudo-active area 41, makes two the 3rd pseudo-active area groups 43 can give the stress of the bearing of trend of active area 1 perpendicular to grid 2 from relative both direction.This arrangement is for making stress suffered by active area 1 more average, and active area 1 one lateral stress avoiding single-sided arrangement the 3rd pseudo-active area group 43 to cause is comparatively large and problem that opposite side stress is less.
As shown in Figure 3, in the second embodiment, in order to avoid interfering with the 3rd pseudo-active area group 43, the second pseudo-active area 42 is not set in the left and right sides of the first pseudo-active area 41, but does not represent in second embodiment the second pseudo-active area 42 cannot be set.When the 3rd pseudo-active area group 43 dodges out the left and right sides of the first pseudo-active area 41, also the second pseudo-active area 42 can be set in the relative both sides of the first pseudo-active area 41, in order to produce along the component of stress of the bearing of trend of grid 2 and along the component of stress perpendicular to the bearing of trend of grid 2, increase the stress that active area 1 is produced further.
Shown in Fig. 3 second embodiment only shows the structure of semiconductor device in an illustrative manner, the concrete quantity of the 3rd pseudo-active area 431 in the grid 2 shown in it, dummy grid 3 and the 3rd pseudo-active area group 43 does not represent the restriction to the application, in actual applications, the grid 2 of respective numbers, dummy grid 3 and the 3rd pseudo-active area 431 can be designed according to actual needs.
In second embodiment, other unaccounted contents with reference to the related content of first embodiment, can not repeat them here, such as the arrangement of dummy grid 3.
Fig. 4 shows the schematic diagram of the semiconductor device of the 3rd embodiment of the application.As shown in Figure 4, the first pseudo-active area 41 in the 3rd embodiment has four, and four the first pseudo-active areas 41 are arranged corresponding to the surrounding of active area 1, and four the first intervals, pseudo-active area 41 are arranged.Each first pseudo-active area 41 all extends into continuous strip in the outside of active area 1, wherein two the first pseudo-active areas 41 are arranged in the left and right sides of active area 1, arranged direction is perpendicular to the bearing of trend of grid 2, each first pseudo-active area 41 in these two the first pseudo-active areas 41 all extends along the bearing of trend of grid 2, first pseudo-active area 41 of this bearing of trend, for providing the stress of the bearing of trend perpendicular to grid 2 for active area 1, meets the stress requirement of active area 1 on the bearing of trend perpendicular to grid 2.Two other first pseudo-active area 41 is arranged in the both sides up and down of active area 1 along the bearing of trend of grid 2, the bearing of trend of each first pseudo-active area 41 in these two the first pseudo-active areas 41 is all perpendicular to the bearing of trend of grid 2, first pseudo-active area 41 of this bearing of trend, for providing the stress of the bearing of trend along grid 2 for active area 1, meets the stress requirement of active area 1 on the bearing of trend along grid 2.
This two bearing of trends pseudo-active area 41 of continuous strip first arranged in conjunction can make active area 1 strengthening all to some extent along grid 2 bearing of trend with perpendicular to stress suffered by grid 2 bearing of trend, meets the stress requirement of active area 1.The 3rd pseudo-active area group 43 comprising multiple spaced apart 3rd pseudo-active area 431 is no longer set simultaneously.
Preferably, in four the first pseudo-active areas 41, the top edge of the first pseudo-active area 41 that the bearing of trend along grid 2 extends is concordant with the top edge of active area 1, and the lower limb of this first pseudo-active area 41 is concordant with the lower limb of active area 1.And the left hand edge of the first pseudo-active area 41 extended perpendicular to the bearing of trend of grid 2 is concordant with the left hand edge of active area 1, and the right hand edge of this first pseudo-active area 41 is concordant with the right hand edge of active area 1.This setup all can align to the corresponding side of active area 1 for making first of all directions the pseudo-active area 41, and the stress that the first pseudo-active area 41 produces acts on active area 1 completely.
As shown in Figure 4, in the 3rd embodiment, the both sides up and down of the first pseudo-active area 41 that the bearing of trend along grid 2 extends are provided with the second pseudo-active area 42, second pseudo-active area 42 and the first interval, pseudo-active area 41 are arranged, in order to produce along the component of stress of the bearing of trend of grid 2 and along the component of stress perpendicular to the bearing of trend of grid 2, these two kinds of components of stress some can act on active area 1, the stress produced with the first pseudo-active area 41 matches, and increases the stress produced active area 1 further.
Here in order to avoid interfering, second pseudo-active area 42 is not set in the left and right sides of the first pseudo-active area 41 of the bearing of trend perpendicular to grid 2, but the left and right sides not representing the first pseudo-active area 41 of the bearing of trend perpendicular to grid 2 cannot arrange the second pseudo-active area 42.In actual design, second pseudo-active area 42 can be arranged on the both sides up and down of the first pseudo-active area 41 that the bearing of trend along grid 2 extends as required, also the left and right sides of the first pseudo-active area 41 of the bearing of trend perpendicular to grid 2 can be arranged on, or when not producing interference, the relative both sides of four the first pseudo-active areas 41 all can arrange the second pseudo-active area 42, increase the stress produced active area 1 further.
In 3rd embodiment, other unaccounted contents with reference to the related content of first embodiment, can not repeat them here, the such as arrangement of dummy grid 3.
Fig. 5 shows the schematic diagram of the semiconductor device of the 4th embodiment of the application.As shown in Figure 5, the first pseudo-active area 41 in the 4th embodiment has four, and four the first pseudo-active areas 41 are arranged corresponding to the surrounding of active area 1, and between four the first pseudo-active areas 41, head and the tail are connected to form enclosed construction in turn.Each first pseudo-active area 41 all extends to form continuous strip in the outside of active area 1, wherein two the first pseudo-active areas 41 are arranged in the left and right sides of active area 1 perpendicular to the bearing of trend of grid 2, each first pseudo-active area 41 in these two the first pseudo-active areas 41 all extends along the bearing of trend of grid 2, first pseudo-active area 41 of this bearing of trend, for providing the stress of the bearing of trend perpendicular to grid 2 for active area 1, meets the stress requirement of active area 1 on the bearing of trend perpendicular to grid 2.Two other first pseudo-active area 41 is arranged in the both sides up and down of active area 1 along the bearing of trend of grid 2, the bearing of trend of each first pseudo-active area 41 in these two the first pseudo-active areas 41 is all perpendicular to the bearing of trend of grid 2, first pseudo-active area 41 of this bearing of trend, for providing the stress of the bearing of trend along grid 2 for active area 1, meets the stress requirement of active area 1 on the bearing of trend along grid 2.
This two bearing of trends pseudo-active area 41 of continuous strip first arranged in conjunction can make active area 1 strengthening all to some extent along grid 2 bearing of trend with perpendicular to stress suffered by grid 2 bearing of trend, meets the stress requirement of active area 1.The 3rd pseudo-active area group 43 comprising multiple spaced apart 3rd pseudo-active area 431 is no longer set simultaneously.
As shown in Figure 5, in the 4th embodiment, because four the first pseudo-active area 41 head and the tail connect in turn, so no longer arrange the second pseudo-active area 42, but rely on the junction of every two the first pseudo-active areas 41 to produce along the component of stress of the bearing of trend of grid 2 and along the component of stress perpendicular to the bearing of trend of grid 2, these two kinds of components of stress some can act on active area 1, the stress that the part corresponding to active area 1 with the first pseudo-active area 41 produces matches, for active area 1 provides required stress.
In 4th embodiment, other unaccounted contents with reference to the related content of first embodiment, can not repeat them here, the such as arrangement of dummy grid 3.
As can be seen from the above description, the application's the above embodiments achieve following technique effect:
First pseudo-active area extends to form continuous strip in the outside of active area, and owing to being extend continuously and correspond to active area to arrange, the first pseudo-active area can increase the stress that produces active area to reach the requirement of active area.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (15)
1. a semiconductor device, comprising:
Active area; And
Pseudo-active area, described pseudo-active area be positioned at described active area outside and and interval, described active area arrange;
It is characterized in that, described pseudo-active area comprises the first pseudo-active area, and described first pseudo-active area extends to form continuous strip in the outside of described active area.
2. semiconductor device according to claim 1, is characterized in that, described first pseudo-active area is concordant with the opposite end of described active area respectively along the opposite end of its bearing of trend.
3. semiconductor device according to claim 1, is characterized in that, described semiconductor device also comprises grid, and described grid is arranged on described active area.
4. semiconductor device according to claim 3, is characterized in that, described first pseudo-active area extends along the bearing of trend of described grid.
5. semiconductor device according to claim 4, is characterized in that, two described first pseudo-active areas are arranged in the relative both sides of described active area along the bearing of trend perpendicular to described grid.
6. semiconductor device according to claim 3, is characterized in that, the bearing of trend of described first pseudo-active area is perpendicular to the bearing of trend of described grid.
7. semiconductor device according to claim 6, is characterized in that, two described first pseudo-active areas are arranged in the relative both sides of described active area along the bearing of trend of described grid.
8. semiconductor device according to claim 3, is characterized in that, described first pseudo-active area has four, and the surrounding corresponding to described active area is arranged.
9. semiconductor device according to claim 8, is characterized in that, four described first intervals, pseudo-active area are arranged.
10. semiconductor device according to claim 8, is characterized in that, four described first pseudo-active area head and the tail connect in turn.
11. semiconductor device according to claim 3, is characterized in that, described semiconductor device also comprises dummy grid, described dummy grid and described gate parallel.
12. semiconductor device according to claim 11, is characterized in that, multiple described dummy grid is arranged along the bearing of trend interval perpendicular to described grid.
13. semiconductor device according to any one of claim 1 to 12, it is characterized in that, described pseudo-active area also comprises the second pseudo-active area, and described second interval, pseudo-active area is arranged in the relative both sides of described first pseudo-active area.
14. semiconductor device according to any one of claim 1 to 12, it is characterized in that, described pseudo-active area also comprises the 3rd pseudo-active area group, and the multiple 3rd pseudo-active areas in described 3rd pseudo-active area group are arranged along the bearing of trend interval perpendicular to described first pseudo-active area.
15. semiconductor device according to claim 14, is characterized in that, two described 3rd pseudo-active area groups are arranged in the relative both sides of described active area along the bearing of trend of described first pseudo-active area.
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| CN201410172667.XA CN105097912A (en) | 2014-04-25 | 2014-04-25 | Semiconductor device |
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| US20040238900A1 (en) * | 2003-05-29 | 2004-12-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device |
| US20060163665A1 (en) * | 2005-01-21 | 2006-07-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy patterns in integrated circuit fabrication |
| US20070057340A1 (en) * | 2005-09-13 | 2007-03-15 | Jung Myung J | Semiconductor device and method of fabricating thereof |
| CN104183490A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor forming method |
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Application publication date: 20151125 |