WO2018198600A1 - Electronic component - Google Patents

Electronic component Download PDF

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Publication number
WO2018198600A1
WO2018198600A1 PCT/JP2018/010973 JP2018010973W WO2018198600A1 WO 2018198600 A1 WO2018198600 A1 WO 2018198600A1 JP 2018010973 W JP2018010973 W JP 2018010973W WO 2018198600 A1 WO2018198600 A1 WO 2018198600A1
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WO
WIPO (PCT)
Prior art keywords
outer peripheral
peripheral surface
terminals
electronic component
disposed
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PCT/JP2018/010973
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French (fr)
Japanese (ja)
Inventor
智史 浅田
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株式会社村田製作所
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Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to TW107113730A priority Critical patent/TWI675386B/en
Publication of WO2018198600A1 publication Critical patent/WO2018198600A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors

Definitions

  • This disclosure relates to a rectangular parallelepiped electronic component.
  • Patent document 1 discloses a rectangular parallelepiped electronic component.
  • This electronic component includes first and second external electrodes disposed on first and second outer peripheral surfaces facing each other.
  • the first and second external electrodes are respectively disposed in regions facing each other on the first and second outer peripheral surfaces.
  • the opposing area between the electrodes increases, so the first and second external electrodes They may be capacitively coupled to each other, leading to isolation degradation (increase in signal leakage).
  • the degree of capacitive coupling between the electrodes is proportional to the opposing area between the electrodes and inversely proportional to the distance between the electrodes.
  • the present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide isolation in an electronic component including first and second external electrodes disposed on first and second outer peripheral surfaces facing each other. It is to suppress the deterioration.
  • An electronic component is a rectangular parallelepiped electronic component having a first outer peripheral surface and a second outer peripheral surface facing each other, and each includes a first portion disposed on the first outer peripheral surface. And a plurality of first external electrodes that do not have a second portion disposed on the second outer peripheral surface, and at least one second external electrode that has the second portion and does not have the first portion. At least a part of the first portion of each first external electrode is disposed in a region outside the region facing the second portion of the second external electrode on the first outer peripheral surface. At least a part of the second portion of the second external electrode is disposed in a region on the second outer peripheral surface that is out of any of the plurality of regions that respectively face the first portions of the plurality of first external electrodes.
  • each of the plurality of first external electrodes and the second external electrode are compared with the case where all of the first portions of the first external electrodes and all of the second portions of the second external electrodes are disposed in regions facing each other. Since the area facing the electrode is reduced, the degree of capacitive coupling between the first and second external electrodes can be reduced. As a result, it is possible to suppress deterioration of isolation in the electronic component including the first and second external electrodes disposed on the first and second outer peripheral surfaces facing each other.
  • the electronic component includes a plurality of second external electrodes. At least a part of the first portion of each first external electrode is arranged in a region on the first outer peripheral surface that is out of any of the plurality of regions that respectively face the second portions of the plurality of second external electrodes. At least a part of the second portion of each second external electrode is arranged in a region on the second outer peripheral surface that is out of any of the plurality of regions that respectively face the first portions of the plurality of first external electrodes.
  • the electronic component includes a plurality of first external electrodes and a plurality of second external electrodes, capacitive coupling between each of the plurality of first external electrodes and each of the plurality of second external electrodes is performed. Can be suppressed.
  • each first external electrode is from any of the plurality of regions respectively facing the second portions of the plurality of second external electrodes on the first outer peripheral surface. Arranged in the deviated area. All of the second portions of the respective second external electrodes are arranged in a region outside the plurality of regions respectively opposed to the first portions of the plurality of first external electrodes on the second outer peripheral surface.
  • each of the plurality of first external electrodes is compared with a case in which a part of the first part of each first external electrode and a part of the second part of each second external electrode are arranged in regions that do not face each other. Since the facing area with each of the plurality of second external electrodes is further reduced (becomes 0), the degree of capacitive coupling between the first and second external electrodes can be further reduced.
  • the electronic component is connected to a third outer peripheral surface connected to the first outer peripheral surface and the second outer peripheral surface, to the first outer peripheral surface and the second outer peripheral surface, and And a third outer peripheral surface opposite to the third outer peripheral surface.
  • the distance between the first outer peripheral surface and the second outer peripheral surface is shorter than the distance between the third outer peripheral surface and the fourth outer peripheral surface.
  • the distance between the first and second outer peripheral surfaces is shorter than the distance between the third and fourth outer peripheral surfaces, and the degree of capacitive coupling between the first and second external electrodes increases accordingly.
  • at least a part of the first part of each first external electrode and at least a part of the second part of the second external electrode are arranged in regions that do not face each other.
  • the electronic component includes a third external electrode having a third portion arranged on the third outer peripheral surface and a fourth external electrode having a fourth portion arranged on the fourth outer peripheral surface.
  • a third external electrode having a third portion arranged on the third outer peripheral surface and a fourth external electrode having a fourth portion arranged on the fourth outer peripheral surface.
  • At least a portion of the third portion of the third external electrode is disposed in a region outside the region facing the fourth portion of the fourth external electrode on the third outer peripheral surface.
  • At least a portion of the fourth portion of the fourth external electrode is disposed in a region outside the region facing the third portion of the third external electrode on the fourth outer peripheral surface.
  • At least a part of the third part of the third external electrode and at least a part of the fourth part of the fourth external electrode are also arranged in regions that do not face each other. Therefore, in addition to capacitive coupling between the first and second external electrodes, capacitive coupling between the third and fourth external electrodes can be suppressed.
  • the electronic component includes a third external electrode having a third portion disposed on the third outer peripheral surface, and a fourth external electrode having a fourth portion disposed on the fourth outer peripheral surface.
  • the third portion of the third external electrode is disposed in a region closer to the electrode having the greater distance from the third outer peripheral surface of the first external electrode and the second external electrode than the center of the third outer peripheral surface.
  • the fourth portion of the fourth external electrode is disposed in a region closer to the electrode having the greater distance from the fourth outer peripheral surface of the first external electrode and the second external electrode than the center of the fourth outer peripheral surface. .
  • the third portion of the third external electrode is closer to the electrode having the greater distance from the third outer peripheral surface of the first and second external electrodes than the center of the third outer peripheral surface. Placed in the area. Accordingly, the distance between the third external electrode and the electrode having the smaller distance between the third outer peripheral surface and the third external electrode is ensured as compared with the case where the third external electrode is arranged at the center of the third outer peripheral surface. Therefore, it is possible to suppress the deterioration of isolation between the electrode having the smaller distance between the third external electrode and the third outer peripheral surface.
  • the fourth portion of the fourth external electrode is disposed in a region closer to the electrode having the greater distance from the fourth outer peripheral surface of the first and second external electrodes than the center of the fourth outer peripheral surface.
  • FIG. 1 is an external perspective view of an electronic component 1 according to the present embodiment.
  • the electronic component 1 is formed in a rectangular parallelepiped shape by stacking a plurality of rectangular dielectrics.
  • the stacking direction of the dielectric (the height direction of the electronic component 1) is the Z-axis direction.
  • the long side (width) direction of the electronic component 1 is defined as the X-axis direction.
  • the short side (depth) direction of the electronic component 1 is defined as the Y-axis direction.
  • the X axis, the Y axis, and the Z axis are orthogonal to each other.
  • the electronic component 1 has a rectangular parallelepiped shape, and has six outer peripheral surfaces, that is, a top surface UF and a bottom surface BF that are parallel to the XY plane and face each other, and a first that is parallel to the ZX plane and faces each other. It has a side surface SA and a second side surface SB, and a third side surface SC and a fourth side surface SD that are parallel to the YZ plane and face each other.
  • the electronic component 1 includes terminals (external electrodes) P1 to P8 configured to be connectable to external devices.
  • Terminals P1 to P8 are an input port for inputting a high-frequency signal from an external device, an output port for outputting a high-frequency signal to an external device, a ground port terminated with a predetermined resistance value, and a ground port connected to a ground potential Used as such.
  • Each of the terminals P1 to P3 (first external electrode) is provided across the top surface UF, the first side surface SA, and the bottom surface BF.
  • Each of the terminals P4 to P6 (second external electrode) is provided across the top surface UF, the second side surface SB, and the bottom surface BF.
  • the terminal P7 (third external electrode) is provided across the top surface UF, the third side surface SC, and the bottom surface BF.
  • the terminal P8 (fourth external electrode) is provided across the top surface UF, the fourth side surface SD, and the bottom surface BF.
  • the shapes of the terminals P1 to P8 are substantially the same will be described, but the shapes of the terminals P1 to P8 are not necessarily the same.
  • some of the terminals P1 to P8 may have different X-axis widths than the remaining X-axis widths.
  • each of the terminals P1 to P8 may not have a portion arranged on at least one of the upper surface UF and the bottom surface BF. That is, each of the terminals P1 to P3 (first external electrode) has at least a portion disposed on the first side surface SA (more specifically, a portion extending from the upper side to the lower side of the first side surface SA). What is necessary is just to have no part arrange
  • the terminal P7 has at least a portion (more specifically, a portion extending from the upper side to the lower side in the third side surface SC) disposed on the third side surface SC, and is provided on the fourth side surface SD. What is necessary is just to have no part to be arranged.
  • the terminal P8 has at least a portion (more specifically, a portion extending from the upper side to the lower side in the fourth side surface SD) arranged on the fourth side surface SD, and is on the third side surface SC. What is necessary is just to have no part to be arranged.
  • a portion disposed on the first side surface SA of the terminal P1 “a portion disposed on the first side surface SA of the terminal P2”, and “a first side surface SA of the terminal P3”
  • the “placed portion” is also simply referred to as “terminal P1”, “terminal P2”, and “terminal P3”, respectively.
  • “Parts disposed on the second side surface SB of the terminal P4”, “parts disposed on the second side surface SB of the terminal P5”, and “portions disposed on the second side surface SB of the terminal P6” are simply referred to as “terminals”. Also referred to as “P4”, “terminal P5”, and “terminal P6”.
  • the “portion disposed on the third side surface SC of the terminal P7” and the “portion disposed on the fourth side surface SD of the terminal P8” are also simply referred to as “terminal P7” and “terminal P8”, respectively.
  • FIG. 2 is a cross-sectional view of the electronic component 1 cut along a plane parallel to the XY plane.
  • the distance between the first side surface SA and the second side surface SB facing each other is a length LY in the short side direction (Y-axis direction) of the electronic component 1.
  • the distance between the third side surface SC and the fourth side surface SD facing each other is the length LX in the long side direction (X-axis direction) of the electronic component 1.
  • regions where the terminals P1 to P3 are respectively projected onto the second side surface SB along the Y-axis direction are shown as facing regions 11 to 13 facing the terminals P1 to P3 on the second side surface SB, respectively.
  • regions where the terminals P4 to P6 are respectively projected on the first side surface SA along the Y-axis direction are shown as regions 14 to 16 facing the terminals P4 to P6 on the first side surface SA.
  • a region where the terminal P8 is projected on the third side surface SC along the X-axis direction is shown as a region 18 facing the terminal P8 on the third side surface SC.
  • a region where the terminal P7 is projected on the fourth side surface SD along the X-axis direction is shown as a region 17 facing the terminal P7 on the fourth side surface SD.
  • the terminals P1 to P3 are arranged on the first side surface SA.
  • the terminals P4 to P6 are disposed on the second side surface SB that faces the first side surface SA.
  • the terminal P7 is disposed on the third side surface SC.
  • the terminal P8 is disposed on the fourth side surface SD facing the third side surface SC.
  • the terminals P1 to P3 are respectively disposed in the facing regions 14 to 16 facing the terminals P4 to P6 on the first side surface SA, the facing area between each of the terminals P1 to P3 and each of the terminals P4 to P6 increases. For this reason, capacitive coupling occurs between the terminals facing each other, which may lead to deterioration of isolation.
  • the terminal P7 is disposed in the region 18 facing the terminal P8 on the third side surface SC, the opposing terminals P7 and P8 are capacitively coupled to each other, which may lead to deterioration of isolation.
  • the degree of capacitive coupling between the opposing terminals is proportional to the opposing area between the terminals and inversely proportional to the distance between the terminals.
  • the distance between the terminals (the length LY in the short side direction, or Since the length LX) in the long side direction is shortened and the capacitive coupling between the terminals is further increased, there is a concern that the isolation is further deteriorated.
  • the distance LY between the first side surface SA and the second side surface SB is shorter than the distance LX between the third side surface SC and the fourth side surface SD, and accordingly, the degree of capacitive coupling between the terminals P1 to P3 and the terminals P4 to P6. There is a concern that it will become larger.
  • the terminals P1 to P3 are arranged in a region that is out of any of the regions 14 to 16 facing the terminals P4 to P6 on the first side surface SA.
  • the terminals P4 to P6 are arranged in a region outside any of the regions 11 to 13 facing the terminals P1 to P3 on the second side surface SB.
  • terminals P1 to P3 first external electrodes
  • terminals P4 to P6 second external electrodes
  • the facing area between the terminals P1 to P3 and the terminals P4 to P6 becomes 0, the degree of capacitive coupling between each of the terminals P1 to P3 and each of the terminals P4 to P6 can be suppressed to a very small value.
  • the terminal P7 is arranged in a region outside the region 18 facing the terminal P8 on the third side surface SC.
  • the terminal P8 is disposed in a region outside the region 17 facing the terminal P7 on the fourth side surface SD. Therefore, in addition to the capacitive coupling degree between each of the terminals P1 to P3 and each of the terminals P4 to P6, capacitive coupling between the terminals P7 and P8 can be suppressed.
  • the terminal P7 is disposed in a region closer to the terminal P1 than the center CL3 on the third side surface SC.
  • the terminals P1 to P3 (first external electrode) and the terminals P4 to P6 (second external electrode) are arranged in regions that do not face each other, so that the third side surface SC and the terminal P4 (second external electrode) are arranged.
  • the distance to the electrode) is smaller than the distance between the third side surface SC and the terminal P1 (first external electrode).
  • the terminal P7 is disposed at the center CL3 on the third side surface SC, the distance between the terminal P7 and the terminal P4 cannot be secured, and there is a concern that the isolation between the terminal P7 and the terminal P4 deteriorates. . Therefore, in the present embodiment, the terminal P7 is disposed in a region closer to the terminal P1 having a larger distance from the third side SC of the terminals P1 and P4 than the center CL3 of the third side SC. The Thereby, the distance between the terminal P7 and the terminal P4 is ensured as compared with the case where the terminal P7 is arranged at the center CL3 on the third side surface SC. Therefore, it is possible to suppress the deterioration of isolation between the terminal P7 and the terminal P4.
  • the terminal P8 is connected to the terminal P6 having a larger distance from the terminal P3 and the fourth side surface SD among the terminals P6 than the center CL4 in the fourth side surface SD. Arranged in the near area. Thereby, the distance between the terminal P8 and the terminal P3 is ensured as compared with the case where the terminal P8 is arranged at the center CL4 in the fourth side surface SD. Therefore, it is possible to suppress the deterioration of isolation between the terminal P8 and the terminal P3.
  • the terminals P1 to P3 disposed on the first side surface SA and the terminals P4 to P6 disposed on the second side surface SB facing the first side surface SA are both. These are arranged so as not to face each other (the facing area becomes 0). Thereby, the capacitive coupling degree between each of the terminals P1 to P3 and each of the terminals P4 to P6 can be suppressed to a very small value.
  • the terminal P7 disposed on the third side surface SC and the terminal P8 disposed on the fourth side surface SD do not face each other (the facing area becomes 0). Placed in. Thereby, the capacitive coupling degree of the terminal P7 and the terminal P8 can also be suppressed to a very small value.
  • the terminals P7 and P8 are disposed on the third side surface SC and the fourth side surface SD, respectively, but may not include at least one of the terminals P7 and P8.
  • FIG. 3 is an example of a cross-sectional view when the electronic component 1A according to the first modification is cut along a plane parallel to the XY plane.
  • An electronic component 1A according to Modification 1 is obtained by removing the terminals P7 and P8 from the electronic component 1 according to the above-described embodiment.
  • terminals P1 to P3 and the terminals P4 to P6 are arranged so as not to face each other as in the electronic component 1 according to the present embodiment described above, each of the terminals P1 to P3 and the terminal The degree of capacitive coupling with each of P4 to P6 can be suppressed to a very small value.
  • each of the terminals P1 to P3 is disposed in a region that is out of any of the opposing regions 14 to 16, and only a part of each of the terminals P4 to P6 is from any of the opposing regions 11 to 13. May be arranged in a region outside.
  • FIG. 4 is an example of a cross-sectional view when the electronic component 1B according to Modification 2 is cut along a plane parallel to the XY plane.
  • the electronic component 1B according to the second modification differs from the electronic component 1 according to the above-described embodiment only in the arrangement of the terminals P1 to P6.
  • the terminals P1 are arranged in areas outside the opposing areas 14 to 16, but the remaining part is included in the opposing area 14 and the terminals P4 Is facing. Most of the terminal P4 is disposed in a region outside the facing regions 11 to 13, but the remaining part is included in the facing region 11 and faces the terminal P1.
  • the arrangement relationship between the terminals P2 and P5 and the arrangement relationship between the terminals P3 and P6 are the same as the arrangement relationship between the terminals P1 and P4.
  • all of the terminals P1 to P3 are all included in any of the opposing regions 14 to 16, and all of the terminals P4 to P6 are all included in any of the opposing regions 11 to 13.
  • the capacity of the capacitive coupling between the terminals P1 to P3 and the terminals P4 to P6 can be reduced.
  • the example in which the three terminals P1 to P3 are arranged on the first side surface SA and the three terminals P4 to P6 are arranged on the second side surface SB has been described.
  • the number of terminals arranged on the first side surface SA and the number of terminals arranged on the second side surface SB are not limited to three, and may be one or two. There may be four or more.
  • the terminals P1 to P3 disposed on the first side surface SA and the terminals P4 to P6 disposed on the second side surface SB are merely disposed so as not to face each other.
  • the terminal P7 arranged on the third side surface SC and the terminal P8 arranged on the fourth side surface SD are arranged so as not to face each other.
  • the terminal P7 disposed on the third side surface SC and the terminal P8 disposed on the fourth side surface SD may be disposed to face each other.
  • FIG. 5 is an example of a cross-sectional view when the electronic component 1C according to the third modification is cut along a plane parallel to the XY plane.
  • the electronic component 1C according to the third modification is obtained by removing the terminals P3, P5, and P6 from the electronic component 1 according to the above-described embodiment, and further changing the arrangement of the terminals P1, P2, P4, P7, and P8. is there.
  • the distance LY between the first side surface SA and the second side surface SB is shorter than the distance LX between the third side surface SC and the fourth side surface SD, and accordingly, the degree of capacitive coupling between the terminals P1, P2 and the terminal P4 is increased. Is concerned. Therefore, in the electronic component 1C according to the third modification, as shown in FIG. 5, the terminals P1 and P2 arranged on the first side surface SA are arranged in a region away from the facing region 14 and arranged on the second side surface SB.
  • the terminal P4 to be connected is disposed in a region outside the opposing regions 11 and 12. Thereby, the capacitive coupling degree between the terminals P1, P2 and the terminal P4 can be suppressed to a very small value.
  • the distance LX between the third side surface SC and the fourth side surface SD is longer than the distance LY between the first side surface SA and the second side surface SB, and even if the terminal P7 and the terminal P8 face each other, It is assumed that the capacitive coupling degree is a small value. Further, the third side surface SC and the fourth side surface SD are smaller in width than the first side surface SA and the second side surface SB, and the area where the terminals can be arranged is narrow.
  • the terminal P7 disposed on the third side surface SC is disposed in the facing region 18, and the terminal P8 disposed on the fourth side surface SD is opposed.
  • region 17 Arranged in region 17.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)

Abstract

An electronic component (1) is provided with: a plurality of terminals (P1-P3) disposed on a first side surface (SA); and a plurality of terminals (P4-P6) disposed on a second side surface (SB) opposite to the first side surface (SA). The plurality of terminals (P1-P3) disposed on the first side surface (SA) are located in a region of the first side surface (SA) other than all regions (14-16) opposite to the plurality of terminals (P4-P6) disposed on the second side surface (SB). The plurality of terminals (P4-P6) disposed on the second side surface (SB) are located in a region of the second side surface (SB) other than all regions (11-13) opposite to the plurality of terminals (P1-P3) disposed on the first side surface (SA).

Description

電子部品Electronic components
 本開示は、直方体状の電子部品に関する。 This disclosure relates to a rectangular parallelepiped electronic component.
 国際公開WO2012/124374号パンフレット(特許文献1)には、直方体状の電子部品が開示されている。この電子部品においては、互いに対向する第1、第2外周面にそれぞれ配置される第1、第2外部電極を備える。第1、第2外部電極は、第1、第2外周面における、互いに対向する領域にそれぞれ配置されている。 International publication WO2012 / 124374 pamphlet (patent document 1) discloses a rectangular parallelepiped electronic component. This electronic component includes first and second external electrodes disposed on first and second outer peripheral surfaces facing each other. The first and second external electrodes are respectively disposed in regions facing each other on the first and second outer peripheral surfaces.
国際公開WO2012/124374号パンフレットInternational Publication WO2012 / 124374 Pamphlet
 しかしながら、特許文献1に開示された電子部品のように、第1、第2外部電極が互いに対向する領域に配置されていると、電極同士の対向面積が大きくなるため第1、第2外部電極同士で容量結合してしまい、アイソレーションの劣化(信号漏れの増加)につながる恐れがある。特に、電極同士の容量結合度は電極同士の対向面積に比例し電極間の距離に反比例するところ、電子部品の小型化が進むと、電極間の距離(第1、第2外周面間の距離)が短くなり電極同士の容量結合度がさらに大きくなるため、アイソレーションがさらに劣化することが懸念される。 However, when the first and second external electrodes are arranged in regions facing each other as in the electronic component disclosed in Patent Document 1, the opposing area between the electrodes increases, so the first and second external electrodes They may be capacitively coupled to each other, leading to isolation degradation (increase in signal leakage). In particular, the degree of capacitive coupling between the electrodes is proportional to the opposing area between the electrodes and inversely proportional to the distance between the electrodes. As the electronic components become smaller, the distance between the electrodes (the distance between the first and second outer peripheral surfaces). ) Is shortened and the capacitive coupling between the electrodes is further increased, and there is a concern that the isolation may further deteriorate.
 本開示は上記の問題に鑑みてなされたものであって、その目的は、互いに対向する第1、第2外周面にそれぞれ配置される第1、第2外部電極を備える電子部品において、アイソレーションの劣化を抑制することである。 The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide isolation in an electronic component including first and second external electrodes disposed on first and second outer peripheral surfaces facing each other. It is to suppress the deterioration.
 (1) 本開示による電子部品は、互いに対向する第1外周面および第2外周面を有する直方体状の電子部品であって、各々が第1外周面上に配置される第1部分を有しかつ第2外周面上に配置される第2部分を有さない複数の第1外部電極と、第2部分を有しかつ第1部分を有さない少なくとも1つの第2外部電極とを備える。各第1外部電極の第1部分の少なくとも一部は、第1外周面における、第2外部電極の第2部分と対向する領域から外れた領域に配置される。第2外部電極の第2部分の少なくとも一部は、第2外周面における、複数の第1外部電極の第1部分にそれぞれ対向する複数の領域のいずれからも外れた領域に配置される。 (1) An electronic component according to the present disclosure is a rectangular parallelepiped electronic component having a first outer peripheral surface and a second outer peripheral surface facing each other, and each includes a first portion disposed on the first outer peripheral surface. And a plurality of first external electrodes that do not have a second portion disposed on the second outer peripheral surface, and at least one second external electrode that has the second portion and does not have the first portion. At least a part of the first portion of each first external electrode is disposed in a region outside the region facing the second portion of the second external electrode on the first outer peripheral surface. At least a part of the second portion of the second external electrode is disposed in a region on the second outer peripheral surface that is out of any of the plurality of regions that respectively face the first portions of the plurality of first external electrodes.
 上記構成によれば、各第1外部電極の第1部分の少なくとも一部および第2外部電極の第2部分の少なくとも一部は、互いに対向しない領域に配置される。そのため、各第1外部電極の第1部分の全部および第2外部電極の第2部分の全部が互いに対向する領域に配置される場合に比べて、複数の第1外部電極の各々と第2外部電極との対向面積が小さくなるため、第1、第2外部電極同士の容量結合度を小さくすることができる。その結果、互いに対向する第1、第2外周面にそれぞれ配置される第1、第2外部電極を備える電子部品において、アイソレーションの劣化を抑制することができる。 According to the above configuration, at least a part of the first part of each first external electrode and at least a part of the second part of the second external electrode are arranged in regions that do not face each other. Therefore, each of the plurality of first external electrodes and the second external electrode are compared with the case where all of the first portions of the first external electrodes and all of the second portions of the second external electrodes are disposed in regions facing each other. Since the area facing the electrode is reduced, the degree of capacitive coupling between the first and second external electrodes can be reduced. As a result, it is possible to suppress deterioration of isolation in the electronic component including the first and second external electrodes disposed on the first and second outer peripheral surfaces facing each other.
 (2) ある実施の形態においては、電子部品は、複数の第2外部電極を備える。各第1外部電極の第1部分の少なくとも一部は、第1外周面における、複数の第2外部電極の第2部分にそれぞれ対向する複数の領域のいずれからも外れた領域に配置される。各第2外部電極の第2部分の少なくとも一部は、第2外周面における、複数の第1外部電極の第1部分にそれぞれ対向する複数の領域のいずれからも外れた領域に配置される。 (2) In an embodiment, the electronic component includes a plurality of second external electrodes. At least a part of the first portion of each first external electrode is arranged in a region on the first outer peripheral surface that is out of any of the plurality of regions that respectively face the second portions of the plurality of second external electrodes. At least a part of the second portion of each second external electrode is arranged in a region on the second outer peripheral surface that is out of any of the plurality of regions that respectively face the first portions of the plurality of first external electrodes.
 上記構成によれば、電子部品が複数の第1外部電極および複数の第2外部電極を備える場合においても、複数の第1外部電極の各々と複数の第2外部電極の各々との容量結合を抑制することができる。 According to the above configuration, even when the electronic component includes a plurality of first external electrodes and a plurality of second external electrodes, capacitive coupling between each of the plurality of first external electrodes and each of the plurality of second external electrodes is performed. Can be suppressed.
 (3) ある実施の形態においては、各第1外部電極の第1部分の全部が、第1外周面における、複数の第2外部電極の第2部分にそれぞれ対向する複数の領域のいずれからも外れた領域に配置される。各第2外部電極の第2部分の全部が、第2外周面における、複数の第1外部電極の第1部分にそれぞれ対向する複数の領域のいずれからも外れた領域に配置される。 (3) In an embodiment, the entire first portion of each first external electrode is from any of the plurality of regions respectively facing the second portions of the plurality of second external electrodes on the first outer peripheral surface. Arranged in the deviated area. All of the second portions of the respective second external electrodes are arranged in a region outside the plurality of regions respectively opposed to the first portions of the plurality of first external electrodes on the second outer peripheral surface.
 上記構成によれば、各第1外部電極の第1部分の全部および各第2外部電極の第2部分の全部が、互いに対向しない領域に配置される。そのため、各第1外部電極の第1部分の一部および各第2外部電極の第2部分の一部が互いに対向しない領域に配置される場合に比べて、複数の第1外部電極の各々と複数の第2外部電極の各々との対向面積がさらに小さくなる(0になる)ため、第1、第2外部電極同士の容量結合度をより小さくすることができる。 According to the above configuration, all of the first portions of the first external electrodes and all of the second portions of the second external electrodes are arranged in regions that do not face each other. Therefore, each of the plurality of first external electrodes is compared with a case in which a part of the first part of each first external electrode and a part of the second part of each second external electrode are arranged in regions that do not face each other. Since the facing area with each of the plurality of second external electrodes is further reduced (becomes 0), the degree of capacitive coupling between the first and second external electrodes can be further reduced.
 (4) ある実施の形態においては、電子部品は、第1外周面と第2外周面とに接続される第3外周面と、第1外周面と第2外周面とに接続され、かつ第3外周面と対向する第4外周面とをさらに有する。第1外周面と第2外周面との距離は、第3外周面と第4外周面との距離よりも短い。 (4) In an embodiment, the electronic component is connected to a third outer peripheral surface connected to the first outer peripheral surface and the second outer peripheral surface, to the first outer peripheral surface and the second outer peripheral surface, and And a third outer peripheral surface opposite to the third outer peripheral surface. The distance between the first outer peripheral surface and the second outer peripheral surface is shorter than the distance between the third outer peripheral surface and the fourth outer peripheral surface.
 上記構成によれば、第1、第2外周面間の距離は第3、第4外周面間の距離よりも短く、その分、第1、第2外部電極間の容量結合度が大きくなることが懸念される。しかしながら、上記構成によれば、各第1外部電極の第1部分の少なくとも一部および第2外部電極の第2部分の少なくとも一部は互いに対向しない領域に配置される。これにより、複数の第1外部電極の各々と第2外部電極との対向面積が小さくなるため、第1、第2外部電極同士の容量結合度が大きくなることを抑制することができる。 According to the above configuration, the distance between the first and second outer peripheral surfaces is shorter than the distance between the third and fourth outer peripheral surfaces, and the degree of capacitive coupling between the first and second external electrodes increases accordingly. Is concerned. However, according to the above configuration, at least a part of the first part of each first external electrode and at least a part of the second part of the second external electrode are arranged in regions that do not face each other. Thereby, since the facing area between each of the plurality of first external electrodes and the second external electrode is reduced, it is possible to suppress an increase in the degree of capacitive coupling between the first and second external electrodes.
 (5) ある実施の形態においては、電子部品は、第3外周面に配置される第3部分を有する第3外部電極と、第4外周面に配置される第4部分を有する第4外部電極とを備える。第3外部電極の第3部分の少なくとも一部分は、第3外周面における、第4外部電極の第4部分と対向する領域から外れた領域に配置される。第4外部電極の第4部分の少なくとも一部分は、第4外周面における、第3外部電極の第3部分と対向する領域から外れた領域に配置される。 (5) In an embodiment, the electronic component includes a third external electrode having a third portion arranged on the third outer peripheral surface and a fourth external electrode having a fourth portion arranged on the fourth outer peripheral surface. With. At least a portion of the third portion of the third external electrode is disposed in a region outside the region facing the fourth portion of the fourth external electrode on the third outer peripheral surface. At least a portion of the fourth portion of the fourth external electrode is disposed in a region outside the region facing the third portion of the third external electrode on the fourth outer peripheral surface.
 上記構成によれば、第3外部電極の第3部分の少なくとも一部および第4外部電極の第4部分の少なくとも一部も、互いに対向しない領域に配置される。そのため、第1、第2外部電極同士の容量結合に加えて、第3、第4外部電極同士の容量結合をも抑制することができる。 According to the above configuration, at least a part of the third part of the third external electrode and at least a part of the fourth part of the fourth external electrode are also arranged in regions that do not face each other. Therefore, in addition to capacitive coupling between the first and second external electrodes, capacitive coupling between the third and fourth external electrodes can be suppressed.
 (6) ある実施の形態においては、電子部品は、第3外周面に配置される第3部分を有する第3外部電極と、第4外周面に配置される第4部分を有する第4外部電極とを備える。第3外部電極の第3部分は、第3外周面における中央よりも、第1外部電極および第2外部電極のうちの第3外周面との距離が大きい方の電極に近い領域に配置される。第4外部電極の第4部分は、第4外周面における中央よりも、第1外部電極および第2外部電極のうちの第4外周面との距離が大きい方の電極に近い領域に配置される。 (6) In an embodiment, the electronic component includes a third external electrode having a third portion disposed on the third outer peripheral surface, and a fourth external electrode having a fourth portion disposed on the fourth outer peripheral surface. With. The third portion of the third external electrode is disposed in a region closer to the electrode having the greater distance from the third outer peripheral surface of the first external electrode and the second external electrode than the center of the third outer peripheral surface. . The fourth portion of the fourth external electrode is disposed in a region closer to the electrode having the greater distance from the fourth outer peripheral surface of the first external electrode and the second external electrode than the center of the fourth outer peripheral surface. .
 上記構成によれば、第1、第2外部電極を互いに対向しない領域に配置したことによって、第3外周面と第1外部電極との距離と、第3外周面と第2外部電極と距離とが不均衡になることが想定される。そのため、仮に、第3外部電極を第3外周面における中央に配置すると、第3外部電極と、第1、第2外部電極のうちの第3外周面との距離が小さい方の電極との距離が確保されず、第3外部電極と上記第3外周面との距離が小さい方の電極との間でアイソレーションが劣化することが懸念される。 According to the above configuration, by arranging the first and second external electrodes in regions that do not face each other, the distance between the third outer peripheral surface and the first external electrode, the distance between the third outer peripheral surface and the second external electrode, Is assumed to be imbalanced. Therefore, if the third external electrode is disposed at the center of the third outer peripheral surface, the distance between the third external electrode and the electrode having the smaller distance between the third outer peripheral surface of the first and second external electrodes. Is not secured, and there is a concern that isolation may deteriorate between the third external electrode and the electrode having the smaller distance between the third outer peripheral surface and the third outer electrode.
 そこで、上記構成においては、第3外部電極の第3部分が、第3外周面における中央よりも、第1、第2外部電極のうちの第3外周面との距離が大きい方の電極に近い領域に配置される。これにより、第3外部電極を第3外周面における中央に配置する場合に比べて、第3外部電極と上記第3外周面との距離が小さい方の電極との距離が確保される。そのため、第3外部電極と上記第3外周面との距離が小さい方の電極との間でアイソレーションが劣化することを抑制することができる。 Therefore, in the above configuration, the third portion of the third external electrode is closer to the electrode having the greater distance from the third outer peripheral surface of the first and second external electrodes than the center of the third outer peripheral surface. Placed in the area. Accordingly, the distance between the third external electrode and the electrode having the smaller distance between the third outer peripheral surface and the third external electrode is ensured as compared with the case where the third external electrode is arranged at the center of the third outer peripheral surface. Therefore, it is possible to suppress the deterioration of isolation between the electrode having the smaller distance between the third external electrode and the third outer peripheral surface.
 同様に、第4外部電極の第4部分が、第4外周面における中央よりも、第1、第2外部電極のうちの第4外周面との距離が大きい方の電極に近い領域に配置される。これにより、第4外部電極を第4外周面における中央に配置する場合に比べて、第4外部電極と、第1、第2外部電極のうちの第4外周面との距離が小さい方の電極との距離が確保される。そのため、第4外部電極と上記第4外周面との距離が小さい方の電極との間でアイソレーションが劣化することを抑制することができる。 Similarly, the fourth portion of the fourth external electrode is disposed in a region closer to the electrode having the greater distance from the fourth outer peripheral surface of the first and second external electrodes than the center of the fourth outer peripheral surface. The Thereby, compared with the case where a 4th external electrode is arrange | positioned in the center in a 4th outer peripheral surface, the electrode of the one where the distance of a 4th outer electrode and the 4th outer peripheral surface of a 1st, 2nd external electrode is smaller And the distance is secured. Therefore, it is possible to suppress the deterioration of isolation between the electrode having the smaller distance between the fourth external electrode and the fourth outer peripheral surface.
 本開示によれば、互いに対向する第1、第2外周面にそれぞれ配置される第1、第2外部電極を備える電子部品において、アイソレーションの劣化を抑制することができる。 According to the present disclosure, it is possible to suppress deterioration of isolation in an electronic component including first and second external electrodes disposed on first and second outer peripheral surfaces facing each other.
電子部品の外観斜視図である。It is an external appearance perspective view of an electronic component. 電子部品の断面図(その1)である。It is sectional drawing (the 1) of an electronic component. 電子部品の断面図(その2)である。It is sectional drawing (the 2) of an electronic component. 電子部品の断面図(その3)である。It is sectional drawing (the 3) of an electronic component. 電子部品の断面図(その4)である。It is sectional drawing (the 4) of an electronic component.
 以下、図面を参照しつつ、実施の形態について説明する。実施の形態の図面において、同一の参照符号や参照番号は、同一部分または相当部分を表わすものとする。また、実施の形態の説明において、同一の参照符号等を付した部分等に対しては、重複する説明は繰り返さない場合がある。 Hereinafter, embodiments will be described with reference to the drawings. In the drawings of the embodiments, the same reference numerals and reference numerals represent the same or corresponding parts. Further, in the description of the embodiments, the overlapping description may not be repeated for the portions with the same reference numerals and the like.
 図1は、本実施の形態による電子部品1の外観斜視図である。電子部品1は、複数の長方形状の誘電体を積層することによって直方体状に形成される。以下では、誘電体の積層方向(電子部品1の高さ方向)をZ軸方向とする。電子部品1の長辺(幅)方向をX軸方向とする。電子部品1の短辺(奥行)方向をY軸方向とする。X軸、Y軸、およびZ軸は互いに直交している。 FIG. 1 is an external perspective view of an electronic component 1 according to the present embodiment. The electronic component 1 is formed in a rectangular parallelepiped shape by stacking a plurality of rectangular dielectrics. Hereinafter, the stacking direction of the dielectric (the height direction of the electronic component 1) is the Z-axis direction. The long side (width) direction of the electronic component 1 is defined as the X-axis direction. The short side (depth) direction of the electronic component 1 is defined as the Y-axis direction. The X axis, the Y axis, and the Z axis are orthogonal to each other.
 図1に示されるように、電子部品1は、直方体状であり、6つの外周面、すなわち、XY平面と平行で互いに対向する上面UFおよび底面BFと、ZX平面と平行で互いに対向する第1側面SAおよび第2側面SBと、YZ平面と平行で互いに対向する第3側面SCおよび第4側面SDとを有する。 As shown in FIG. 1, the electronic component 1 has a rectangular parallelepiped shape, and has six outer peripheral surfaces, that is, a top surface UF and a bottom surface BF that are parallel to the XY plane and face each other, and a first that is parallel to the ZX plane and faces each other. It has a side surface SA and a second side surface SB, and a third side surface SC and a fourth side surface SD that are parallel to the YZ plane and face each other.
 電子部品1は、外部の機器と接続可能に構成される端子(外部電極)P1~P8を備える。端子P1~P8は、外部の機器から高周波信号が入力される入力ポート、外部の機器に高周波信号を出力する出力ポート、所定の抵抗値で終端される接地ポート、接地電位に接続される接地ポートなどとして用いられる。 The electronic component 1 includes terminals (external electrodes) P1 to P8 configured to be connectable to external devices. Terminals P1 to P8 are an input port for inputting a high-frequency signal from an external device, an output port for outputting a high-frequency signal to an external device, a ground port terminated with a predetermined resistance value, and a ground port connected to a ground potential Used as such.
 端子P1~P3の各々(第1外部電極)は、上面UF、第1側面SA、および底面BFに亘って設けられている。端子P4~P6の各々(第2外部電極)は、上面UF、第2側面SB、および底面BFに亘って設けられている。端子P7(第3外部電極)は、上面UF、第3側面SC、および底面BFに亘って設けられている。端子P8(第4外部電極)は、上面UF、第4側面SD、および底面BFに亘って設けられている。 Each of the terminals P1 to P3 (first external electrode) is provided across the top surface UF, the first side surface SA, and the bottom surface BF. Each of the terminals P4 to P6 (second external electrode) is provided across the top surface UF, the second side surface SB, and the bottom surface BF. The terminal P7 (third external electrode) is provided across the top surface UF, the third side surface SC, and the bottom surface BF. The terminal P8 (fourth external electrode) is provided across the top surface UF, the fourth side surface SD, and the bottom surface BF.
 なお、本実施の形態においては、端子P1~P8の形状がほぼ同じである例について説明するが、端子P1~P8の形状は必ずしも同じでなくてもよい。たとえば、端子P1~P8のうちの一部のX軸方向の幅が残部のX軸方向の幅と異なるものであってもよい。 In the present embodiment, an example in which the shapes of the terminals P1 to P8 are substantially the same will be described, but the shapes of the terminals P1 to P8 are not necessarily the same. For example, some of the terminals P1 to P8 may have different X-axis widths than the remaining X-axis widths.
 また、各端子P1~P8は、上面UFおよび底面BFの少なくとも一方に配置される部分を有しないものであってもよい。すなわち、端子P1~P3の各々(第1外部電極)は、少なくとも第1側面SAに配置される部分(より詳しくは、第1側面SAにおける上辺から下辺に亘って延在する部分)を有し、第2側面SBに配置される部分を有しないものであればよい。端子P4~P6の各々(第2外部電極)は、少なくとも第2側面SBに配置される部分(より詳しくは、第2側面SBにおける上辺から下辺に亘って延在する部分)を有し、第1側面SAに配置される部分を有しないものであればよい。端子P7(第3外部電極)は、少なくとも第3側面SCに配置される部分(より詳しくは、第3側面SCにおける上辺から下辺に亘って延在する部分)を有し、第4側面SDに配置される部分を有しないものであればよい。端子P8(第4外部電極)は、少なくとも第4側面SDに配置される部分(より詳しくは、第4側面SDにおける上辺から下辺に亘って延在する部分)を有し、第3側面SCに配置される部分を有しないものであればよい。 Further, each of the terminals P1 to P8 may not have a portion arranged on at least one of the upper surface UF and the bottom surface BF. That is, each of the terminals P1 to P3 (first external electrode) has at least a portion disposed on the first side surface SA (more specifically, a portion extending from the upper side to the lower side of the first side surface SA). What is necessary is just to have no part arrange | positioned in 2nd side SB. Each of the terminals P4 to P6 (second external electrode) has at least a portion disposed on the second side surface SB (more specifically, a portion extending from the upper side to the lower side of the second side surface SB). What is necessary is just to have no part arrange | positioned at 1 side surface SA. The terminal P7 (third external electrode) has at least a portion (more specifically, a portion extending from the upper side to the lower side in the third side surface SC) disposed on the third side surface SC, and is provided on the fourth side surface SD. What is necessary is just to have no part to be arranged. The terminal P8 (fourth external electrode) has at least a portion (more specifically, a portion extending from the upper side to the lower side in the fourth side surface SD) arranged on the fourth side surface SD, and is on the third side surface SC. What is necessary is just to have no part to be arranged.
 以下では、説明を簡略化するために、「端子P1の第1側面SAに配置される部分」、「端子P2の第1側面SAに配置される部分」、「端子P3の第1側面SAに配置される部分」を、それぞれ単に「端子P1」、「端子P2」、「端子P3」とも記載する。「端子P4の第2側面SBに配置される部分」、「端子P5の第2側面SBに配置される部分」、「端子P6の第2側面SBに配置される部分」を、それぞれ単に「端子P4」、「端子P5」、「端子P6」とも記載する。「端子P7の第3側面SCに配置される部分」、「端子P8の第4側面SDに配置される部分」を、それぞれ単に「端子P7」、「端子P8」とも記載する。 Hereinafter, in order to simplify the description, “a portion disposed on the first side surface SA of the terminal P1”, “a portion disposed on the first side surface SA of the terminal P2”, and “a first side surface SA of the terminal P3” The “placed portion” is also simply referred to as “terminal P1”, “terminal P2”, and “terminal P3”, respectively. “Parts disposed on the second side surface SB of the terminal P4”, “parts disposed on the second side surface SB of the terminal P5”, and “portions disposed on the second side surface SB of the terminal P6” are simply referred to as “terminals”. Also referred to as “P4”, “terminal P5”, and “terminal P6”. The “portion disposed on the third side surface SC of the terminal P7” and the “portion disposed on the fourth side surface SD of the terminal P8” are also simply referred to as “terminal P7” and “terminal P8”, respectively.
 図2は、電子部品1をXY平面と平行な面で切断した場合の断面図である。互いに対向する第1側面SAと第2側面SBとの距離は、電子部品1の短辺方向(Y軸方向)の長さLYである。互いに対向する第3側面SCと第4側面SDとの距離は、電子部品1の長辺方向(X軸方向)の長さLXである。 FIG. 2 is a cross-sectional view of the electronic component 1 cut along a plane parallel to the XY plane. The distance between the first side surface SA and the second side surface SB facing each other is a length LY in the short side direction (Y-axis direction) of the electronic component 1. The distance between the third side surface SC and the fourth side surface SD facing each other is the length LX in the long side direction (X-axis direction) of the electronic component 1.
 図2においては、端子P1~P3がY軸方向に沿って第2側面SBにそれぞれ投影された領域が、第2側面SBにおける端子P1~P3との対向領域11~13としてそれぞれ示されている。同様に、端子P4~P6がY軸方向に沿って第1側面SAにそれぞれ投影された領域が、第1側面SAにおける端子P4~P6との対向領域14~16として示されている。端子P8がX軸方向に沿って第3側面SCに投影された領域が、第3側面SCにおける端子P8との対向領域18として示されている。端子P7がX軸方向に沿って第4側面SDに投影された領域が、第4側面SDにおける端子P7との対向領域17として示されている。 In FIG. 2, regions where the terminals P1 to P3 are respectively projected onto the second side surface SB along the Y-axis direction are shown as facing regions 11 to 13 facing the terminals P1 to P3 on the second side surface SB, respectively. . Similarly, regions where the terminals P4 to P6 are respectively projected on the first side surface SA along the Y-axis direction are shown as regions 14 to 16 facing the terminals P4 to P6 on the first side surface SA. A region where the terminal P8 is projected on the third side surface SC along the X-axis direction is shown as a region 18 facing the terminal P8 on the third side surface SC. A region where the terminal P7 is projected on the fourth side surface SD along the X-axis direction is shown as a region 17 facing the terminal P7 on the fourth side surface SD.
 上述したように、端子P1~P3は、第1側面SA上に配置される。端子P4~P6は、第1側面SAに対向する第2側面SB上に配置される。端子P7は、第3側面SCに配置される。端子P8は、第3側面SCに対向する第4側面SDに配置される。 As described above, the terminals P1 to P3 are arranged on the first side surface SA. The terminals P4 to P6 are disposed on the second side surface SB that faces the first side surface SA. The terminal P7 is disposed on the third side surface SC. The terminal P8 is disposed on the fourth side surface SD facing the third side surface SC.
 仮に、端子P1~P3が第1側面SAにおける端子P4~P6との対向領域14~16にそれぞれ配置されると、端子P1~P3の各々と端子P4~P6の各々との対向面積が大きくなるため、対向する端子同士で容量結合してしまい、アイソレーションの劣化につながる恐れがある。同様に、仮に、端子P7が第3側面SCにおける端子P8との対向領域18に配置されると、対向する端子P7,P8同士で容量結合してしまい、アイソレーションの劣化につながる恐れがある。 If the terminals P1 to P3 are respectively disposed in the facing regions 14 to 16 facing the terminals P4 to P6 on the first side surface SA, the facing area between each of the terminals P1 to P3 and each of the terminals P4 to P6 increases. For this reason, capacitive coupling occurs between the terminals facing each other, which may lead to deterioration of isolation. Similarly, if the terminal P7 is disposed in the region 18 facing the terminal P8 on the third side surface SC, the opposing terminals P7 and P8 are capacitively coupled to each other, which may lead to deterioration of isolation.
 対向する端子同士の容量結合度は端子同士の対向面積に比例し端子間の距離に反比例するところ、電子部品1の小型化が進むと、端子間の距離(短辺方向の長さLY、あるいは長辺方向の長さLX)が短くなり端子同士の容量結合度がより大きくなるため、アイソレーションがさらに劣化することが懸念される。特に、第1側面SAと第2側面SBとの距離LYは第3側面SCと第4側面SDとの距離LXよりも短く、その分、端子P1~P3と端子P4~P6との容量結合度もより大きくなることが懸念される。 The degree of capacitive coupling between the opposing terminals is proportional to the opposing area between the terminals and inversely proportional to the distance between the terminals. As the electronic component 1 is further downsized, the distance between the terminals (the length LY in the short side direction, or Since the length LX) in the long side direction is shortened and the capacitive coupling between the terminals is further increased, there is a concern that the isolation is further deteriorated. In particular, the distance LY between the first side surface SA and the second side surface SB is shorter than the distance LX between the third side surface SC and the fourth side surface SD, and accordingly, the degree of capacitive coupling between the terminals P1 to P3 and the terminals P4 to P6. There is a concern that it will become larger.
 上記の点に鑑み、本実施の形態による電子部品1においては、端子P1~P3が、第1側面SAにおける端子P4~P6との対向領域14~16のいずれからも外れた領域に配置される。端子P4~P6が、第2側面SBにおける端子P1~P3との対向領域11~13のいずれからも外れた領域に配置される。 In view of the above, in the electronic component 1 according to the present embodiment, the terminals P1 to P3 are arranged in a region that is out of any of the regions 14 to 16 facing the terminals P4 to P6 on the first side surface SA. . The terminals P4 to P6 are arranged in a region outside any of the regions 11 to 13 facing the terminals P1 to P3 on the second side surface SB.
 そのため、第1側面SA上に配置される端子P1~P3(第1外部電極)と、第1側面SAに対向する第2側面SB上に配置される端子P4~P6(第2外部電極)とは、互いに対向しない。そのため、端子P1~P3と端子P4~P6との対向面積が0になるため、端子P1~P3の各々と端子P4~P6の各々との容量結合度を非常に小さい値に抑制することができる。 Therefore, terminals P1 to P3 (first external electrodes) disposed on the first side surface SA, and terminals P4 to P6 (second external electrodes) disposed on the second side surface SB opposite to the first side surface SA, Are not opposed to each other. Therefore, since the facing area between the terminals P1 to P3 and the terminals P4 to P6 becomes 0, the degree of capacitive coupling between each of the terminals P1 to P3 and each of the terminals P4 to P6 can be suppressed to a very small value. .
 さらに、本実施の形態による電子部品1においては、端子P7が、第3側面SCにおける端子P8との対向領域18から外れた領域に配置される。端子P8が、第4側面SDにおける端子P7との対向領域17から外れた領域に配置される。そのため、端子P1~P3の各々と端子P4~P6の各々との容量結合度に加えて、端子P7,P8同士の容量結合をも抑制することができる。 Furthermore, in the electronic component 1 according to the present embodiment, the terminal P7 is arranged in a region outside the region 18 facing the terminal P8 on the third side surface SC. The terminal P8 is disposed in a region outside the region 17 facing the terminal P7 on the fourth side surface SD. Therefore, in addition to the capacitive coupling degree between each of the terminals P1 to P3 and each of the terminals P4 to P6, capacitive coupling between the terminals P7 and P8 can be suppressed.
 さらに、本実施の形態による電子部品1においては、端子P7が、第3側面SCにおける中央CL3よりも、端子P1に近い領域に配置される。本実施の形態においては、端子P1~P3(第1外部電極)と端子P4~P6(第2外部電極)とを対向しない領域に配置したことによって、第3側面SCと端子P4(第2外部電極)との距離が、第3側面SCと端子P1(第1外部電極)との距離よりも小さくなっている。そのため、仮に、端子P7を第3側面SCにおける中央CL3に配置すると、端子P7と端子P4との距離が確保できず、端子P7と端子P4との間でアイソレーションが劣化することが懸念される。そこで、本実施の形態においては、端子P7が、第3側面SCにおける中央CL3よりも、端子P1および端子P4のうちの第3側面SCとの距離が大きい方の端子P1に近い領域に配置される。これにより、端子P7を第3側面SCにおける中央CL3に配置する場合に比べて、端子P7と端子P4との距離が確保される。そのため、端子P7と端子P4との間でアイソレーションが劣化することを抑制することができる。 Furthermore, in the electronic component 1 according to the present embodiment, the terminal P7 is disposed in a region closer to the terminal P1 than the center CL3 on the third side surface SC. In the present embodiment, the terminals P1 to P3 (first external electrode) and the terminals P4 to P6 (second external electrode) are arranged in regions that do not face each other, so that the third side surface SC and the terminal P4 (second external electrode) are arranged. The distance to the electrode) is smaller than the distance between the third side surface SC and the terminal P1 (first external electrode). Therefore, if the terminal P7 is disposed at the center CL3 on the third side surface SC, the distance between the terminal P7 and the terminal P4 cannot be secured, and there is a concern that the isolation between the terminal P7 and the terminal P4 deteriorates. . Therefore, in the present embodiment, the terminal P7 is disposed in a region closer to the terminal P1 having a larger distance from the third side SC of the terminals P1 and P4 than the center CL3 of the third side SC. The Thereby, the distance between the terminal P7 and the terminal P4 is ensured as compared with the case where the terminal P7 is arranged at the center CL3 on the third side surface SC. Therefore, it is possible to suppress the deterioration of isolation between the terminal P7 and the terminal P4.
 同様に、本実施の形態による電子部品1においては、端子P8が、第4側面SDにおける中央CL4よりも、端子P3および端子P6のうちの第4側面SDとの距離が大きい方の端子P6に近い領域に配置される。これにより、端子P8を第4側面SDにおける中央CL4に配置する場合に比べて、端子P8と端子P3との距離が確保される。そのため、端子P8と端子P3との間でアイソレーションが劣化することを抑制することができる。 Similarly, in the electronic component 1 according to the present embodiment, the terminal P8 is connected to the terminal P6 having a larger distance from the terminal P3 and the fourth side surface SD among the terminals P6 than the center CL4 in the fourth side surface SD. Arranged in the near area. Thereby, the distance between the terminal P8 and the terminal P3 is ensured as compared with the case where the terminal P8 is arranged at the center CL4 in the fourth side surface SD. Therefore, it is possible to suppress the deterioration of isolation between the terminal P8 and the terminal P3.
 以上のように、本実施の形態による電子部品1においては、第1側面SAに配置される端子P1~P3と、第1側面SAと対向する第2側面SBに配置される端子P4~P6とも、互いに対向しない(対向面積が0になる)ように配置される。これにより、端子P1~P3の各々と端子P4~P6の各々との容量結合度を非常に小さい値に抑制することができる。 As described above, in the electronic component 1 according to the present embodiment, the terminals P1 to P3 disposed on the first side surface SA and the terminals P4 to P6 disposed on the second side surface SB facing the first side surface SA are both. These are arranged so as not to face each other (the facing area becomes 0). Thereby, the capacitive coupling degree between each of the terminals P1 to P3 and each of the terminals P4 to P6 can be suppressed to a very small value.
 さらに、本実施の形態による電子部品1においては、第3側面SCに配置される端子P7と、第4側面SDに配置される端子P8とが、互いに対向しない(対向面積が0になる)ように配置される。これにより、端子P7と端子P8との容量結合度をも非常に小さい値に抑制することができる。 Furthermore, in the electronic component 1 according to the present embodiment, the terminal P7 disposed on the third side surface SC and the terminal P8 disposed on the fourth side surface SD do not face each other (the facing area becomes 0). Placed in. Thereby, the capacitive coupling degree of the terminal P7 and the terminal P8 can also be suppressed to a very small value.
 <変形例1>
 上述の実施の形態による電子部品1においては第3側面SCおよび第4側面SDにそれぞれ端子P7,P8が配置されていたが、端子P7,P8の少なくとも一方を有しないものであってもよい。
<Modification 1>
In the electronic component 1 according to the above-described embodiment, the terminals P7 and P8 are disposed on the third side surface SC and the fourth side surface SD, respectively, but may not include at least one of the terminals P7 and P8.
 図3は、本変形例1による電子部品1AをXY平面と平行な面で切断した場合の断面図の一例である。本変形例1による電子部品1Aは、上述の実施の形態による電子部品1から端子P7,P8を取り除いたものである。 FIG. 3 is an example of a cross-sectional view when the electronic component 1A according to the first modification is cut along a plane parallel to the XY plane. An electronic component 1A according to Modification 1 is obtained by removing the terminals P7 and P8 from the electronic component 1 according to the above-described embodiment.
 このような電子部品1Aにおいても、上述の本実施の形態による電子部品1と同様、端子P1~P3と端子P4~P6とが対向しないように配置されるため、端子P1~P3の各々と端子P4~P6の各々との容量結合度を非常に小さい値に抑制することができる。 Also in such an electronic component 1A, since the terminals P1 to P3 and the terminals P4 to P6 are arranged so as not to face each other as in the electronic component 1 according to the present embodiment described above, each of the terminals P1 to P3 and the terminal The degree of capacitive coupling with each of P4 to P6 can be suppressed to a very small value.
 <変形例2>
 上述の実施の形態による電子部品1においては、端子P1~P3の各々の全部が対向領域14~16のいずれからも外れた領域に配置され、端子P4~P6の各々の全部が対向領域11~13のいずれからも外れた領域に配置されていた。
<Modification 2>
In the electronic component 1 according to the above-described embodiment, all of the terminals P1 to P3 are arranged in a region outside any of the opposing regions 14 to 16, and all of the terminals P4 to P6 are all of the opposing regions 11 to It was arranged in a region deviating from any of 13.
 しかしながら、端子P1~P3の各々の一部のみが対向領域14~16のいずれからも外れた領域に配置され、かつ、端子P4~P6の各々の一部のみが対向領域11~13のいずれからも外れた領域に配置されるようにしてもよい。 However, only a part of each of the terminals P1 to P3 is disposed in a region that is out of any of the opposing regions 14 to 16, and only a part of each of the terminals P4 to P6 is from any of the opposing regions 11 to 13. May be arranged in a region outside.
 図4は、本変形例2による電子部品1BをXY平面と平行な面で切断した場合の断面図の一例である。本変形例2による電子部品1Bは、上述の実施の形態による電子部品1に対して、端子P1~P6の配置のみが異なる。 FIG. 4 is an example of a cross-sectional view when the electronic component 1B according to Modification 2 is cut along a plane parallel to the XY plane. The electronic component 1B according to the second modification differs from the electronic component 1 according to the above-described embodiment only in the arrangement of the terminals P1 to P6.
 図4に示すように、本変形例2による電子部品1Bにおいては、端子P1の大部分は対向領域14~16から外れた領域に配置されるが、残部は対向領域14に含まれ、端子P4と対向している。そして、端子P4の大部分は対向領域11~13から外れた領域に配置されるが、残部は対向領域11に含まれ、端子P1と対向している。端子P2と端子P5との配置関係、端子P3と端子P6との配置関係も、端子P1と端子P4との配置関係と同様である。 As shown in FIG. 4, in the electronic component 1B according to the second modified example, most of the terminals P1 are arranged in areas outside the opposing areas 14 to 16, but the remaining part is included in the opposing area 14 and the terminals P4 Is facing. Most of the terminal P4 is disposed in a region outside the facing regions 11 to 13, but the remaining part is included in the facing region 11 and faces the terminal P1. The arrangement relationship between the terminals P2 and P5 and the arrangement relationship between the terminals P3 and P6 are the same as the arrangement relationship between the terminals P1 and P4.
 このような電子部品1Bにおいても、端子P1~P3の各々の全部が対向領域14~16のいずれかに含まれ、かつ端子P4~P6の各々の全部が対向領域11~13のいずれかに含まれる場合に比べて、端子P1~P3と端子P4~P6との対向面積が小さくなるため、端子P1~P3と端子P4~P6との容量結合度を小さくすることができる。 Also in such an electronic component 1B, all of the terminals P1 to P3 are all included in any of the opposing regions 14 to 16, and all of the terminals P4 to P6 are all included in any of the opposing regions 11 to 13. Compared to the case where the terminals P1 to P3 and the terminals P4 to P6 are opposed to each other, the capacity of the capacitive coupling between the terminals P1 to P3 and the terminals P4 to P6 can be reduced.
 <変形例3>
 上述の実施の形態による電子部品1においては、第1側面SAに3つの端子P1~P3が配置され、第2側面SBに3つの端子P4~P6が配置される例について説明した。しかしながら、第1側面SAに配置される端子の数、および第2側面SBに配置される端子の数は、3つに限定されるものではなく、1つであってもよいし、2つであってもよいし、4つ以上であってもよい。
<Modification 3>
In the electronic component 1 according to the above-described embodiment, the example in which the three terminals P1 to P3 are arranged on the first side surface SA and the three terminals P4 to P6 are arranged on the second side surface SB has been described. However, the number of terminals arranged on the first side surface SA and the number of terminals arranged on the second side surface SB are not limited to three, and may be one or two. There may be four or more.
 また、上述の実施の形態による電子部品1においては、第1側面SAに配置される端子P1~P3と第2側面SBに配置される端子P4~P6とが対向しないように配置されるだけでなく、第3側面SCに配置される端子P7と第4側面SDに配置される端子P8とも対向しないように配置されていた。しかしながら、第3側面SCに配置される端子P7と第4側面SDに配置される端子P8とが互いに対向するように配置されていてもよい。 Further, in the electronic component 1 according to the above-described embodiment, the terminals P1 to P3 disposed on the first side surface SA and the terminals P4 to P6 disposed on the second side surface SB are merely disposed so as not to face each other. The terminal P7 arranged on the third side surface SC and the terminal P8 arranged on the fourth side surface SD are arranged so as not to face each other. However, the terminal P7 disposed on the third side surface SC and the terminal P8 disposed on the fourth side surface SD may be disposed to face each other.
 図5は、本変形例3による電子部品1CをXY平面と平行な面で切断した場合の断面図の一例である。本変形例3による電子部品1Cは、上述の実施の形態による電子部品1に対して、端子P3,P5,P6を取り除き、さらに端子P1,P2,P4,P7,P8の配置を変更したものである。 FIG. 5 is an example of a cross-sectional view when the electronic component 1C according to the third modification is cut along a plane parallel to the XY plane. The electronic component 1C according to the third modification is obtained by removing the terminals P3, P5, and P6 from the electronic component 1 according to the above-described embodiment, and further changing the arrangement of the terminals P1, P2, P4, P7, and P8. is there.
 第1側面SAと第2側面SBとの距離LYは第3側面SCと第4側面SDとの距離LXよりも短く、その分、端子P1,P2と端子P4との容量結合度が大きくなることが懸念される。そのため、本変形例3による電子部品1Cにおいては、図5に示すように、第1側面SAに配置される端子P1,P2は対向領域14から外れた領域に配置され、第2側面SBに配置される端子P4は対向領域11,12から外れた領域に配置される。これにより、端子P1,P2と端子P4との容量結合度を非常に小さい値に抑制することができる。 The distance LY between the first side surface SA and the second side surface SB is shorter than the distance LX between the third side surface SC and the fourth side surface SD, and accordingly, the degree of capacitive coupling between the terminals P1, P2 and the terminal P4 is increased. Is concerned. Therefore, in the electronic component 1C according to the third modification, as shown in FIG. 5, the terminals P1 and P2 arranged on the first side surface SA are arranged in a region away from the facing region 14 and arranged on the second side surface SB. The terminal P4 to be connected is disposed in a region outside the opposing regions 11 and 12. Thereby, the capacitive coupling degree between the terminals P1, P2 and the terminal P4 can be suppressed to a very small value.
 一方、第3側面SCと第4側面SDとの距離LXは第1側面SAと第2側面SBとの距離LYよりも長く、その分、仮に端子P7と端子P8とが対向しても両者の容量結合度は小さい値であることが想定される。また、第3側面SCおよび第4側面SDは、第1側面SAおよび第2側面SBよりも幅が小さく、端子を配置可能な領域が狭い。 On the other hand, the distance LX between the third side surface SC and the fourth side surface SD is longer than the distance LY between the first side surface SA and the second side surface SB, and even if the terminal P7 and the terminal P8 face each other, It is assumed that the capacitive coupling degree is a small value. Further, the third side surface SC and the fourth side surface SD are smaller in width than the first side surface SA and the second side surface SB, and the area where the terminals can be arranged is narrow.
 そのため、本変形例3による電子部品1Cにおいては、図5に示すように、第3側面SCに配置される端子P7が対向領域18に配置され、第4側面SDに配置される端子P8が対向領域17に配置される。このように、対向距離が長くかつ端子を配置可能な領域が狭い第3側面SCおよび第4側面SDにそれぞれ配置される端子P7,P8については、互いに対向することが許容される。これにより、端子P7,P8の容量結合度を抑制しつつ、端子P7,P8の配置領域を自由に設定することができる。 Therefore, in the electronic component 1C according to the third modification, as illustrated in FIG. 5, the terminal P7 disposed on the third side surface SC is disposed in the facing region 18, and the terminal P8 disposed on the fourth side surface SD is opposed. Arranged in region 17. As described above, the terminals P7 and P8 disposed on the third side surface SC and the fourth side surface SD, respectively, which have a long facing distance and a narrow region where the terminals can be disposed, are allowed to face each other. Thereby, the arrangement region of the terminals P7 and P8 can be freely set while suppressing the capacitive coupling degree of the terminals P7 and P8.
 今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本開示の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present disclosure is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
 1,1A,1B,1C 電子部品、11~18 対向領域、BF 底面、P1~P8 端子、SA 第1側面、SB 第2側面、SC 第3側面、SD 第4側面、UF 上面。 1, 1A, 1B, 1C electronic parts, 11-18 facing area, BF bottom surface, P1-P8 terminals, SA first side, SB second side, SC third side, SD fourth side, UF top surface.

Claims (6)

  1.  互いに対向する第1外周面および第2外周面を有する直方体状の電子部品であって、
     各々が前記第1外周面上に配置される第1部分を有しかつ前記第2外周面上に配置される第2部分を有さない複数の第1外部電極と、
     前記第2部分を有しかつ前記第1部分を有さない少なくとも1つの第2外部電極とを備え、
     各前記第1外部電極の前記第1部分の少なくとも一部は、前記第1外周面における、前記第2外部電極の前記第2部分と対向する領域から外れた領域に配置され、
     前記第2外部電極の前記第2部分の少なくとも一部は、前記第2外周面における、前記複数の第1外部電極の前記第1部分にそれぞれ対向する複数の領域のいずれからも外れた領域に配置される、電子部品。
    A rectangular parallelepiped electronic component having a first outer peripheral surface and a second outer peripheral surface facing each other,
    A plurality of first external electrodes each having a first portion disposed on the first outer peripheral surface and not having a second portion disposed on the second outer peripheral surface;
    And at least one second external electrode having the second part and not having the first part,
    At least a part of the first portion of each first external electrode is disposed in a region outside the region facing the second portion of the second external electrode on the first outer peripheral surface,
    At least a part of the second portion of the second external electrode is a region on the second outer peripheral surface that is out of any of the plurality of regions that respectively face the first portion of the plurality of first external electrodes. Electronic components to be placed.
  2.  前記電子部品は、複数の前記第2外部電極を備え、
     各前記第1外部電極の前記第1部分の少なくとも一部は、前記第1外周面における、複数の前記第2外部電極の前記第2部分にそれぞれ対向する複数の領域のいずれからも外れた領域に配置され、
     各前記第2外部電極の前記第2部分の少なくとも一部は、前記第2外周面における、複数の前記第1外部電極の前記第1部分にそれぞれ対向する複数の領域のいずれからも外れた領域に配置される、請求項1に記載の電子部品。
    The electronic component includes a plurality of the second external electrodes,
    At least a part of the first portion of each of the first external electrodes is a region that is out of any of the plurality of regions that respectively face the second portions of the plurality of second external electrodes on the first outer peripheral surface. Placed in
    At least a part of the second portion of each of the second external electrodes is a region that is out of any of the plurality of regions that respectively face the first portions of the plurality of first external electrodes on the second outer peripheral surface. The electronic component according to claim 1, wherein the electronic component is disposed on the surface.
  3.  各前記第1外部電極の前記第1部分の全部が、前記第1外周面における、複数の前記第2外部電極の前記第2部分にそれぞれ対向する複数の領域のいずれからも外れた領域に配置され、
     各前記第2外部電極の前記第2部分の全部が、前記第2外周面における、前記複数の第1外部電極の前記第1部分にそれぞれ対向する複数の領域のいずれからも外れた領域に配置される、請求項2に記載の電子部品。
    All of the first portion of each of the first external electrodes is disposed in a region on the first outer peripheral surface that is out of any of the plurality of regions that respectively face the second portions of the plurality of second external electrodes. And
    All of the second portion of each of the second external electrodes is disposed in a region outside the plurality of regions that respectively face the first portions of the plurality of first external electrodes on the second outer peripheral surface. The electronic component according to claim 2.
  4.  前記電子部品は、
     前記第1外周面と前記第2外周面とに接続される第3外周面と、
     前記第1外周面と前記第2外周面とに接続され、かつ前記第3外周面と対向する第4外周面とをさらに有し、
     前記第1外周面と前記第2外周面との距離は、前記第3外周面と前記第4外周面との距離よりも短い、請求項1~3のいずれかに記載の電子部品。
    The electronic component is
    A third outer peripheral surface connected to the first outer peripheral surface and the second outer peripheral surface;
    A fourth outer peripheral surface connected to the first outer peripheral surface and the second outer peripheral surface and facing the third outer peripheral surface;
    The electronic component according to claim 1, wherein a distance between the first outer peripheral surface and the second outer peripheral surface is shorter than a distance between the third outer peripheral surface and the fourth outer peripheral surface.
  5.  前記電子部品は、
     前記第3外周面に配置される第3部分を有する第3外部電極と、
     前記第4外周面に配置される第4部分を有する第4外部電極とを備え、
     前記第3外部電極の前記第3部分の少なくとも一部は、前記第3外周面における、前記第4外部電極の前記第4部分と対向する領域から外れた領域に配置され、
     前記第4外部電極の前記第4部分の少なくとも一部は、前記第4外周面における、前記第3外部電極の前記第3部分と対向する領域から外れた領域に配置される、請求項4に記載の電子部品。
    The electronic component is
    A third external electrode having a third portion disposed on the third outer peripheral surface;
    A fourth external electrode having a fourth portion disposed on the fourth outer peripheral surface,
    At least a part of the third portion of the third external electrode is disposed in a region outside the region facing the fourth portion of the fourth external electrode on the third outer peripheral surface,
    The at least part of the fourth portion of the fourth external electrode is disposed in a region outside the region facing the third portion of the third external electrode on the fourth outer peripheral surface. The electronic component described.
  6.  前記電子部品は、
     前記第3外周面に配置される第3部分を有する第3外部電極と、
     前記第4外周面に配置される第4部分を有する第4外部電極とを備え、
     前記第3外部電極の前記第3部分は、前記第3外周面における中央よりも、前記第1外部電極および前記第2外部電極のうちの前記第3外周面との距離が大きい方の電極に近い領域に配置され、
     前記第4外部電極の前記第4部分は、前記第4外周面における中央よりも、前記第1外部電極および前記第2外部電極のうちの前記第4外周面との距離が大きい方の電極に近い領域に配置される、請求項4に記載の電子部品。
    The electronic component is
    A third external electrode having a third portion disposed on the third outer peripheral surface;
    A fourth external electrode having a fourth portion disposed on the fourth outer peripheral surface,
    The third portion of the third external electrode is an electrode having a larger distance from the third outer peripheral surface of the first external electrode and the second external electrode than the center of the third outer peripheral surface. Placed in a close area,
    The fourth portion of the fourth external electrode is an electrode having a larger distance from the fourth outer peripheral surface of the first outer electrode and the second outer electrode than the center of the fourth outer peripheral surface. The electronic component according to claim 4, wherein the electronic component is disposed in a close region.
PCT/JP2018/010973 2017-04-28 2018-03-20 Electronic component WO2018198600A1 (en)

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JPH02117933U (en) * 1989-03-13 1990-09-21
WO2008015899A1 (en) * 2006-08-02 2008-02-07 Murata Manufacturing Co., Ltd. Filter element and method for manufacturing filter element
JP2008078664A (en) * 2006-09-22 2008-04-03 Samsung Electro-Mechanics Co Ltd Stacked chip capacitor
US20110090665A1 (en) * 2009-10-16 2011-04-21 Avx Corporation Thin film surface mount components

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JP2006286731A (en) * 2005-03-31 2006-10-19 Tdk Corp Multilayer capacitor
JP5652542B2 (en) * 2011-03-14 2015-01-14 株式会社村田製作所 Directional coupler
TWM527148U (en) * 2016-03-29 2016-08-11 Yageo Corp Multilayer capacitor with multiple terminal electrode

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02117933U (en) * 1989-03-13 1990-09-21
WO2008015899A1 (en) * 2006-08-02 2008-02-07 Murata Manufacturing Co., Ltd. Filter element and method for manufacturing filter element
JP2008078664A (en) * 2006-09-22 2008-04-03 Samsung Electro-Mechanics Co Ltd Stacked chip capacitor
US20110090665A1 (en) * 2009-10-16 2011-04-21 Avx Corporation Thin film surface mount components

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