CN105097721A - Method for forming packaged structure - Google Patents

Method for forming packaged structure Download PDF

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Publication number
CN105097721A
CN105097721A CN201510375008.0A CN201510375008A CN105097721A CN 105097721 A CN105097721 A CN 105097721A CN 201510375008 A CN201510375008 A CN 201510375008A CN 105097721 A CN105097721 A CN 105097721A
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China
Prior art keywords
chip
connecting key
carrier
formation method
layer
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Granted
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CN201510375008.0A
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CN105097721B (en
Inventor
石磊
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Nantong Fujitsu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to a method for forming a packaged structure. The method comprises the following steps: providing a carrier with a chip area, a third surface and a fourth surface, wherein the third surface is opposite to the fourth surface; forming a slot around the chip area in the carrier; fixing a chip on the third surface in the chip area of the carrier, wherein the chip is provided with a first surface and a second surface opposite to each other; the second surface of the chip comprises a functional area; and the first surface of the chip is mutually fixed with the third surface of the carrier; fixing a connection key comprising a first end and a second end in the slot, wherein a conductor wire is exposed at the first end and the second end of the connection key; the first end of the connection key is positioned in the slot; and the second end of the connection key is aligned to the surface of the functional area of the chip; forming a plastic packaging layer encircling the chip and the connection key on the third surface of the carrier; thinning the fourth surface of the carrier till the second end of the connection key is exposed; and forming a re-wiring layer and a first welded ball on the surface of the plastic packaging layer. The method for forming the packaged structure is simple; the technological cost is low; and the formed packaged structure is precise and small in size.

Description

The formation method of encapsulating structure
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of encapsulating structure.
Background technology
In the prior art, the connection of chip and external circuit is realized by the mode of metal lead wire bonding (WireBonding), i.e. Wire Bonding Technology.Along with the integrated level of the feature size downsizing of chip and integrated circuit improves, the growth requirement of Wire Bonding Technology no longer applicable technology.
In order to improve the integrated level of chip package, Stacked Die Packaging (stackeddiepackage) technology becomes the main flow of technical development gradually.Stacked Die Packaging technology, also known as three-dimensional packaging technology, the specifically encapsulation technology of stacking at least two chips in same packaging body.Stacked Die Packaging technology can realize the Large Copacity of semiconductor device, multi-functional, the technical need such as small size, low cost, and therefore laminated chips technology obtains flourish in recent years.
To use the memory of stacked package technology, compared to the memory not using Stack Technology, adopt the memory of stacked package technology can have the memory capacity of more than twice.In addition, use stacked package technology more can effectively utilize the area of chip, be applied to the aspect such as the USB flash disk of large memory space, SD card more.
Stacked chips encapsulation technology can be realized by multiple technologies means, such as routing technique, silicon through hole (throughsiliconvia is called for short TSV) technology or plastic packaging through hole (throughmoldingvia is called for short TMV) technology.
But above-mentioned technological means still faces various process technology limit and cost restriction, and, be faced with the problem of further thinning encapsulating structure gauge.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of encapsulating structure, and the formation method of described encapsulating structure is simple, process costs reduces, and the encapsulating structure size formed accurately and reduce.
For solving the problem, the invention provides a kind of formation method of encapsulating structure, comprising:
There is provided carrier, described carrier has chip region, and described carrier has the 3rd relative surface and the 4th surface;
In described carrier, form one or several slots, described slot is positioned at around described chip region, and described slot top is positioned at described 3rd surface;
At the 3rd surperficial fixed chip of described support core section, described chip has relative first surface and second surface, and the second surface of described chip comprises functional areas, and the first surface of described chip and the 3rd surface of carrier interfix;
At described slot internal fixtion connecting key, described connecting key comprises conductor wire, described connecting key comprises first end and the second end, first end and second end of described connecting key expose described conductor wire, the first end of described connecting key is positioned at described slot, and the second end of described connecting key flushes in surface, the functional areas of described chip;
Form plastic packaging layer on the 3rd surface of described carrier, described plastic packaging layer surrounds described chip and connecting key, and the surface of described plastic packaging layer exposes the second end of described connecting key and the surface, functional areas of chip;
Carry out thinning, until expose the first end of described connecting key to described the 4th surface at carrier;
Form wiring layer again on described plastic packaging layer surface, described wiring layer is again electrically connected with the second end of described connecting key and the functional areas of chip;
The first soldered ball is formed on the described surface of wiring layer again.
Optionally, described connecting key also comprises the protective layer being positioned at described conductor wire sidewall surfaces, and described protective layer exposes the conductor wire of described connecting key first end and the second end.
Optionally, the forming step of described connecting key comprises: provide initial conduction line, and described initial conduction line has the 3rd end and the 4th end; Form initial protective layers in the sidewall surfaces of described initial conduction line, form initial connecting key, described initial protective layers exposes the 3rd end and the 4th end of described initial conduction line; Cut described initial protective layers and initial conduction line along the direction perpendicular to described initial conduction line sidewall, form some sections of conductor wires and be positioned at the protective layer of conductor wire sidewall surfaces.
Optionally, the formation process of described initial protective layers comprises chemical vapor deposition method, physical gas-phase deposition, atom layer deposition process, spraying coating process or Shooting Technique.
Optionally, the material of described protective layer is insulating material.
Optionally, described insulating material is organic insulating material or inorganic insulating material; Described organic insulating material comprises polyvinyl chloride; Described inorganic insulating material comprise in silica, silicon nitride and silicon oxynitride one or more.
Optionally, the first end size of described connecting key and the second end measure-alike; The conductor wire size of described connecting key first end and the conductor wire of the second end measure-alike.
Optionally, described connecting key first end is 40 microns ~ 400 microns to the distance of the second end.
Optionally, the material of described conductor wire is copper, tungsten, aluminium, gold or silver-colored.
Optionally, in the carrier around each described chip region, there is one or several slots.
Optionally, the size at the top of described slot is more than or equal to the size of the first end of described connecting key.
Optionally, the sidewalls orthogonal of described slot is in the 3rd surface of described carrier.
Optionally, the degree of depth of described slot is less than the thickness of described carrier.
Optionally, carrying out thinning technique to described the 4th surface at carrier is CMP (Chemical Mechanical Polishing) process or etching technics.
Optionally, the surface, functional areas of described chip exposes pad; ; Described bond pad surface has projection, and the top surface of described projection protrudes from the second surface of described chip; Described plastic packaging layer exposes the top surface of described projection, the top surface of described projection and the surface, functional areas of described chip.
Optionally, also comprise: described in formation again before wiring layer, form the first insulating barrier on described plastic packaging layer surface, have in described first insulating barrier and expose the conductor wire of described connecting key second end and some first through holes on surface, chip functions district respectively; In described first through hole and part first surface of insulating layer formed described in wiring layer again.
Optionally, also comprise: before described first soldered ball of formation, form the second insulating barrier on the described surface of wiring layer again, there is in described second insulating barrier the second through hole exposing partly again wiring layer; Described first soldered ball is formed in described second through hole.
Optionally, also comprise: after thinning described carrier, form the second soldered ball on the conductor wire surface of described connecting key first end.
Optionally, also comprise: provide packaging body, described packaging body has the 5th surface, and the 5th surface of described packaging body exposes conductive structure; The first surface of described chip and plastic packaging layer surface are oppositely arranged with the 5th surface of described packaging body, and by welding procedure, described second soldered ball and described conductive structure are interconnected.
Compared with prior art, technical scheme of the present invention has the following advantages:
In formation method of the present invention, there is in described carrier the slot be positioned at around chip region, and described slot top is positioned at carrier the 3rd surface.Described slot is used for being fixedly connected with key, makes described connecting key be positioned at chip circumference, and described chip is fixed on the 3rd surface of support core section.First end due to described connecting key is positioned at described slot, therefore the contact stabilization between described connecting key and described carrier, in subsequent technique, described connecting key is not easily subjected to displacement, thus ensure that the relative position between described connecting key and chip is accurate, between the functional areas being conducive to wiring layer and connecting key or chip again described in avoiding, occurrence positions offsets, and then ensure that the electrical connection between the wiring layer again of follow-up formation and described connecting key and chip functions district is stablized.Described connecting key comprises conductor wire, and the first end of described connecting key and the second end all expose conductor wire; After the first end of described connecting key is fixed in slot, second end of described connecting key can flush the functional surfaces in described chip, therefore, after described carrier surface formation exposes the plastic packaging floor in chip functions district, second end of described connecting key also can flush in described plastic packaging layer surface, make described conductor wire can be through in the slot of carrier from described plastic packaging layer surface, realize the electrical connection of chip first surface to second surface with this.Because described connecting key is fixed in the slot of carrier, avoid the follow-up step that plastic packaging layer is processed, the formation process of encapsulating structure can be made to simplify.To sum up, the formation method processing step of described encapsulating structure simplifies, process costs reduces, technology difficulty reduces, and the size of the encapsulating structure formed is more accurate, is conducive to the size reducing encapsulating structure.
Further, described connecting key also comprises the protective layer being positioned at described conductor wire sidewall surfaces.Described protective layer can not only protect described conductor wire when being inserted in slot by connecting key, can also increase the cross sectional dimensions of connecting key; When being inserted in slot by described connecting key, described connecting key is easier to aim at, and is conducive to ensureing that described connecting key is accurate relative to the position of chip.
Further, the first end of described connecting key and the measure-alike of the second end, and the sidewalls orthogonal of described size is in surface, carrier ground the 3rd, when described connecting key inserts described slot, what be conducive to making between described connecting key and carrier is fixing more stable, can avoid in the process forming plastic packaging layer, described connecting key is subjected to displacement, thus ensure that the relative position between connecting key and chip is accurate.
Accompanying drawing explanation
Fig. 1 introduces through-silicon via structure to realize the cross-sectional view of chip chamber conducting in encapsulating structure;
Fig. 2 introduces plastic packaging through-hole structure to realize the cross-sectional view of chip chamber conducting in encapsulating structure;
Fig. 3 to Figure 18 is the structural representation of the forming process of the encapsulating structure of the embodiment of the present invention.
Embodiment
As stated in the Background Art, existing stacked chips encapsulation technology faces process technology limit and cost restriction, restriction is caused for applying of technology, and, stacked chips encapsulation technology also faces the problem at further thinning encapsulating structure gauge, to improving integrated level, the reduction size of chip further.
Stacked chips encapsulation technology can pass through silicon through hole (throughsiliconvia is called for short TSV) technology or plastic packaging through hole (throughmoldingvia is called for short TMV) technology realizes.But, no matter be silicon through hole technology or plastic packaging through hole technology, all there is certain defect.
Please refer to Fig. 1, Fig. 1 introduces through-silicon via structure to realize the cross-sectional view of chip chamber conducting in encapsulating structure, comprising: carrier 100; Be fixed on the chip 101 on carrier 100 surface, described chip 101 comprises relative non-functional face 102 and functional surfaces 103, and the non-functional face 102 of described chip 101 contacts with carrier 100 surface, and functional surfaces 103 surface of described chip 101 has pad 104; Run through the conductive plunger 105 of described chip 101, one end of described conductive plunger 105 is electrically connected with described pad 104; Be positioned at the plastic packaging layer 106 on described carrier 100 surface, described plastic packaging layer 106 surrounds described chip 101, and described plastic packaging layer 106 exposes described pad 104; Be positioned at the wiring layer again 107 on described plastic packaging layer 106 surface, described wiring layer again 107 is electrically connected with described pad 104; The soldered ball 108 on wiring layer 107 surface again described in being positioned at.
Wherein, described conductive plunger 105 is usually formed in cutting and is independently formed before chip 101; The forming step of described conductive plunger 105 comprises: provide substrate, and described substrate has functional surfaces, and described substrate comprises some chip region; Etching technics is adopted to form through hole from described functional surfaces in the chip region of described substrate; In sidewall and lower surface formation insulating barrier (sign) of described through hole; Surface of insulating layer in described through hole forms conductive plunger 105; Polishing is carried out, until expose an end position of described conductive plunger 105 from described substrate and functional surfaces apparent surface; After described glossing, cut described substrate, make some chip region form independently chip 101.
But, in the process forming described conductive plunger 105, need to form through hole in substrate, and the degree of depth of described through hole is formed chip 101 thickness, therefore the degree of depth of described through hole is comparatively dark, and the depth-to-width ratio of described through hole is higher, therefore, require higher to the etching technics forming described through hole, the difficulty of described etching technics is larger.And filled conductive material is to form conductive plunger 105 in described through hole for follow-up needs, and the depth-to-width ratio of described through hole is higher, the filling difficulty of described electric conducting material is comparatively large, higher for the technological requirement forming conductive plunger 105.In addition, the process costs that the etching technics of above-mentioned high-aspect-ratio and high aspect ratio vias fill is realized higher.To sum up, because the technology difficulty of through-silicon via structure is higher, technique is comparatively complicated, and process costs is higher, is applied to stacked chips encapsulation causes restriction for silicon through hole technology.
In order to reduce technology difficulty, also been proposed a kind of plastic packaging through hole technology.Please refer to Fig. 2, Fig. 2 introduces plastic packaging through-hole structure to realize the cross-sectional view of chip chamber conducting in encapsulating structure, comprising: carrier 110; Be fixed on the chip 111 on carrier 110 surface, described chip 111 comprises relative non-functional face 112 and functional surfaces 113, and the non-functional face 112 of described chip 111 contacts with carrier 110 surface, and functional surfaces 113 surface of described chip 111 has pad 114; Be positioned at the plastic packaging layer 115 on described carrier 110 surface, described plastic packaging layer 115 surrounds described chip 111, and described plastic packaging layer 115 exposes described pad 114; Run through the conductive plunger 116 of described plastic packaging layer 115; Be positioned at the wiring layer again 117 on described plastic packaging layer 115 surface, described wiring layer again 117 is electrically connected with described pad 114 and conductive plunger 116; The soldered ball 118 on wiring layer 117 surface again described in being positioned at.
Wherein, the forming step of described conductive plunger 116 comprises: adopt etching technics in described plastic packaging layer 115, form the through hole being through to carrier 110 surface; Conductive plunger 116 is formed in described through hole.
But due to the thickness of described plastic packaging layer 115 and the thickness of described chip 111, and described through hole runs through described plastic packaging layer 115, therefore the degree of depth of described through hole is comparatively dark, and the depth-to-width ratio of described through hole is higher; Have higher required precision to the etching technics forming described through hole, the difficulty of described etching technics is larger.Secondly, due to follow-up needs, in described through hole, filled conductive material is to form conductive plunger 116, and the depth-to-width ratio of described through hole is higher, causes the difficulty of filling described electric conducting material larger.And, because described conductive plunger 116 is formed at around described chip 111, therefore, need accurately to be decided to be the position of described conductive plunger 116 relative to chip, therefore, higher for positioning accuracy request when forming described through hole.To sum up, even if adopt plastic packaging through hole technology to realize stacked chips encapsulation, be still faced with complex process, technology difficulty is higher and cost is higher problem.
In order to solve the problem, the invention provides a kind of formation method of encapsulating structure, comprising: provide carrier, described carrier has chip region, and described carrier has the 3rd relative surface and the 4th surface; In described carrier, form one or several slots, described slot is positioned at around described chip region, and described slot top is positioned at described 3rd surface; At the 3rd surperficial fixed chip of described support core section, described chip has relative first surface and second surface, and the second surface of described chip comprises functional areas, and the first surface of described chip and the 3rd surface of carrier interfix; At described slot internal fixtion connecting key, described connecting key comprises conductor wire, described connecting key comprises first end and the second end, first end and second end of described connecting key expose described conductor wire, the first end of described connecting key is positioned at described slot, and the second end of described connecting key flushes in surface, the functional areas of described chip; Form plastic packaging layer on the 3rd surface of described carrier, described plastic packaging layer surrounds described chip and connecting key, and the surface of described plastic packaging layer exposes the second end of described connecting key and the surface, functional areas of chip; Carry out thinning, until expose the second end of described connecting key to described the 4th surface at carrier; Form wiring layer again on described plastic packaging layer surface, described wiring layer is again electrically connected with the second end of described connecting key and the functional areas of chip; The first soldered ball is formed on the described surface of wiring layer again.
Wherein, there is in described carrier the slot be positioned at around chip region, and described slot top is positioned at carrier the 3rd surface.Described slot is used for being fixedly connected with key, makes described connecting key be positioned at chip circumference, and described chip is fixed on the 3rd surface of support core section.First end due to described connecting key is positioned at described slot, therefore the contact stabilization between described connecting key and described carrier, in subsequent technique, described connecting key is not easily subjected to displacement, thus ensure that the relative position between described connecting key and chip is accurate, between the functional areas being conducive to wiring layer and connecting key or chip again described in avoiding, occurrence positions offsets, and then ensure that the electrical connection between the wiring layer again of follow-up formation and described connecting key and chip functions district is stablized.Described connecting key comprises conductor wire, and the first end of described connecting key and the second end all expose conductor wire; After the first end of described connecting key is fixed in slot, second end of described connecting key can flush the functional surfaces in described chip, therefore, after described carrier surface formation exposes the plastic packaging floor in chip functions district, second end of described connecting key also can flush in described plastic packaging layer surface, make described conductor wire can be through in the slot of carrier from described plastic packaging layer surface, realize the electrical connection of chip first surface to second surface with this.Because described connecting key is fixed in the slot of carrier, avoid the follow-up step that plastic packaging layer is processed, the formation process of encapsulating structure can be made to simplify.To sum up, the formation method processing step of described encapsulating structure simplifies, process costs reduces, technology difficulty reduces, and the size of the encapsulating structure formed is more accurate, is conducive to the size reducing encapsulating structure.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 3 to Figure 18 is the structural representation of the forming process of the encapsulating structure of the embodiment of the present invention.
Please refer to Fig. 3, provide carrier 200, described carrier 200 has chip region 201, and described carrier 200 has the 3rd relative surface 203 and the 4th surface 204.
Described carrier 200 provides workbench for subsequent technique, for the plastic packaging layer of carries chips and follow-up formation.
In the present embodiment, described carrier 200 is rigid substrate, and described rigid substrate is glass substrate, semiconductor substrate or polymeric substrates.Described rigid substrate has higher hardness, not easily deformation occurs, and is enough to supporting chip and plastic packaging layer in subsequent technique.In another embodiment, described carrier 200 can also be PCB substrate or metal substrate.
3rd surface 203 of described carrier 200 is for fixing with chip; The chip 200 of described carrier 200 is namely for the region of fixed chip.Chip region 201 quantity in described carrier 200 is more than or equal to 1; When the quantity of described chip region 201 is greater than 1, the region between adjacent core section 201 can be used in cutting, makes some chip region 201 separate.
In the present embodiment, follow-uply in carrier 200, form slot, and described slot is used for being fixedly connected with key, and therefore described carrier 200 needs to have enough large hardness, to ensure that connecting key can not be subjected to displacement described in subsequent technique.
Please refer to Fig. 4 and Fig. 5, Fig. 4 is the cross-sectional view of Fig. 5 along AA ' direction, in described carrier 200, form one or several slots 202, described slot 202 is positioned at around described chip region 201, and described slot 202 top is positioned at described 3rd surface 203.
Described slot 202 is follow-up for being fixedly connected with key, and described connecting key is for the electrical connection of the first surface to second surface that realize chip.
In the present embodiment, one or several slots 202 are formed in the carrier 200 around each described chip region 201.And when having some slots 202 around a chip region 201, and when the follow-up chip surface being fixed on carrier 200 surface has some pads, the position of some slots 202 can be mutually corresponding with some pads.In the present embodiment, around a chip region 201,4 slots 202 are formed.
The forming step of described slot 202 comprises: form mask layer on described carrier 200 surface, described mask layer exposes the subregion around chip region 201; With described mask layer for mask, etch described carrier 200, in described carrier 200, form slot 202; After the described slot 202 of formation, remove described mask layer.
In one embodiment, described mask layer is patterned photoresist layer, and described mask layer adopts coating process and litho developing process to be formed.In another embodiment, the material of described mask layer is one or more in silicon nitride, silicon oxynitride, titanium nitride, tantalum nitride and amorphous carbon; Described mask layer by with patterned photoresist layer for mask etching is formed.
The technique etching described carrier 200 is anisotropic dry etch process.In the present embodiment, the sidewalls orthogonal of the slot 202 formed is in the 3rd surface 203 of carrier 200.In other embodiments, the sidewall of described slot 202 can also favour described 3rd surface 203, and the size at the top of described slot 202 is more than or equal to the connecting key first end size of follow-up setting.
The degree of depth of described slot 202 is less than the thickness of described carrier 200, the i.e. non-through described carrier 200 of described slot 202, when follow-up after described slot 202 internal fixtion connecting key, the bottom of described slot 202 can be used in carrying described connecting key, avoids described connecting key to be subjected to displacement on the direction perpendicular to carrier 200 the 3rd surface 203.
Please refer to Fig. 6, at the 3rd surperficial 203 fixed chips 210 of described carrier 200 chip region 201, described chip 210 has relative first surface 211 and second surface 212, the second surface 212 of described chip 210 comprises functional areas, and the first surface 211 of described chip 210 interfixes with the 3rd surface 203 of carrier 200.
The first surface 211 of described chip 210 is fixed on described carrier 200 surface by tack coat (not shown).The material of described tack coat is UV glue or other cohesive material.
In one embodiment, adhere to tack coat at the first surface 211 of described chip 210, more described tack coat is adhered to the 3rd surface 203 of carrier 200, to realize the bonding between chip 210 and carrier 200.And the first surface 211 of described chip 210 does not have functional areas, namely the first surface 210 of described chip 210 does not expose electric connection structure, after chip 210 first surface 211 is fixed on carrier 200 surface, the functional areas of the second surface 212 of chip 210 can be exposed.
In another embodiment, the correspondence position of fixing induction chip 210 can also be needed tack coat is formed on the surface of described carrier 200, again the first surface 211 of described induction chip 210 is adhered to described tie layer surface, make induction chip 210 be fixed on carrier 200 surface.
Described chip 210 can be sensor chip, logic circuit chip, storage chip etc.Can have in transistor, passive device (such as resistance, electric capacity and inductance etc.), memory device, transducer, electric interconnection structure in the functional areas of described chip 210 second surface 212 one or more.
The forming step of described chip 210 comprises: provide substrate, and described substrate has some chip region, and described substrate comprises relative first surface and second surface, has functional areas in the chip region of described substrate second surface; Described substrate is cut, some chip region are separated from each other, form independently chip 210.
In the present embodiment, the surface, functional areas of described chip 210 exposes pad; Described bond pad surface has projection 213, and the top surface of described projection 213 protrudes from the second surface 212 of described chip 210, the top surface of described projection 213 and the surface, functional areas of described chip 210.The material of described projection 213 comprises copper, gold or tin, and described projection 213 has preset thickness.Described projection 213 can realize being electrically connected with the circuit in functional areas or device.Described projection 213 for being electrically connected with the connecting key of follow-up setting, thus realizes the electrical connection between the functional areas of chip 210 and other chip or external circuit.In the present embodiment, the surface, functional areas of described chip 210 and the top surface of described projection 213.In other embodiments, described functional areas can also be sensor region, have transducer in described sensor region, and described transducer is for obtaining the information in external environment condition.
Please refer to Fig. 7, at described slot 202 internal fixtion connecting key 220, described connecting key 220 comprises conductor wire 223, described connecting key 220 comprises first end 221 and the second end 222, the first end 221 of described connecting key 220 and the second end 222 expose described conductor wire 223, the first end 221 of described connecting key 220 is positioned at described slot 202 (as shown in Figure 6), and the second end 222 of described connecting key 220 flushes in surface, the functional areas of described chip 210.
The size at the top of described slot 202 is more than or equal to the size of described connecting key 220 first end 221, and described connecting key 220 interfixes with described carrier 200 by inserting described slot 202.
In one embodiment, the top dimension of described slot 202 is greater than first end 221 size of described connecting key 220, and the sidewalls orthogonal of described slot 202 is in the 3rd surface 203 of carrier 200, after described connecting key 220 is inserted in described slot 202, can also, at described slot 202 fill insulant, make the combination between described connecting key 220 and carrier 200 more firm.
In another embodiment, the top dimension of described slot 202 equals the size of the first end 221 of described connecting key 220, and the first end 221 of described connecting key 220 can be interfixed by tack coat and slot 202.The material of described tack coat is the sticking material of tool, such as UV glue.
By forming slot 202 in described carrier 200, and at described slot 202 internal fixtion connecting key 220, the combination between described connecting key 220 and carrier 200 can be made more firm, and the displacement of described connecting key 220 can be reduced in subsequent technique, with this make the relative position between described connecting key 220 and chip 210 and distance more accurate, can avoid offseting between the wiring layer again of follow-up formation and the projection 213 of described connecting key 220 or chip 210, be conducive to ensureing follow-up formation wiring layer again can and between described connecting key and projection 213 electrical connection properties good.
In the present embodiment, the surface, functional areas of described chip 210 and the top surface of described projection 213, and after the first end 221 of slot 202 internal fixtion connecting key 220, second end 222 surface of connecting key 220 flushes in surface, the functional areas of described chip 210, and namely the second end 222 surface of described connecting key 220 flushes the top surface in described projection 213.
Owing to being formed with one or several slots 202 in the carrier 200 around a chip region 201, then around a chip 210, fix one or several connecting keys 220; When connecting key 220 quantity around a chip 210 is greater than 1, the quantity of described connecting key 220 can be consistent with projection 213 quantity on chip 210 surface, and the position of described connecting key 220 is corresponding with projection 213 position on described chip 210 surface.
The first end 221 of described connecting key 220 and the second end 222 expose conductor wire 223, by the first end 221 of described connecting key 220 be fixed in slot 202 after, conductor wire 223 and described carrier 200 that described connecting key 220 first end 221 exposes interfix, and conductor wire 223 surface that described second end 222 exposes flushes the top surface in described projection 213.Follow-up after plastic packaging layer surface forms wiring layer again, described wiring layer again can realize the electrical connection between conductor wire 223 that described second end 222 exposes and projection 213, thus enables projection 213 realize electrical connection to carrier 200 surface.
Because described connecting key 220 is directly fixed in slot 202, avoid after follow-up formation plastic packaging layer, then carry out routing technique or carry out the forming step of plastic packaging through-hole structure, can Simplified flowsheet step, and reduce technology difficulty, thus can reduce costs.And described connecting key 220 is directly fixed in slot 202, make described connecting key 220 more accurate relative to the position of chip 210, avoid in the process forming plastic packaging through-hole structure, the error problem produced during etching through hole.In addition, the second end 222 of described connecting key 220 flushes the top surface in described projection 213, then the surface of the plastic packaging layer of follow-up formation can flush in described bond pad surface; Compared in routing technique, plastic packaging layer surface needs the problem higher than chip surface, and the plastic packaging layer thickness of the follow-up formation of the present embodiment is thinner, is conducive to the gauge of thinning formed encapsulating structure.
In the present embodiment, the distance of described connecting key 220 first end 221 to the second end 222 is 40 microns ~ 400 microns; The distance of described connecting key 220 first end 221 to the second end 222 is greater than the thickness of described chip 210, and the thickness of described chip 210 is the distance of described projection 213 top surface to the first surface 211 of chip 210.Can ensure that, after follow-up formation plastic packaging layer, described plastic packaging layer surface can flush with pad 221 top surface thus, described plastic packaging layer can expose the second end 222 of connecting key 220 simultaneously.
The material of described conductor wire 223 is electric conducting material, and described conductor wire 223 is for realizing the conducting of chip 210 from first surface 211 to second surface 212; Described electric conducting material comprises for copper, tungsten, aluminium, gold or silver-colored.
In the present embodiment, described connecting key 220 also comprises the protective layer 224 being positioned at described conductor wire 223 sidewall surfaces, and described protective layer 224 exposes the conductor wire 223 of described connecting key 220 first end 221 and the second end 222.
In another embodiment, described connecting key can not also comprise described protective layer, and only has described conductor wire.
The material of described protective layer 224 is insulating material.Described insulating material is organic insulating material or inorganic insulating material; Described organic insulating material comprises polyvinyl chloride or resin; Described resin comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; Described inorganic insulating material comprise in silica, silicon nitride and silicon oxynitride one or more.
Described protective layer 224 can not only in the slot 202 connecting key 220 being fixed on carrier 200 time; for the protection of the surface of described conductor wire 223 from damage; and the sectional dimension of described connecting key 220 can be increased; thus aim at connecting key 220 being inserted described slot 202 Nei Shigengyi, make the connecting key 220 being fixed on carrier 200 surface more accurate relative to the position of chip 210.
In the present embodiment, first end 221 size of described connecting key 220 and the second end 222 measure-alike.Conductor wire 223 size of described connecting key 220 first end 221 and the conductor wire 223 of the second end 222 measure-alike.Wherein, described conductor wire 223 diameter is 30 microns ~ 150 microns, and the thickness of described protective layer 224 is 10 nanometer ~ 10 micron; When the material of described conductor wire 223 is copper, the minimum diameter of described conductor wire 223 is 30 microns; When the material of described conductor wire 223 is aluminium, the minimum diameter of described conductor wire 223 is 100 microns.
In the present embodiment, described conductor wire 223 is cylindrical, and namely the cross section of described conductor wire 223 is circular, and the first end 221 of described connecting key 220 and the second end 222 expose described columniform conductor wire 223 two ends respectively; Described connecting key 220 first end 221 and conductor wire 223 size of the second end 222 and the diameter of described cylindrical conductive line 223.
In the present embodiment, described columniform conductor wire 223 is identical from connecting key 203 first end 221 to the second end 222 diameter.
In the present embodiment; described conductor wire 223 sidewall surfaces is also coated with protective layer 224; and the thickness of described protective layer 224 is homogeneous, thus after described conductor wire 223 Surface coating protective layer 224, described connecting key 220 is still identical from the size of first end 221 to the second end 222.
In other embodiments, the size of the second end of described connecting key can also be less than the size of described first end.
Be described below with reference to the forming step of accompanying drawing to described connecting key.
Please refer to Fig. 8, provide initial conduction line 300, described initial conduction line 300 has the 3rd end 303 and the 4th end 304.
Described initial conduction line 300 forms conductor wire 230 (as shown in Figure 5) for cutting.The material of described initial conduction line 300 is electric conducting material; Described electric conducting material comprises for copper, tungsten, aluminium, gold or silver-colored.Described initial conduction line 300 diameter is 30 microns ~ 150 microns.
In the present embodiment, described initial conduction line 300 is cylindrical, and namely the cross section of described initial conduction line 300 is circular; And described initial conduction line 300 is from measure-alike to the 4th end 304 of the 3rd end 303, namely described columniform conductor wire 300 is identical to the diameter of the 4th end 304 from the 3rd end 303.
Please refer to Fig. 9, form initial protective layers 301 in the sidewall surfaces of described initial conduction line 300, form initial connecting key 302, described initial protective layers 301 exposes the 3rd end 303 and the 4th end 304 of described initial conduction line 300.
The material of described initial protective layers 301 is insulating material; Described insulating material is organic insulating material or inorganic insulating material.The formation process of described initial protective layers 301 comprises chemical vapor deposition method, physical gas-phase deposition, atom layer deposition process, spraying coating process or Shooting Technique.
In one embodiment, when the material of described initial protective layers 301 is organic insulating material, described organic insulating material comprises polyvinyl chloride or resin; Described resin comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; The formation process of described initial protective layers 301 can be spraying coating process or Shooting Technique.
In another embodiment, the material of described initial protective layers 301 is inorganic insulating material, described inorganic insulating material comprise in silica, silicon nitride and silicon oxynitride one or more; The formation process of described initial protective layers 301 can chemical vapor deposition method, physical gas-phase deposition, atom layer deposition process; And the technique forming described initial protective layers 301 needs to have good covering power and uniformity, make formed initial protective layers 301 can be covered in the surface of described initial conduction line 300 equably.
Please refer to Figure 10; cut described initial protective layers 301 (as shown in Figure 9) and initial conduction line 300 along the direction perpendicular to described initial conduction line 300 (as shown in Figure 9) sidewall, form some sections of conductor wires 223 and be positioned at the protective layer 224 of conductor wire 223 sidewall surfaces.
In the present embodiment, the sidewall surfaces of described initial conduction line 300 is the surface around described axis B (as shown in Figure 7), and described axis B is the central shaft through the 3rd end 303 and the 4th end 304 in described initial conduction line 300; Namely described initial protective layers 301 and initial conduction line 300 is cut along the direction perpendicular to axis B along the direction cutting perpendicular to described initial conduction line 300 sidewall.
Described cutting technique can be laser cutting parameter.After cutting technique, described initial protective layers 301 and initial conduction line 300 form some discrete connecting keys 220.
Please refer to Figure 11, plastic packaging layer 230 is formed on the 3rd surface 203 of described carrier 200, described plastic packaging layer 230 surrounds described chip 210 and connecting key 220, and the surface of described plastic packaging layer 230 exposes the second end 222 of described connecting key 220 and the surface, functional areas of chip 210.
In the present embodiment, the surface of described plastic packaging layer 230 flushes with projection 213 top surface of described chip 210 second surface 212, and namely described plastic packaging layer 230 exposes the top surface of described projection 213.The second end 222 due to described connecting key 220 flushes the top surface in described projection 213, thus described plastic packaging layer 230 can be made to expose the second end 222 of described connecting key 220.Follow-up can by forming the electrical connection that wiring layer again realizes between connecting key 220 and projection 213.
And because the surface of described plastic packaging layer 230 flushes with the top surface of projection 213, the thickness of described plastic packaging layer 230 is identical with the thickness of chip 210, the thinner thickness of described plastic packaging layer 230 can make the gauge of formed encapsulating structure less.
In the present embodiment, the forming step of described plastic packaging layer 230 comprises: the initial plastic packaging layer forming the projection 213 covered on described chip 210 and chip 210 on described carrier 200 surface; Polishing is carried out to described initial plastic packaging layer, till the top surface exposing described projection 213, forms described plastic packaging layer 230.
Described plastic packaging layer 230 can be photosensitive dry film, non-photo-sensing dry film or capsulation material film.
In one embodiment, described plastic packaging layer 230 is photosensitive dry film, and the formation process of described initial plastic packaging layer is vacuum film coating process.
In another is implemented, the material of described plastic packaging layer 230 is capsulation material, and described capsulation material comprises epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol or other suitable polymeric materials.
The formation process of described initial plastic packaging layer comprises Shooting Technique (injectionmolding), turns and mould technique (transfermolding) or silk-screen printing technique.Described Shooting Technique comprises: provide mould; Fill capsulation material in the mold, make the coated described chip 210 of described capsulation material and connecting key 220; Elevated cure is carried out to described capsulation material, forms plastic packaging layer 230.
In other embodiments, described plastic packaging layer 230 material also can be other insulating material.
The follow-up wiring layer be again electrically connected with described connecting key 220 second end 222 and projection 213 in described plastic packaging layer 230 surface formation.In one embodiment, described wiring layer more directly can be formed at described plastic packaging layer 230 surface.In the present embodiment, after described plastic packaging layer 230 surface forms the first insulating barrier, then wiring layer again can be formed in the first surface of insulating layer; Be described below with reference to accompanying drawing.
Please refer to Figure 12, carry out thinning, until expose the first end 221 of described connecting key 220 to described the 4th surface 204 at carrier 200.
First end 221 due to described connecting key 220 inserts in slot 202, and the hardness of described carrier 200 is higher, therefore described carrier 200 is not suitable for being stripped, therefore, need to carry out thinning from the 4th surface 204 of described carrier 200, expose the first end 221 of connecting key 220 with this.
In the present embodiment, carrying out thinning technique to described the 4th surface 204 at carrier 200 is CMP (Chemical Mechanical Polishing) process, till described CMP (Chemical Mechanical Polishing) process proceeds to conductor wire 223 surface exposing first end 221.In another embodiment, described reduction process is etching technics, and described etching technics can be anisotropic dry etch process, isotropic dry etch process or wet-etching technology.
Please refer to Figure 13, form the first insulating barrier 231 on described plastic packaging layer 230 surface, have in described first insulating barrier 231 and expose the conductor wire 223 of described connecting key 220 second end 222 and some first through holes 232 on surface, chip 210 functional areas respectively.
Described first insulating barrier 231 is for the protection of described plastic packaging layer 230 surface; The first through hole 232 in described first insulating barrier 231 is electrically connected with conductor wire 223 and projection 213 for enabling the wiring layer again of follow-up formation.
The forming step of described first insulating barrier 231 comprises: form the first dielectric film on described plastic packaging layer 230, connecting key 220 and projection 213 surface; Carry out graphically, forming the first insulating barrier 231 to described first dielectric film, and in described first insulating barrier 231, there is the first through hole 232.
In one embodiment, the material of described first insulating barrier 231 is polymeric material or inorganic insulating material; Described polymeric material can be insulating resin; Described inorganic insulating material can be one or more combinations in silica, silicon nitride, silicon oxynitride.
Carry out patterned technique to described first dielectric film to comprise: adopt coating process and exposure imaging technique to form patterned photoresist layer at the first insulating film surface; With described first dielectric film of described photoresist layer etching.
The technique etching described first dielectric film is anisotropic dry etch process; The etching gas of described anisotropic dry etch process comprises CH 4, CHF 3, CH 3one or more in F, bias power is greater than 100 watts, and bias voltage is greater than 10 volts.
In another embodiment, the material of the first insulating barrier 231 is photoresist, and described first through hole 232 adopts photoetching process to be formed.
Please refer to Figure 14, in described first through hole 232 (as shown in figure 13) and part first insulating barrier 231 surface formed described in wiring layer 233 again, described wiring layer again 233 is electrically connected with the second end 222 of described connecting key 220 and the functional areas of chip 210.
The forming step of described wiring layer again 233 comprises: in described first through hole 232 and the first insulating barrier 231 surface form conducting film, described conducting film fills full described first through hole 232; Conducting film described in planarization; After flatening process, form patterned layer, described patterned layer cover part conducting film on described conducting film surface; With described patterned layer for mask, etch described conducting film, till exposing the first insulating barrier 231 surface; After the described conducting film of etching, remove described patterned layer.
The material of described conducting film comprise in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride, silver one or more; The technique etching described conducting film is anisotropic dry etch process or wet processing; Described patterned layer can be patterned photoresist layer, can also be patterned hard mask, the material of described hard mask be a kind of in silica, silicon nitride, silicon oxynitride or multiple; Described flatening process can be CMP (Chemical Mechanical Polishing) process.
Described wiring layer again 233 can be single layer structure or sandwich construction, and the wiring layer again 233 of described single layer structure or sandwich construction is for realizing specific circuit function.In the present embodiment, described wiring layer again 233 is single layer structure.In other embodiments, described wiring layer again can be sandwich construction, and with insulating barrier electric isolution between adjacent two layers wiring layer.
Please refer to Figure 15, form the second insulating barrier 234 on described wiring layer again 233 surface, there is in described second insulating barrier 234 the second through hole 235 exposing partly again wiring layer 233.
Described second insulating barrier 234 is solder mask, described second insulating barrier 234 for the protection of described in layer at wiring layer 233, and the second through hole 235 in described second insulating barrier 234 is for defining the position of the first soldered ball of follow-up formation.
The forming step of described second insulating barrier 234 comprises: form the second dielectric film at wiring layer 233 again and the first insulating barrier 232 surface; Carry out graphically, forming the second insulating barrier 234 to described second dielectric film, and in described second insulating barrier 234, there is described second through hole 235.
In one embodiment, the material of described second insulating barrier 234 is polymeric material or inorganic insulating material; Described polymeric material can be insulating resin; Described inorganic insulating material can be one or more combinations in silica, silicon nitride, silicon oxynitride.
Carry out patterned technique to described second dielectric film to comprise: adopt coating process and exposure imaging technique to form patterned photoresist layer at the second insulating film surface; With described first dielectric film of described photoresist layer etching.
The technique etching described second dielectric film is anisotropic dry etch process; The etching gas of described anisotropic dry etch process comprises CH 4, CHF 3, CH 3one or more in F, bias power is greater than 100 watts, and bias voltage is greater than 10 volts.
In another embodiment, the material of the second insulating barrier 234 is photoresist, and described second through hole 235 adopts photoetching process to be formed.
Please refer to Figure 16, wiring layer again 233 surface in described second through hole 235 (with reference to Figure 15) forms described first soldered ball 236.
The material of described first soldered ball 236 comprises tin.The forming step of described first soldered ball 236 comprises: the wiring layer again 233 surface printing tin cream bottom described second through hole 235, then carries out high temperature reflux, under surface tension effects, forms the first soldered ball 236.
In another embodiment, can also electricity wiring layer 233 surface printing scaling powder and soldered ball particle more first bottom described two through holes 235, then high temperature reflux forms the first soldered ball 236.In other embodiments, can also on described wiring layer again 233 electrotinning post, then high temperature reflux forms the first soldered ball 236.
In one embodiment, between described wiring layer again 233 and described first soldered ball 236, metal structure under ball (UnderBallMetal is called for short UBM) can also be had; Under described ball, metal structure can comprise the metal level of single metal layer or multiple-layer overlapped; The material of described single metal layer or more metal layers comprises one or more combinations in copper, aluminium, nickel, cobalt, titanium, tantalum.
Please refer to Figure 17, after thinning described carrier 200, form the second soldered ball 237 on conductor wire 223 surface of described connecting key 220 first end 221.
After forming described second soldered ball 237, the two-sided of encapsulating structure namely realizing being formed plants ball, and the both side surface of described encapsulating structure all can realize stacked package with other packaging body.
In another embodiment, described carrier and have tack coat between described chip 210 and plastic packaging layer 230, before described second soldered ball of formation, can also peel off and remove described carrier; Described carrier can be glass substrate, semiconductor substrate, polymeric substrates, PCB substrate or metal substrate.After described carrier is removed in stripping, the first end 221 of described connecting key 220 protrudes from the first surface of described plastic packaging layer 230 surface and chip 210.Before the described carrier of stripping, can thinning or not thinning described carrier.After the described support plate of stripping, the second soldered ball can be formed on first end 221 surface of described connecting key 220 sidewall surfaces and connecting key 220 that protrude from plastic packaging layer 230 surface.
The material of described second soldered ball 237 comprises tin.The forming step of described second soldered ball 237 comprises: at the conductor wire 223 surface printing tin cream of described connecting key 220 first end 221, then carry out high temperature reflux, under surface tension effects, form the second soldered ball 237.
In another embodiment, can also first at conductor wire 223 surface printing scaling powder and the soldered ball particle of described connecting key 220 first end 221, then high temperature reflux forms the second soldered ball 237.In other embodiments, can also at the zinc-plated post of conductor wire 223 surface electrical of described connecting key 220 first end 221, then high temperature reflux forms the second soldered ball 237.
In another embodiment, please refer to Figure 18, also comprise: provide packaging body 400, described packaging body 400 has the 5th surface 401, and the 5th surface 401 of described packaging body 400 exposes conductive structure 402; The first surface 211 of described chip 210 and plastic packaging layer 230 surface are oppositely arranged with the 5th surface 401 of described packaging body 400, and by welding procedure, described second soldered ball 237 are interconnected with described conductive structure 402.
In described packaging body 400, there is chip or semiconductor device, and described chip or semiconductor device are electrically connected with described conductive structure.Because described conductive structure 402 is electrically connected with chip 210 by the second soldered ball 237 and connecting key 220, thus the chip that can realize in packaging body 400 or semiconductor device are electrically connected with described chip 210, stacked chip package structure is formed with this, and what formed is packaging body stacked structure (PackageOnPackage is called for short POP).
To sum up, in the present embodiment, there is in described carrier the slot be positioned at around chip region, and described slot top is positioned at carrier the 3rd surface.Described slot is used for being fixedly connected with key, makes described connecting key be positioned at chip circumference, and described chip is fixed on the 3rd surface of support core section.First end due to described connecting key is positioned at described slot, therefore the contact stabilization between described connecting key and described carrier, in subsequent technique, described connecting key is not easily subjected to displacement, thus ensure that the relative position between described connecting key and chip is accurate, between the functional areas being conducive to wiring layer and connecting key or chip again described in avoiding, occurrence positions offsets, and then ensure that the electrical connection between the wiring layer again of follow-up formation and described connecting key and chip functions district is stablized.Described connecting key comprises conductor wire, and the first end of described connecting key and the second end all expose conductor wire; After the first end of described connecting key is fixed in slot, second end of described connecting key can flush the functional surfaces in described chip, therefore, after described carrier surface formation exposes the plastic packaging floor in chip functions district, second end of described connecting key also can flush in described plastic packaging layer surface, make described conductor wire can be through in the slot of carrier from described plastic packaging layer surface, realize the electrical connection of chip first surface to second surface with this.Because described connecting key is fixed in the slot of carrier, avoid the follow-up step that plastic packaging layer is processed, the formation process of encapsulating structure can be made to simplify.To sum up, the formation method processing step of described encapsulating structure simplifies, process costs reduces, technology difficulty reduces, and the size of the encapsulating structure formed is more accurate, is conducive to the size reducing encapsulating structure.
And described connecting key also comprises the protective layer being positioned at described conductor wire sidewall surfaces.Described protective layer can not only protect described conductor wire when being inserted in slot by connecting key, can also increase the cross sectional dimensions of connecting key; When being inserted in slot by described connecting key, described connecting key is easier to aim at, and is conducive to ensureing that described connecting key is accurate relative to the position of chip.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (19)

1. a formation method for encapsulating structure, is characterized in that, comprising:
There is provided carrier, described carrier has chip region, and described carrier has the 3rd relative surface and the 4th surface;
In described carrier, form one or several slots, described slot is positioned at around described chip region, and described slot top is positioned at described 3rd surface;
At the 3rd surperficial fixed chip of described support core section, described chip has relative first surface and second surface, and the second surface of described chip comprises functional areas, and the first surface of described chip and the 3rd surface of carrier interfix;
At described slot internal fixtion connecting key, described connecting key comprises conductor wire, described connecting key comprises first end and the second end, first end and second end of described connecting key expose described conductor wire, the first end of described connecting key is positioned at described slot, and the second end of described connecting key flushes in surface, the functional areas of described chip;
Form plastic packaging layer on the 3rd surface of described carrier, described plastic packaging layer surrounds described chip and connecting key, and the surface of described plastic packaging layer exposes the second end of described connecting key and the surface, functional areas of chip;
Carry out thinning, until expose the first end of described connecting key to described the 4th surface at carrier;
Form wiring layer again on described plastic packaging layer surface, described wiring layer is again electrically connected with the second end of described connecting key and the functional areas of chip;
The first soldered ball is formed on the described surface of wiring layer again.
2. the formation method of encapsulating structure as claimed in claim 1, it is characterized in that, described connecting key also comprises the protective layer being positioned at described conductor wire sidewall surfaces, and described protective layer exposes the conductor wire of described connecting key first end and the second end.
3. the formation method of encapsulating structure as claimed in claim 2, it is characterized in that, the forming step of described connecting key comprises: provide initial conduction line, and described initial conduction line has the 3rd end and the 4th end; Form initial protective layers in the sidewall surfaces of described initial conduction line, form initial connecting key, described initial protective layers exposes the 3rd end and the 4th end of described initial conduction line; Cut described initial protective layers and initial conduction line along the direction perpendicular to described initial conduction line sidewall, form some sections of conductor wires and be positioned at the protective layer of conductor wire sidewall surfaces.
4. the formation method of encapsulating structure as claimed in claim 3, it is characterized in that, the formation process of described initial protective layers comprises chemical vapor deposition method, physical gas-phase deposition, atom layer deposition process, spraying coating process or Shooting Technique.
5. the formation method of encapsulating structure as claimed in claim 2, it is characterized in that, the material of described protective layer is insulating material.
6. the formation method of encapsulating structure as claimed in claim 5, it is characterized in that, described insulating material is organic insulating material or inorganic insulating material; Described organic insulating material comprises polyvinyl chloride; Described inorganic insulating material comprise in silica, silicon nitride and silicon oxynitride one or more.
7. the formation method of encapsulating structure as claimed in claim 1, it is characterized in that, first end size and second end of described connecting key are measure-alike; The conductor wire size of described connecting key first end and the conductor wire of the second end measure-alike.
8. the formation method of encapsulating structure as claimed in claim 1, it is characterized in that, described connecting key first end is 40 microns ~ 400 microns to the distance of the second end.
9. the formation method of encapsulating structure as claimed in claim 1, it is characterized in that, the material of described conductor wire is copper, tungsten, aluminium, gold or silver-colored.
10. the formation method of encapsulating structure as claimed in claim 1, is characterized in that having one or several slots in the carrier around each described chip region.
The formation method of 11. encapsulating structures as claimed in claim 1, it is characterized in that, the size at the top of described slot is more than or equal to the size of the first end of described connecting key.
The formation method of 12. encapsulating structures as claimed in claim 1, is characterized in that, the sidewalls orthogonal of described slot is in the 3rd surface of described carrier.
The formation method of 13. encapsulating structures as claimed in claim 1, it is characterized in that, the degree of depth of described slot is less than the thickness of described carrier.
The formation method of 14. encapsulating structures as claimed in claim 1, is characterized in that, carrying out thinning technique to described the 4th surface at carrier is CMP (Chemical Mechanical Polishing) process or etching technics.
The formation method of 15. encapsulating structures as claimed in claim 1, it is characterized in that, the surface, functional areas of described chip exposes pad; Described bond pad surface has projection, and the top surface of described projection protrudes from the second surface of described chip; Described plastic packaging layer exposes the top surface of described projection, the top surface of described projection and the surface, functional areas of described chip.
The formation method of 16. encapsulating structures as claimed in claim 1, it is characterized in that, also comprise: described in formation again before wiring layer, form the first insulating barrier on described plastic packaging layer surface, have in described first insulating barrier and expose the conductor wire of described connecting key second end and some first through holes on surface, chip functions district respectively; In described first through hole and part first surface of insulating layer formed described in wiring layer again.
The formation method of 17. encapsulating structures as claimed in claim 1, it is characterized in that, also comprise: before described first soldered ball of formation, form the second insulating barrier on the described surface of wiring layer again, there is in described second insulating barrier the second through hole exposing partly again wiring layer; Described first soldered ball is formed in described second through hole.
The formation method of 18. encapsulating structures as claimed in claim 1, is characterized in that, also comprise: after thinning described carrier, forms the second soldered ball on the conductor wire surface of described connecting key first end.
The formation method of 19. encapsulating structures as claimed in claim 1, is characterized in that, also comprise: provide packaging body, and described packaging body has the 5th surface, and the 5th surface of described packaging body exposes conductive structure; The first surface of described chip and plastic packaging layer surface are oppositely arranged with the 5th surface of described packaging body, and by welding procedure, described second soldered ball and described conductive structure are interconnected.
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CN115425000A (en) * 2022-09-21 2022-12-02 苏州通富超威半导体有限公司 Packaging structure and forming method thereof

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