CN105097715B - Method and structure for packaging chip by insulating tube - Google Patents
Method and structure for packaging chip by insulating tube Download PDFInfo
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- CN105097715B CN105097715B CN201510413119.6A CN201510413119A CN105097715B CN 105097715 B CN105097715 B CN 105097715B CN 201510413119 A CN201510413119 A CN 201510413119A CN 105097715 B CN105097715 B CN 105097715B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
Abstract
The application discloses a method and a structure for packaging a chip by an insulating tube. The boss of the second electrode is correspondingly and electrically connected with the other end face of the opposite two end faces of the chip through the second electric connection layer, the thickness S and the consumption V of the second buffer layer which is used for sealing the chip and is arranged between the second base and the insulating tube are adjusted according to an internal and external tolerance dimension chain relation formula, the other end face of the opposite two end faces of the second base and the insulating tube are correspondingly sealed, the material consumption V=P.s of the second buffer layer, if the area P of the second buffer layer is controlled to be not more than the cross section area R of the insulating tube through the sealing force during production, the proper consumption V.ltoreq.R of the second buffer layer can be controlled * S, the minimum thickness of the sealed chip and a buffer layer with proper sealing quantity are obtained, so that the small-volume insulating tube packaging structure for the sealed chip is realized.
Description
Technical Field
The application relates to the field of chip packaging, in particular to a method and a structure for packaging a chip by an insulating tube.
Background
In the prior art of packaging the chip by the porcelain tube, because the two electrodes respectively connected with the two end faces of the chip have different height tolerance during manufacturing and tolerance exists during production of the porcelain tube, the height of the electrode sleeve connected with the chip, which is arranged in the porcelain tube and is sealed with the porcelain tube, cannot meet the gap-free matching sealing of the electrode and the porcelain tube and the electrical connection of the largest area between the internal chip and the electrode during actual production. Once the dosage of the sealing material is not well controlled, the phenomena of overflow of the sealing material, poor sealing or chip lack welding and false welding are easily generated before the electrode and the porcelain tube. The overflow of the sealing material directly affects the application production of the product client, if the sealing material with electric conductivity is adopted, the overflow can also affect the service performance of the product, and if the overflow of the conductive sealing material is serious, the application short circuit can be caused; if the sealing material is insufficient, the sealing material is possibly insufficient, so that the airtight sealing of the electrode and the porcelain tube is not realized, and the chip absorbs moisture and even is short-circuited; if a gap exists between the chip and the electrode, the welding area of the chip is insufficient, the through-flow capacity of the chip is affected, in addition, in order to realize the sealing of the chip, another simple realization method in the prior art is to package the chip through resin, and the method is only suitable for packaging small-power chips, and is used for packaging high-power chips, so that the heat productivity of the chip is large when the chip is applied, and the service life of a product is not affected easily due to heat dissipation.
Disclosure of Invention
The embodiment of the application provides a method and a structure for packaging a chip by an insulating tube, which solve the problems that the prior art is easy to cause overflow of sealing materials, poor sealing or chip lack welding and virtual welding before electrodes and porcelain tubes.
In a first aspect, an embodiment of the present application provides a method for packaging a chip with an insulating tube, where two electrodes electrically connected to opposite end surfaces of the chip in one-to-one correspondence are used to seal the opposite end surfaces of the insulating tube in one-to-one correspondence, and seal the chip, where the two electrodes are a first electrode and a second electrode, the first electrode includes a first base, the second electrode includes a second base, and the second electrode further includes a boss protruding on a first end surface of the second base; the method comprises the following steps:
s110, fixing a connecting end face of the chip electrically connected to the first electrode through a first electrical connection layer, wherein the connecting end face of the first electrode is used for being electrically connected with one of two opposite end faces of the chip;
s120, fixing the second electric connection layer to be connected to the other end face of the two opposite end faces of the chip;
and before/after step S120 or step S110, the method further comprises:
A. Sealing the first base and one end face of the opposite end faces of the insulating tube in a corresponding manner through a first buffer layer arranged between the first base and the insulating tube;
the method further comprises the steps of:
s130, correspondingly and electrically connecting the boss of the second electrode with the other end face of the opposite end faces of the chip through the second electric connection layer, and correspondingly sealing the second base and the other end face of the opposite end faces of the insulating tube by adjusting the thickness S and the consumption V of a second buffer layer which is used for sealing the chip and is arranged between the second base and the insulating tube according to an internal and external tolerance dimension chain relation formula;
wherein, the inside and outside tolerance dimension chain relation formula is as follows:
S≥max{(H1+|H2|+D1+|D2|)，(T1+|T2|+d1+|d2|)}；S≤0.4mm；H+D＝T+S+D；V＝S*P；
the P is the area of the second buffer layer, the P is smaller than or equal to the cross-sectional area of the insulating tube, the radial height of the second base is T, the sum of the radial height of the boss of the second electrode and the radial height of the second base is H, the radial height between the outer end surface of the first base opposite to the connecting end surface and the insulating tube and between the outer end surface and the insulating tube is D, the radial height between the outer end surface of the first base and the second electrical connection layer is D, H1 and H2 are respectively the upper deviation and the lower deviation of H, D1 and D2 are respectively the upper deviation and the lower deviation of D, T1 and T2 are respectively the upper deviation and the lower deviation of T, and D1 and D2 are respectively the upper deviation and the lower deviation of D.
With reference to the first aspect, in a first possible implementation manner, the first electrode is a boss electrode, the first electrode further includes a first boss protruding on an inner surface of the first base, the connection end surface of the first electrode is an end surface of the first boss that is correspondingly and electrically connected with the chip through the first electrical connection layer, and the outer end surface of the first electrode is an outer surface of the first base opposite to the end surface of the first boss.
With reference to the first aspect, in a second possible implementation manner, the first electrode is a planar electrode, the connection end surface of the first electrode is an inner surface of the first base, which is correspondingly and electrically connected to the chip through the first electrical connection layer, and the outer end surface of the first electrode is an outer surface opposite to the inner surface of the first base.
With reference to the first aspect or based on the first possible implementation manner or the second possible implementation manner of the first aspect, in a third possible implementation manner, the step 130, that is, electrically connecting the boss of the second electrode with the other end face of the opposite two end faces of the chip through the second electrical connection layer, and adjusting, according to an inside-outside tolerance dimension chain relation formula, a thickness S and an amount V of a second buffer layer for sealing the chip, where the second buffer layer is disposed between the second base and the insulating tube, and correspondingly sealing the second base with the other end face of the opposite two end faces of the insulating tube, includes:
Correspondingly and electrically connecting the boss of the second electrode with the other end face of the two opposite end faces of the chip through the second electric connection layer;
adjusting the thickness S and the consumption V of a second buffer layer which is used for sealing the chip and is arranged between the second base and the insulating tube according to an internal and external tolerance dimension chain relation formula to obtain a product to be sealed;
inverting the product to be sealed to enable the second electrode to be positioned at the lowest part of the product to be sealed, and correspondingly sealing the second base and the other end face of the two opposite end faces of the insulating tube by adopting a solidification sealing process.
With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner, inverting the product to be sealed so that the second electrode is located at the lowest part of the product to be sealed, and correspondingly sealing the second base and the other end face of the opposite two end faces of the insulating tube by using a curing sealing process, including:
inverting the product to be sealed to enable the second electrode to be positioned at the lowest layer of the product to be sealed, and adopting a solidification sealing process to correspondingly seal the second base and the other end face of the opposite two end faces of the insulating tube in a gas discharge tube sealing furnace.
With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner, a sealing temperature of the gas discharge tube sealing furnace is 265-400 ℃.
With reference to the fifth possible implementation manner of the first aspect, in a sixth possible implementation manner, the insulating tube is a ceramic tube, and the first buffer layer and the second buffer layer are solder layers or adhesive layers or solder paste layers; the first electrical connection layer and the second electrical connection layer are solder layers, adhesive or solder paste layers.
With reference to the sixth possible implementation manner of the first aspect, in a seventh possible implementation manner, the method further includes
Encapsulating the insulating tube, the first electrode, the second electrode except for the outer surfaces of the first electrode, the second electrode.
In a second aspect, an embodiment of the present application provides a structure of an insulating tube packaged chip, including a cavity and a chip sealed in the cavity, where the cavity includes an insulating tube, and a first electrode and a second electrode for sealing the insulating tube; the cavity further comprises:
a first buffer layer for hermetically connecting one end surface of the insulating tube and the first electrode;
A second buffer layer for hermetically connecting the other end face of the insulating tube and the second electrode;
the first electrode and the second electrode are electrically connected with the opposite two end surfaces of the chip in a one-to-one correspondence manner through a first electrical connection layer and a second electrical connection layer; the connecting end face of the first electrode is used for being electrically connected with one end face of the opposite end faces of the chip;
the first electrode comprises a first base, the second electrode comprises a second base, the second electrode further comprises a boss protruding on the first end face of the second base, and the thickness of the second buffer layer is obtained through the following inside and outside tolerance dimension chain relation formula:
S≥max{(H1+|H2|+D1+|D2|)，(T1+|T2|+d1+|d2|)}；S≤0.4mm；H+D＝T+S+D；
the diameter height of the second base is T, the sum of the diameter height of the boss of the second electrode and the diameter height of the second base is H, the diameter height from the outer end surface of the first base opposite to the connecting end surface to the insulating tube and between the insulating tube and the insulating tube is D, the diameter height from the outer end surface of the first base to the second electric connecting layer and between the outer end surface of the first base and the second electric connecting layer is D, H1 and H2 are respectively upper deviation and lower deviation of H, D1 and D2 are respectively upper deviation and lower deviation of D, T1 and T2 are respectively upper deviation and lower deviation of T, and D1 and D2 are respectively upper deviation and lower deviation of D.
With reference to the second aspect, in a first possible implementation manner, the first electrode is a boss electrode, the first electrode further includes a first boss protruding on an inner surface of the first base, the connection end surface of the first electrode is an end surface of the first boss that is correspondingly and electrically connected with the chip through the first electrical connection layer, and the outer end surface of the first electrode is an outer surface of the first base opposite to the end surface of the first boss.
With reference to the second aspect, in a second possible implementation manner, the first electrode is a planar electrode, the connection end surface of the first electrode is an inner surface of the first base, which is correspondingly and electrically connected to the chip through the first electrical connection layer, and the outer end surface of the first electrode is an outer surface opposite to the inner surface of the first base.
With reference to the second aspect or the first possible implementation manner or the second possible implementation manner of the second aspect, in a third possible implementation manner, the insulating tube is a ceramic tube, and the first buffer layer and the second buffer layer are solder layers or adhesive layers or solder paste layers.
With reference to the third possible implementation manner of the second aspect, in a fourth possible implementation manner, the first electrical connection layer and the second electrical connection layer are solder layers or adhesive layers or solder paste layers.
With reference to the fourth possible implementation manner of the second aspect, in a fifth possible implementation manner, the structure further includes an insulating encapsulation body for encapsulating the insulating tube, the first electrode, and the second electrode except for an outer surface of the first electrode and the second electrode.
According to the method for packaging the chip by the insulating tube, the two electrodes which are in one-to-one correspondence with the opposite end surfaces of the chip are in one-to-one correspondence sealing with the opposite end surfaces of the insulating tube, and are used for sealing the chip, wherein the boss of the second electrode is in corresponding electrical connection with the other end surface of the opposite end surfaces of the chip through the second electrical connection layer, the thickness S and the consumption V of a second buffer layer which is used for sealing the chip and is arranged between the second base and the insulating tube are adjusted according to an internal and external tolerance size chain relation formula, and the second base is in corresponding sealing with the other end surface of the opposite end surfaces of the insulating tube; wherein, the inside and outside tolerance dimension chain relation formula is as follows: s is greater than or equal to max { (H1+|H2|+D1+|D2|) } (T1+|T2|+d1+|d2|); s is less than or equal to 0.4mm; h+d=t+s+d, In the embodiment of the application, if the material consumption V=P.s of the second buffer layer is controlled by sealing force to ensure that the area P of the second buffer layer is not larger than the cross section area R of the insulating tube during production, the buffer layer which can seal the chip and has the minimum thickness and the proper sealing consumption can be obtained by controlling the proper consumption V.ltoreq.R.s of the second buffer layer, thereby meeting the electric connection of the electrode and the porcelain tube with the largest area between the internal chip and the electrode in a gap-free matching sealing way, realizing the small-volume insulating tube packaging structure for sealing the chip, solving the phenomena of overflow of the sealing material, poor sealing or chip lack welding and lack welding before the electrode and the porcelain tube, and preventing the chip from moisture absorption and even short circuit; in addition, the electrical connection of the maximum area between the chip and the electrode is increased to promote the chipThrough-flow capability of (2).
In addition, the embodiment of the application adopts the ceramic package chip, so that the heat dissipation problem of the resin package high-power chip can be solved while the small-volume insulating tube package structure for sealing the chip is realized.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1a is a flowchart of a method for packaging a chip with an insulating tube according to an embodiment of the present application;
fig. 1b is a structural dimension identification diagram of an insulating tube packaged chip according to an embodiment of the present application;
FIG. 1c is a flowchart of another method for packaging a chip with an insulating tube according to an embodiment of the present application;
fig. 1d is a structural dimension identification diagram of an insulating tube packaged chip according to an embodiment of the present application;
fig. 1e is a flowchart of another method for packaging a chip with an insulating tube according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The following will each explain in detail by means of specific examples.
In the prior art, the ceramic tube packaging chip has tolerance of different heights during manufacturing due to the fact that two electrodes respectively connected with two end faces of the chip are respectively manufactured, and tolerance is also present during production of the ceramic tube, so that in actual production, after the electrodes connected with the chip are sleeved in the ceramic tube, the height of the inner dimension of the ceramic tube during sealing cannot meet the requirement that the outer dimension of the electrodes and the outer dimension of the ceramic tube are sealed in a void-free matching manner. Once the dosage of the sealing material is not well controlled, the phenomenon of overflow or shortage of the sealing material easily occurs. The overflow of the sealing material directly affects the application performance of the product client, and the chip production of the product is also affected along with bad appearance, and the phenomena of the overflow of the sealing material, poor sealing or chip lack welding and virtual welding are easy to occur before the electrode and the porcelain tube. In order to solve the problem that the chip cannot be sealed in the prior art, the embodiment provides a method for packaging the chip by using an insulating tube, namely two electrodes which are electrically connected with opposite end surfaces of the chip in one-to-one correspondence are sealed with opposite end surfaces of the insulating tube in one-to-one correspondence, the effect of sealing the chip is achieved by controlling the thickness and the usage of a buffer layer arranged between the insulating tube and a base of the electrodes, and particularly the thickness S and the usage V of the buffer layer for sealing the chip can be adjusted by an internal tolerance dimension chain relation formula and an external tolerance dimension chain relation formula and by controlling the sealing force. Wherein each electrode comprises a base and at least one electrode comprises a boss protruding on a first end face of the base. The method for packaging the chip by the insulating tube provided by the embodiment comprises the following steps:
S110, fixing and electrically connecting the chip to a connecting end face of the first electrode through the first electric connecting layer, wherein the connecting end face of the first electrode is used for being correspondingly and electrically connected with one of two opposite end faces of the chip;
s120, fixing the second electric connection layer to be connected to the other end face of the two opposite end faces of the chip; and before/after step S120 or step S110, the method further comprises:
A. sealing the base of the first electrode with one end face of the insulating tube opposite to the base of the first electrode through a first buffer layer arranged between the base of the first electrode and the insulating tube; following the above steps, the method further comprises the following step S130:
s130, correspondingly and electrically connecting a boss of the second electrode with the other end face of the opposite two end faces of the chip through the second electric connection layer, and correspondingly sealing the base of the second electrode with the other end face of the opposite two end faces of the insulating tube by adjusting the thickness S and the consumption V of the second buffer layer which is used for sealing the chip and is arranged between the base of the second electrode and the insulating tube according to an inside and outside tolerance dimension chain relation formula.
In this embodiment, the inside and outside tolerance dimension chain relationship formula is as follows:
S≥max{(H1+|H2|+D1+|D2|)，(T1+|T2|+d1+|d2|)}；
S≤0.4mm；
H+D＝T+S+D；
V＝S*P；
in this embodiment, the amount v=s×p, where P is the area of the second buffer layer, P is less than or equal to the cross-sectional area R of the insulating tube, the radial height of the base of the second electrode is T, the sum of the radial height of the boss of the second electrode and the radial height of the base is H, the radial height between the outer end surface of the base of the first electrode opposite to the connecting end surface and the insulating tube and between the outer end surface and the insulating tube is D, and the radial height between the outer end surface of the base of the first electrode and the second electrical connection layer is D. In this embodiment, if the area of the second buffer layer is not greater than R after the material consumption v=p×s of the second buffer layer is controlled by the sealing force during production, the buffer layer with minimum thickness and proper sealing consumption can be obtained by controlling the proper consumption V of the second buffer layer, so as to meet the requirement of void-free matching sealing of the electrode and the porcelain tube and the electrical connection of the largest area between the internal chip and the electrode, realize the small-volume insulating tube packaging structure for sealing the chip, solve the phenomena of overflow of the sealing material, poor sealing or chip lack welding and false welding generated before the electrode and the porcelain tube, and prevent the chip from moisture absorption and even short circuit; in addition, the electrical connection of the maximum area between the chip and the electrode is increased, so that the current passing capability of the chip is improved.
As an optional implementation manner, step S130, namely, electrically connecting the boss of the second electrode with the other end face of the opposite two end faces of the chip correspondingly through the second electrical connection layer, adjusting the thickness S and the amount V of the second buffer layer used for sealing the chip and placed between the second base and the insulating tube according to the inside and outside tolerance dimension chain relation formula, and correspondingly sealing the second base and the other end face of the opposite two end faces of the insulating tube, includes:
s131, correspondingly and electrically connecting the lug boss of the second electrode with the other end face of the two opposite end faces of the chip through the second electric connection layer;
s132, adjusting the thickness S and the dosage V of a second buffer layer which is used for sealing the chip and is arranged between the second base and the insulating tube according to an internal and external tolerance dimension chain relation formula to obtain a product to be sealed;
s133, inverting the product to be sealed to enable the second electrode to be positioned at the lowest part of the product to be sealed, and correspondingly sealing the second base and the other end face of the two opposite end faces of the insulating tube by adopting a solidification sealing process.
As an optional embodiment, step S133, namely inverting the product to be sealed so that the second electrode is located at the lowest part of the product to be sealed, and correspondingly sealing the second base and the other end face of the opposite two end faces of the insulating tube by using a curing sealing process, includes:
Inverting the product to be sealed to enable the second electrode to be positioned at the lowest layer of the product to be sealed, and adopting a solidification sealing process to correspondingly seal the second base and the other end face of the opposite two end faces of the insulating tube in the gas discharge tube sealing furnace.
As an alternative embodiment, the sealing temperature of the gas discharge tube sealing furnace is 265-400 ℃.
As an alternative embodiment, the insulating tube is a ceramic tube, and the first buffer layer and the second buffer layer are solder layers or adhesive layers or solder paste layers.
The embodiment of the application adopts the ceramic packaging chip, realizes a small-volume insulating tube packaging structure for sealing the chip, and can solve the heat dissipation problem of the resin packaging high-power chip.
As an alternative embodiment, the first electrical connection layer and the second electrical connection layer are solder layers or adhesive or solder paste layers.
As an alternative embodiment, the method further comprises:
an insulating tube, a first electrode, and a second electrode are encapsulated except for the outer surfaces of the first electrode and the second electrode.
Specific embodiments are explained below with reference to the drawings.
Referring to fig. 1a, fig. 1a is a flowchart of a method for packaging a chip with an insulating tube according to an embodiment of the application. In the embodiment shown in fig. 1a, the two electrodes are a first electrode and a second electrode, the first electrode is a planar electrode without a boss, and the second electrode is a boss electrode with a boss, that is, a boss is raised on the first end surface of the base of the second electrode. As shown in fig. 1a, the method for packaging a chip with an insulating tube provided in this embodiment includes the following steps:
A. Sealing the base of the first electrode with one end face of the insulating tube opposite to the base of the first electrode through a first buffer layer arranged between the base of the first electrode and the insulating tube;
s110, fixing the chip in the insulating tube through the first electric connection layer to enable the chip to be electrically connected to the connection end face of the first electrode, wherein the connection end face of the first electrode is used for being correspondingly and electrically connected with one of two opposite end faces of the chip;
s120, fixing the second electric connection layer to be connected to the other end face of the two opposite end faces of the chip;
s130, correspondingly and electrically connecting a boss of the second electrode with the other end face of the opposite two end faces of the chip through the second electric connection layer, and correspondingly sealing the base of the second electrode with the other end face of the opposite two end faces of the insulating tube by adjusting the thickness S and the consumption V of the second buffer layer which is used for sealing the chip and is arranged between the base of the second electrode and the insulating tube according to an inside and outside tolerance dimension chain relation formula.
In this embodiment, the first electrode is a planar electrode, so the connection end face of the first electrode is an inner end face of the base of the first electrode, and the inside-outside tolerance dimension chain relation formula in this embodiment is as follows:
S≥max{(H1+|H2|+D1+|D2|)，(T1+|T2|+d1+|d2|)}；
S≤0.4mm；
H+D＝T+S+D；
V＝S*P；
In this embodiment, the material amount v=s×p of the second buffer layer, where P is the area of the second buffer layer, and P is smaller than or equal to the cross-sectional area R of the insulating tube, if the area of the second buffer layer is not greater than R after being controlled by the sealing strength during production, the proper amount V of the second buffer layer is controlled to be less than or equal to r×s, so as to obtain a buffer layer with minimum thickness and proper sealing amount, so as to realize a small-volume insulating tube packaging structure for sealing a chip. Referring to fig. 1b, fig. 1b is a structural dimension identification diagram of an insulation tube packaged chip according to an embodiment of the application. As shown in fig. 1b, the structure of the insulating tube packaged chip in the embodiment includes a cavity 100 and a chip 101 sealed in the cavity 100, the cavity 100 includes two electrodes, namely a first electrode 110 and a second electrode 120, and further includes an insulating tube 130, a first electrical connection layer 140, a second electrical connection layer 141, a first buffer layer 150 and a second buffer layer 151, a radial height of a base of the second electrode 120 is T, a sum of a radial height of a boss of the second electrode 120 and a radial height of the base is H, a connection end face of the first electrode 110 is an inner end face of the base of the first electrode 110, so that a radial height between an outer end face 110a of the base of the first electrode 110 opposite to the connection end face and the insulating tube 130 is D, and a radial height between the outer end face 110a of the base of the first electrode 110 and the second electrical connection layer 141 is D.
In this embodiment, if the material consumption v=p×s of the second buffer layer 151 is controlled by a fixed sealing force during production, the area of the second buffer layer 151 is not greater than R, and the proper consumption V of the second buffer layer 151 is controlled according to an internal and external tolerance dimension chain relation formula, so as to obtain a buffer layer capable of sealing the chip 101 and having a minimum thickness, and a proper sealing consumption, so as to meet the void-free matching sealing of the second electrode 120 and the insulating tube 130 and the electrical connection between the internal chip 101 and the first electrode 110 and the second electrode 120 with the largest area, thereby realizing a small-volume insulating tube packaging structure for sealing the chip 101, solving the phenomena of poor sealing, chip lack welding and false welding caused by the existing sealing material overflow, electrode and porcelain tube, and preventing the chip 101 from moisture absorption and even short circuit; in addition, the electrical connection between the chip 101 and the first electrode 110 and the second electrode 120 with the largest area is increased, so as to improve the current capacity of the chip.
Referring to fig. 1c, fig. 1c is a flowchart of another method for packaging a chip with an insulating tube according to an embodiment of the application. In the embodiment shown in fig. 1c, the two electrodes are a first electrode and a second electrode, the first electrode selected in the embodiment is a boss electrode with a boss, a boss is raised on the inner end surface of the base of the first electrode, the second electrode selected is also a boss electrode, and a boss is raised on the first end surface of the base of the second electrode. As shown in fig. 1c, the method for packaging a chip with an insulating tube provided in this embodiment includes the following steps:
S110, fixing the chip through the first electric connection layer to enable the chip to be electrically connected to the connection end face of the first electrode, wherein the connection end face of the first electrode is used for being correspondingly and electrically connected with one of two opposite end faces of the chip; the chip is placed in an insulating tube.
A. Sealing the base of the first electrode with one end face of the insulating tube opposite to the base of the first electrode through a first buffer layer arranged between the base of the first electrode and the insulating tube;
s120, fixing the second electric connection layer to be connected to the other end face of the two opposite end faces of the chip;
s130, correspondingly and electrically connecting a boss of the second electrode with the other end face of the opposite two end faces of the chip through the second electric connection layer, and correspondingly sealing the base of the second electrode with the other end face of the opposite two end faces of the insulating tube by adjusting the thickness S and the consumption V of the second buffer layer which is used for sealing the chip and is arranged between the base of the second electrode and the insulating tube according to an inside and outside tolerance dimension chain relation formula.
In this embodiment, the first electrode is a boss-type electrode, so the connection end face of the first electrode is an end face of a boss protruding on the inner end face of the base of the first electrode, and the internal and external tolerance dimension chain relation formula in this embodiment is as follows:
S≥max{(H1+|H2|+D1+|D2|)，(T1+|T2|+d1+|d2|)}；
S≤0.4mm；
H+D＝T+S+D；
V＝S*P；
In this embodiment, the material amount v=s×p of the second buffer layer, where P is the area of the second buffer layer, and P is smaller than or equal to the cross-sectional area R of the insulating tube, if the area of the second buffer layer is not greater than R after being controlled by the sealing strength during production, the proper amount V of the second buffer layer is controlled to be less than or equal to r×s, so as to obtain a buffer layer with minimum thickness and proper sealing amount, so as to realize a small-volume insulating tube packaging structure for sealing a chip. Referring to fig. 1d, fig. 1d is a structural dimension identification diagram of an insulation tube packaged chip according to an embodiment of the present application. As shown in fig. 1D, the structure of the insulating tube packaged chip in the embodiment includes a cavity 100 and a chip 101 sealed in the cavity 100, the cavity 100 includes two electrodes, namely a first electrode 110 and a second electrode 120, and further includes an insulating tube 130, a first electrical connection layer 140, a second electrical connection layer 141, a first buffer layer 150 and a second buffer layer 151, a radial height of a base of the second electrode 120 is T, a sum of a radial height of a boss of the second electrode 120 and a radial height of the base is H, a radial height of an outer end surface 110a of the base of the first electrode 110 opposite to a connection end surface, to the insulating tube 130 and therebetween is D, and a radial height from an outer end surface 110a of the base of the first electrode 110 to the second electrical connection layer 141 and therebetween is D.
In this embodiment, if the material consumption v=p×s of the second buffer layer 151 is controlled by the sealing force during production so that the area of the second buffer layer 151 is not larger than R, then a buffer layer with the smallest thickness and suitable sealing consumption can be obtained by controlling the proper consumption V of the second buffer layer 151 to be smaller than R (d+h-T-D), so as to meet the void-free matching sealing of the second electrode 120 and the insulating tube 130 and the electrical connection of the largest area between the internal chip 101 and the first electrode 110 and the second electrode 120, realize the small-volume insulating tube packaging structure for sealing the chip 101, solve the phenomena of poor sealing, chip lack welding and cold welding generated before the existing sealing material overflows, the electrode and the porcelain tube, and prevent the chip from moisture absorption and even short circuit; in addition, the electrical connection between the chip 101 and the first electrode 110 and the second electrode 120 with the largest area is increased, so as to improve the current capacity of the chip.
Referring to fig. 1e, fig. 1e is a flowchart of another method for packaging a chip with an insulating tube according to an embodiment of the application. The two electrodes in this embodiment shown in fig. 1e are a first electrode and a second electrode, where the first electrode selected in this embodiment is a boss-type electrode with a boss, and the second electrode selected further includes a boss protruding from the first end surface of the base of the second electrode. As shown in fig. 1e, the method for packaging a chip with an insulating tube provided in this embodiment includes the following steps:
S110, fixing the chip through the first electric connection layer to enable the chip to be electrically connected to the connection end face of the first electrode, wherein the connection end face of the first electrode is used for being correspondingly and electrically connected with one of two opposite end faces of the chip;
s120, fixing the second electric connection layer to be connected to the other end face of the two opposite end faces of the chip;
A. sealing the base of the first electrode with one end face of the insulating tube opposite to the base of the first electrode through a first buffer layer arranged between the base of the first electrode and the insulating tube; the implementation of this step is to put the chip in an insulating tube;
130. the boss of the second electrode is correspondingly and electrically connected with the other end face of the two opposite end faces of the chip through the second electric connection layer, the thickness S and the consumption V of the second buffer layer which is used for sealing the chip and is arranged between the base of the second electrode and the insulating tube are adjusted according to an internal and external tolerance dimension chain relation formula, and the base of the second electrode is correspondingly sealed with the other end face of the two opposite end faces of the insulating tube.
In this embodiment, the first electrode is a boss-type electrode, so the connection end face of the first electrode is an end face of a boss protruding on the inner end face of the base of the first electrode, and the internal and external tolerance dimension chain relation formula in this embodiment is as follows:
S≥max{(H1+|H2|+D1+|D2|)，(T1+|T2|+d1+|d2|)}；
S≤0.4mm；
H+D＝T+S+D；
V＝S*P；
In this embodiment, the material amount v=s×p of the second buffer layer, where P is the area of the second buffer layer, and P is smaller than or equal to the cross-sectional area R of the insulating tube, if the area of the second buffer layer is not greater than R after being controlled by the sealing strength during production, the proper amount V of the second buffer layer is controlled to be less than or equal to r×s, so as to obtain a buffer layer with minimum thickness and proper sealing amount, so as to realize a small-volume insulating tube packaging structure for sealing a chip. Referring to fig. 1d, fig. 1d is a structural dimension identification diagram of an insulation tube packaged chip according to an embodiment of the present application. As shown in fig. 1D, the structure of the insulating tube packaged chip in the embodiment includes a cavity 100 and a chip 101 sealed in the cavity 100, the cavity 100 includes two electrodes, namely a first electrode 110 and a second electrode 120, and further includes an insulating tube 130, a first electrical connection layer 140, a second electrical connection layer 141, a first buffer layer 150 and a second buffer layer 151, a radial height of a base of the second electrode 120 is T, a sum of a radial height of a boss of the second electrode 120 and a radial height of the base is H, a radial height of an outer end surface 110a of the base of the first electrode 110 opposite to a connection end surface, to the insulating tube 130 and therebetween is D, and a radial height from an outer end surface 110a of the base of the first electrode 110 to the second electrical connection layer 141 and therebetween is D.
In this embodiment, if the material consumption v=p×s of the second buffer layer 151 is controlled by the sealing force during production so that the area of the second buffer layer 151 is not larger than R, then a buffer layer with minimum thickness and suitable sealing consumption can be obtained by controlling the suitable consumption V of the second buffer layer 151, so as to meet the requirement of void-free matching sealing of the second electrode 120 and the insulating tube 130 and the electrical connection of the largest area between the internal chip 101 and the first electrode 110 and the second electrode 120, realize the small-volume insulating tube packaging structure for sealing the chip 101, solve the phenomena of poor sealing or chip lack welding and lack welding before the overflow of the sealing material, the electrode and the porcelain tube, and prevent the chip from moisture absorption and even short circuit; in addition, the electrical connection between the chip 101 and the first electrode 110 and the second electrode 120 with the largest area is increased, so as to improve the current-carrying capability of the chip 101.
Another aspect of an embodiment of the present application provides a structure of an insulating tube packaging chip, including a cavity and a chip sealed in the cavity, the cavity including an insulating tube and a first electrode and a second electrode for sealing the insulating tube; the cavity further comprises:
a first buffer layer for hermetically connecting one end surface of the insulating tube and the first electrode;
A second buffer layer for hermetically connecting the other end surface of the insulating tube and the second electrode;
the first electrode and the second electrode are electrically connected with the opposite two end surfaces of the chip in a one-to-one correspondence manner through the first electrical connection layer and the second electrical connection layer;
the first electrode comprises a first base, the second electrode comprises a second base, the second electrode further comprises a boss protruding on the first end face of the second base, and the thickness of the second buffer layer is obtained through the following inside and outside tolerance dimension chain relation formula:
S≥max{(H1+|H2|+D1+|D2|)，(T1+|T2|+d1+|d2|)}；
S≤0.4mm；
H+D＝T+S+D；
V＝S*P；
in this embodiment, the material consumption v=p×s of the second buffer layer, P is the area of the second buffer layer, P is less than or equal to the cross-sectional area R of the insulating tube, the radial height of the base of the second electrode is T, the sum of the radial height of the boss of the second electrode and the radial height of the base is H, the radial height between the outer end surface of the base of the first electrode opposite to the connecting end surface and the insulating tube and between the outer end surface of the base of the first electrode and the insulating tube is D, and the radial height between the outer end surface of the base of the first electrode and the second electrical connecting layer is D. In this embodiment, if the area of the second buffer layer is controlled to be not greater than R by the sealing strength during production, the buffer layer which can seal the chip and has the minimum thickness and the proper sealing amount can be obtained by controlling the proper amount V of the second buffer layer to be less than or equal to R, so as to meet the requirement of void-free matching sealing of the electrode and the porcelain tube and the electrical connection of the largest area between the internal chip and the electrode, realize the small-volume insulating tube packaging structure for sealing the chip, and solve the phenomena of overflow of the sealing material, poor sealing or chip lack welding and false welding generated before the electrode and the porcelain tube.
As an alternative embodiment, the first electrode is a boss-type electrode, the first electrode further includes a first boss protruding from an inner surface of the first base, the connection end face of the first electrode is an end face of the first boss that is electrically connected to the chip through the first electrical connection layer, and the outer end face of the first electrode is an outer surface of the first base opposite to the end face of the first boss.
As an alternative implementation mode, the first electrode is a planar electrode, the connecting end face of the first electrode is an inner surface of the first base, which is correspondingly and electrically connected with the chip through the first electric connection layer, and the outer end face of the first electrode is an outer surface opposite to the inner surface of the first base.
As an alternative embodiment, the insulating tube is a ceramic tube, and the first buffer layer and the second buffer layer are solder layers or adhesive layers or solder paste layers.
As an alternative embodiment, the first electrical connection layer and the second electrical connection layer are solder layers or adhesive or solder paste layers.
As an alternative embodiment, the structure further comprises an insulating envelope for enveloping the insulating tube, the first electrode, the second electrode, in addition to the outer surfaces of the first electrode, the second electrode.
The structure of the insulating tube packaged chip provided by the embodiment of the present application is described in detail below with reference to fig. 1b and 1 d.
Referring to fig. 1b, as shown in fig. 1b, the structure of the insulating tube packaged chip in the present embodiment includes a cavity 100 and a chip 101 sealed in the cavity 100, wherein the cavity 100 includes an insulating tube 130, two electrodes for sealing the chip 101 in the insulating tube 130, namely a first electrode 110 and a second electrode 120, respectively, and further includes a first electrical connection layer 140, a second electrical connection layer 141, a first buffer layer 150 and a second buffer layer 151. And the first electrode 110 in this embodiment is a planar electrode, and includes only a first base, and the second electrode 120 is a boss-type electrode, which includes a second base and a boss protruding from a first end surface of the second base.
In this embodiment, the first buffer layer 150 is used for sealing and connecting one end face of the insulating tube 130 with the first electrode 110, the second buffer layer 151 is used for sealing and connecting the other end face of the insulating tube 130 with the second electrode 120, and the first electrode 110, the second electrode 120 and two opposite end faces of the chip 101 are electrically connected in a one-to-one correspondence through the first electrical connection layer 140 and the second electrical connection layer 141.
In this embodiment, the first electrode 110 is a planar electrode, the connection end surface of the first electrode 110 is an inner surface of the first base, which is correspondingly and electrically connected to the chip 101 through the first electrical connection layer 140, that is, so the connection end surface of the first electrode 110 is an inner end surface of the first base of the first electrode 110, the outer end surface of the first electrode 110 is an outer surface opposite to the inner surface of the first base, and the thickness of the second buffer layer 151 is obtained by the following inner and outer tolerance dimension chain relation formula:
S≥max{(H1+|H2|+D1+|D2|)，(T1+|T2|+d1+|d2|)}；
S≤0.4mm；
H+D＝T+S+D；
V＝S*P；
In this embodiment, the amount v=s×p, where P is the area of the second buffer layer 151, P is less than or equal to the cross-sectional area R of the insulating tube 130, the radial height of the base of the second electrode 120 is T, the sum of the radial height of the boss of the second electrode 120 and the radial height of the base is H, the connection end face of the first electrode 110 is the inner end face of the base of the first electrode 110, so the radial height from the outer end face 110a of the base of the first electrode 110 opposite to the connection end face to the insulating tube 130 and between them is D, and the radial height from the outer end face 110a of the base of the first electrode 110 to the second electrical connection layer 141 and between them is D. In this embodiment, if the area of the second buffer layer 151 is controlled to be not greater than R by the sealing force during production, a buffer layer with the smallest thickness and a relatively suitable sealing amount, which can seal the chip 101, can be obtained by controlling the appropriate amount V of the second buffer layer 151 to be less than or equal to R, so as to meet the requirement of void-free matching sealing between the second electrode 120 and the insulating tube 130 and the electrical connection between the internal chip 101 and the first electrode 110 and the second electrode 120, and realize a small-volume insulating tube packaging structure for sealing the chip 101, thereby solving the problems of overflow of the sealing material, poor sealing between the electrode and the porcelain tube, or chip lack welding and false welding before the chip is prevented from absorbing moisture and even short-circuiting; in addition, the electrical connection between the chip 101 and the first electrode 110 and the second electrode 120 with the largest area is increased, so as to improve the current-carrying capability of the chip 101.
Referring to fig. 1d, as shown in fig. 1d, the structure of the insulating tube packaged chip in the present embodiment includes a cavity 100 and a chip 101 sealed in the cavity 100, wherein the cavity 100 includes an insulating tube 130, two electrodes for sealing the chip 101 in the insulating tube 130, namely a first electrode 110 and a second electrode 120, respectively, and further includes a first electrical connection layer 140, a second electrical connection layer 141, a first buffer layer 150 and a second buffer layer 151. And the first electrode 110 in this embodiment is a boss electrode, including a first base and a first boss protruding on an inner end surface of the first base, and the second electrode 120 is a boss electrode, including a second base and a second boss protruding on the first end surface of the second base.
In this embodiment, the first buffer layer 150 is used for sealing and connecting one end face of the insulating tube 130 with the first electrode 110, the second buffer layer 151 is used for sealing and connecting the other end face of the insulating tube 130 with the second electrode 120, and the first electrode 110, the second electrode 120 and two opposite end faces of the chip 101 are electrically connected in a one-to-one correspondence through the first electrical connection layer 140 and the second electrical connection layer 141.
In this embodiment, the first electrode 110 is a boss-type electrode, the connection end face of the first electrode 110 is an end face of a first boss that is electrically connected to the chip through the first electrical connection layer 140, so the connection end face of the first electrode 110 is an end face of a boss protruding on an inner end face of the first base of the first electrode 110, an outer end face of the first electrode 110 is an outer surface of the first base opposite to the end face of the first boss, and the thickness of the second buffer layer 151 is obtained by the following inner and outer tolerance dimension chain relation formula:
S≥max{(H1+|H2|+D1+|D2|)，(T1+|T2|+d1+|d2|)}；
S≤0.4mm；
H+D＝T+S+D；
V＝S*P；
In this embodiment, the amount v=s×p, where P is the area of the second buffer layer 151, P is less than or equal to the cross-sectional area R of the insulating tube 130, the radial height of the base of the second electrode 120 is T, the sum of the radial height of the boss of the second electrode 120 and the radial height of the base is H, the connection end face of the first electrode 110 is the inner end face of the base of the first electrode 110, so the radial height from the outer end face 110a of the base of the first electrode 110 opposite to the connection end face to the insulating tube 130 and between them is D, and the radial height from the outer end face 110a of the base of the first electrode 110 to the second electrical connection layer 141 and between them is D. In this embodiment, if the area of the second buffer layer 151 is controlled to be not greater than R by the sealing force during production, a buffer layer with the smallest thickness and a relatively suitable sealing amount, which can seal the chip 101, can be obtained by controlling the appropriate amount V of the second buffer layer 151 to be less than or equal to R, so as to meet the requirement of void-free matching sealing between the second electrode 120 and the insulating tube 130 and the electrical connection between the internal chip 101 and the first electrode 110 and the second electrode 120, and realize a small-volume insulating tube packaging structure for sealing the chip 101, thereby solving the phenomena of overflow of the sealing material, poor sealing between the electrode and the porcelain tube, or chip lack welding and false welding; in addition, the electrical connection between the chip 101 and the first electrode 110 and the second electrode 120 with the largest area is increased, so as to improve the current-carrying capability of the chip 101.
In the embodiments of the present application, it should be understood that the foregoing description is only a specific embodiment of the present application, but the scope of the present application is not limited thereto, and any equivalent modifications or substitutions will be apparent to those skilled in the art within the scope of the present application, and they are intended to be included in the scope of the present application.
Claims (14)
1. The method for packaging the chip by using the insulating tube is characterized in that two electrodes which are in one-to-one correspondence with two opposite end surfaces of the chip are used for sealing the chip in one-to-one correspondence with two opposite end surfaces of the insulating tube, the two electrodes are a first electrode and a second electrode, the first electrode comprises a first base, the second electrode comprises a second base, and the second electrode also comprises a boss protruding on the first end surface of the second base; the method comprises the following steps:
s110, fixing a connecting end face of the chip electrically connected to the first electrode through a first electrical connection layer, wherein the connecting end face of the first electrode is used for being electrically connected with one of two opposite end faces of the chip;
S120, fixing the second electric connection layer to be connected to the other end face of the two opposite end faces of the chip;
and before/after step S120 or step S110, the method further comprises:
A. sealing the first base and one end face of the opposite end faces of the insulating tube in a corresponding manner through a first buffer layer arranged between the first base and the insulating tube;
the method further comprises the steps of:
s130, correspondingly and electrically connecting the boss of the second electrode with the other end face of the opposite end faces of the chip through the second electric connection layer, and correspondingly sealing the second base and the other end face of the opposite end faces of the insulating tube by adjusting the thickness S and the consumption V of a second buffer layer which is used for sealing the chip and is arranged between the second base and the insulating tube according to an internal and external tolerance dimension chain relation formula;
wherein, the inside and outside tolerance dimension chain relation formula is as follows:
S≥max{(H1+|H2|+D1+|D2|)，(T1+|T2|+d1+|d2|)}；S≤0.4mm；H+D＝T+S+D；V＝S*P；
the P is the area of the second buffer layer, the P is smaller than or equal to the cross-sectional area of the insulating tube, the radial height of the second base is T, the sum of the radial height of the boss of the second electrode and the radial height of the second base is H, the radial height between the outer end surface of the first base opposite to the connecting end surface and the insulating tube and between the outer end surface and the insulating tube is D, the radial height between the outer end surface of the first base and the second electrical connection layer is D, H1 and H2 are respectively the upper deviation and the lower deviation of H, D1 and D2 are respectively the upper deviation and the lower deviation of D, T1 and T2 are respectively the upper deviation and the lower deviation of T, and D1 and D2 are respectively the upper deviation and the lower deviation of D.
2. The method of claim 1, wherein the first electrode is a bump electrode, the first electrode further comprising a first bump protruding from an inner surface of the first base, the connection end surface of the first electrode being an end surface of the first bump that is electrically connected to the chip through the first electrical connection layer, and an outer end surface of the first electrode being an outer surface of the first base opposite to an end surface of the first bump.
3. The method of claim 1, wherein the first electrode is a planar electrode, the connection end surface of the first electrode is an inner surface of the first base that is electrically connected to the chip through the first electrical connection layer, and the outer end surface of the first electrode is an outer surface opposite to the inner surface of the first base.
4. A method according to claim 1, 2 or 3, wherein the step 130 of electrically connecting the boss of the second electrode with the other of the opposite end surfaces of the chip through the second electrical connection layer, and adjusting the thickness S and the amount V of the second buffer layer for sealing the chip according to the inside-outside tolerance dimension chain relation formula, and disposed between the second base and the insulating tube, correspondingly sealing the second base with the other of the opposite end surfaces of the insulating tube, comprises:
Correspondingly and electrically connecting the boss of the second electrode with the other end face of the two opposite end faces of the chip through the second electric connection layer;
adjusting the thickness S and the consumption V of a second buffer layer which is used for sealing the chip and is arranged between the second base and the insulating tube according to an internal and external tolerance dimension chain relation formula to obtain a product to be sealed;
inverting the product to be sealed to enable the second electrode to be positioned at the lowest part of the product to be sealed, and correspondingly sealing the second base and the other end face of the two opposite end faces of the insulating tube by adopting a solidification sealing process.
5. The method of claim 4, wherein inverting the product to be sealed such that the second electrode is positioned at the lowermost portion of the product to be sealed, and correspondingly sealing the second base to the other of the opposite end surfaces of the insulating tube using a curing sealing process, comprises:
inverting the product to be sealed to enable the second electrode to be positioned at the lowest layer of the product to be sealed, and adopting a solidification sealing process to correspondingly seal the second base and the other end face of the opposite two end faces of the insulating tube in a gas discharge tube sealing furnace.
6. The method of claim 5, wherein the gas discharge tube sealing furnace has a sealing temperature of 265-400 ℃.
7. The method of claim 6, wherein the insulating tube is a ceramic tube, and the first buffer layer and the second buffer layer are solder layers or adhesive layers or solder paste layers; the first electrical connection layer and the second electrical connection layer are solder layers, adhesive or solder paste layers.
8. The method as recited in claim 7, further comprising
Encapsulating the insulating tube, the first electrode, the second electrode except for the outer surfaces of the first electrode, the second electrode.
9. The structure of the insulating tube packaged chip is characterized by comprising a cavity and a chip sealed in the cavity, wherein the cavity comprises an insulating tube and a first electrode and a second electrode for sealing the insulating tube; the cavity further comprises:
a first buffer layer for hermetically connecting one end surface of the insulating tube and the first electrode;
a second buffer layer for hermetically connecting the other end face of the insulating tube and the second electrode;
the first electrode and the second electrode are electrically connected with the opposite two end surfaces of the chip in a one-to-one correspondence manner through a first electrical connection layer and a second electrical connection layer; the connecting end face of the first electrode is used for being electrically connected with one end face of the opposite end faces of the chip;
The first electrode comprises a first base, the second electrode comprises a second base, the second electrode further comprises a boss protruding on the first end face of the second base, and the thickness of the second buffer layer is obtained through the following inside and outside tolerance dimension chain relation formula:
S≥max{(H1+|H2|+D1+|D2|)，(T1+|T2|+d1+|d2|)}；S≤0.4mm；H+D＝T+S+D；
the diameter height of the second base is T, the sum of the diameter height of the boss of the second electrode and the diameter height of the second base is H, the diameter height from the outer end surface of the first base opposite to the connecting end surface to the insulating tube and between the insulating tube and the insulating tube is D, the diameter height from the outer end surface of the first base to the second electric connecting layer and between the outer end surface of the first base and the second electric connecting layer is D, H1 and H2 are respectively upper deviation and lower deviation of H, D1 and D2 are respectively upper deviation and lower deviation of D, T1 and T2 are respectively upper deviation and lower deviation of T, and D1 and D2 are respectively upper deviation and lower deviation of D.
10. The structure of claim 9, wherein the first electrode is a bump electrode, the first electrode further comprises a first bump protruding from an inner surface of the first base, the connection end surface of the first electrode is an end surface of the first bump that is electrically connected to the chip through the first electrical connection layer, and an outer end surface of the first electrode is an outer surface of the first base opposite to an end surface of the first bump.
11. The structure of claim 9, wherein the first electrode is a planar electrode, the connection end surface of the first electrode is an inner surface of the first base that is electrically connected to the chip through the first electrical connection layer, and the outer end surface of the first electrode is an outer surface opposite to the inner surface of the first base.
12. The structure according to any one of claims 9 to 11, wherein the insulating tube is a ceramic tube, and the first buffer layer and the second buffer layer are solder layers or adhesive layers or solder paste layers.
13. The structure of claim 12, wherein the first electrical connection layer and the second electrical connection layer are solder layers or adhesive or solder paste layers.
14. The structure of an insulating tube-packaged chip according to claim 13, further comprising an insulating encapsulation for encapsulating the insulating tube, the first electrode, and the second electrode except for an outer surface of the first electrode and the second electrode.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510413119.6A CN105097715B (en) | 2015-07-14 | 2015-07-14 | Method and structure for packaging chip by insulating tube |
| PCT/CN2016/085267 WO2017008603A1 (en) | 2015-07-14 | 2016-06-08 | Method structure for packaging chip with insulating tube |
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| CN201510413119.6A CN105097715B (en) | 2015-07-14 | 2015-07-14 | Method and structure for packaging chip by insulating tube |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102593090A (en) * | 2011-01-06 | 2012-07-18 | 嘉盛马来西亚公司 | Lead frame package with die arranged on pedestal for lead isolation |
| CN202888185U (en) * | 2012-09-21 | 2013-04-17 | 北京新创椿树整流器件有限公司 | Flat packaging crimping type outlet electrode insulated gate bipolar transistor element |
| CN103681547A (en) * | 2012-09-21 | 2014-03-26 | 北京新创椿树整流器件有限公司 | Flat package crimping type extraction electrode insulated gate bipolar transistor element |
| CN204792751U (en) * | 2015-07-14 | 2015-11-18 | 深圳市槟城电子有限公司 | Structure of insulating tube encapsulation chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8354750B2 (en) * | 2010-02-01 | 2013-01-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress buffer structures in a mounting structure of a semiconductor device |
| CN102194865B (en) * | 2011-05-11 | 2012-10-03 | 江阴市赛英电子有限公司 | High-power insulated gate bipolar translator (IGBT) flat pressed and connected packaging structure |
| CN105097715B (en) * | 2015-07-14 | 2023-10-13 | 深圳市槟城电子股份有限公司 | Method and structure for packaging chip by insulating tube |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102593090A (en) * | 2011-01-06 | 2012-07-18 | 嘉盛马来西亚公司 | Lead frame package with die arranged on pedestal for lead isolation |
| CN202888185U (en) * | 2012-09-21 | 2013-04-17 | 北京新创椿树整流器件有限公司 | Flat packaging crimping type outlet electrode insulated gate bipolar transistor element |
| CN103681547A (en) * | 2012-09-21 | 2014-03-26 | 北京新创椿树整流器件有限公司 | Flat package crimping type extraction electrode insulated gate bipolar transistor element |
| CN204792751U (en) * | 2015-07-14 | 2015-11-18 | 深圳市槟城电子有限公司 | Structure of insulating tube encapsulation chip |
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Address after: 518116 Shenzhen, Longgang, Guangdong province Longgang Street Baolong community Baolong four road 3 Lan Pu Yuan Industrial Zone 1 Factory A501 Applicant after: Shenzhen Penang Electronics Co.,Ltd. Address before: 518116 Shenzhen, Longgang, Guangdong province Longgang Street Baolong community Baolong four road 3 Lan Pu Yuan Industrial Zone 1 Factory A501 Applicant before: Shenzhen Bencent Electronics Co.,Ltd. |
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| GR01 | Patent grant | ||
| GR01 | Patent grant |