CN105097503A - 一种调节硅化钛/硅肖特基接触势垒的方法 - Google Patents

一种调节硅化钛/硅肖特基接触势垒的方法 Download PDF

Info

Publication number
CN105097503A
CN105097503A CN201410199891.8A CN201410199891A CN105097503A CN 105097503 A CN105097503 A CN 105097503A CN 201410199891 A CN201410199891 A CN 201410199891A CN 105097503 A CN105097503 A CN 105097503A
Authority
CN
China
Prior art keywords
titanium silicide
silicon
titanium
atoms
nitrogen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410199891.8A
Other languages
English (en)
Other versions
CN105097503B (zh
Inventor
蒋玉龙
王琳琳
彭雾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fudan University
Original Assignee
Fudan University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fudan University filed Critical Fudan University
Priority to CN201410199891.8A priority Critical patent/CN105097503B/zh
Publication of CN105097503A publication Critical patent/CN105097503A/zh
Application granted granted Critical
Publication of CN105097503B publication Critical patent/CN105097503B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

本发明属于微电子技术领域,具体为一种调节硅化钛和硅之间肖特基接触势垒的方法。本发明通过向硅化钛薄膜中引入适量氮原子,形成硅化钛(TiSix,内含氮原子)/Si肖特基接触结构,实现对硅化钛与硅之间肖特基接触势垒的有效调节。相比普通硅化钛/硅肖特基整流二极管的工艺流程,本发明只需要增加一步氮原子的引入工艺,就可获得明显的接触势垒调节,整个工艺步骤简单易行,具有良好的应用前景。

Description

一种调节硅化钛/硅肖特基接触势垒的方法
技术领域
本发明属于微电子技术领域,具体涉及调节硅化钛(TiSix)和硅之间肖特基接触势垒的方法。
背景技术
肖特基器件不仅广泛应用于通信、计算机、汽车等电子信息领域,而且应用于航空、航天等国防重点工程,由于钛具有熔点高、比重小、比强度高、韧性好、抗疲劳、耐腐蚀、导热系数低、高低温度耐受性能好、在急冷急热条件下应力小等特点是制作高耐压、低正向压降和高开关速度肖特基二极管的比较理想的新型材料,目前硅化钛/硅肖特基二极管被广泛研究。
肖特基器件的性能主要受到肖特基接触势垒的制约。普通硅化钛/硅肖特基整流二极管的接触势垒约为0.69eV,这是由于界面处由于存在界面态,费米能级被钉扎在Si的价带附近,造成电子势垒较大,从而限制了硅化钛/硅肖特基整流二极管性能的提升。因为电子势垒高度是决定开态电流大小的重要因素,较大的电子势垒限制了电子的流动,导致器件的开态电流小。
当今半导体器件不断朝着高能低价的方向进步,而工艺步骤作为制约器件生产成本中的重要因素,尤其值得研究人员的关注。工艺步骤的简单易行、工艺耗材的方便易得都是优化器件工艺的重要方法。由于氮化钛/硅接触势垒很低,约为0.49eV。通过向硅化钛/硅肖特基整流二极管中的硅化钛薄膜中引入适量氮原子而有效调节接触势垒的方法简单易行,并且效果显著,所得硅化钛(TiSix,内含氮原子)/硅肖特基整流二极管的接触势垒约为0.61eV,远低于普通硅化钛/硅肖特基整流二极管0.69eV的接触势垒。
发明内容
本发明的目的在于提出一种工艺简单、调节硅化钛/硅肖特基接触势垒的方法。
本发明提出的调节硅化钛与硅之间肖特基接触势垒的方法,具体步骤是,向硅化钛/硅肖特基整流二极管中的硅化钛薄膜中引入适量氮原子,形成硅化钛(TiSix,内含氮原子)/Si肖特基接触结构,实现接触势垒调节。
所述引入氮原子的方法可以有两种,它们分别是:
(1)在硅衬底上淀积金属钛膜后,通过离子注入或扩散方式将氮原子引入到金属钛膜中,再利用退火过程,通过金属钛膜与衬底硅的固相反应,在形成硅化钛/硅肖特基整流接触的同时,将氮原子掺入形成的硅化钛薄膜中;
(2)在硅衬底上淀积金属钛膜后,先利用退火过程实现金属钛与衬底硅的固相反应,生成硅化钛/硅肖特基整流接触,再利用离子注入或扩散工艺将氮原子引入到硅化钛薄膜中。
本发明中,最终生成的含有氮原子的硅化钛薄膜与衬底硅接触界面硅化钛薄膜一侧10纳米厚度内氮原子平均体浓度为1015-1024cm-3。优选氮原子平均体浓度为1016-1020cm-3
本发明中,热退火温度为500~1000oC,时间为1秒~10分钟。优选热退火温度为600~800oC,时间为1~5分钟。
本发明由于只需要在普通硅化钛/硅肖特基晶体管工艺中增加一步氮原子的引入工艺,就可获得明显的接触势垒调节,整个工艺步骤简单易行。
本发明通过向硅化钛薄膜中引入适量氮原子,形成硅化钛(TiSix,内含氮原子)/Si肖特基接触结构,实现对硅化钛与硅之间肖特基接触势垒的有效调节。在正向偏压下,该种肖特基接触的工作电流经由降低后的势垒区域流通,因而可以得到较高的工作电流。其I-V特性对比如图1所示。
附图说明
图1为氮掺入对硅化钛/硅肖特基二极管整流特性的影响。
图2—图6为工艺流程的示意图(侧视图)。
具体实施方式
下面结合附图进一步描述本发明:
第一种方案工艺步骤:
1、基于已经过清洗处理的清洁表面硅衬底进行金属钛薄膜的淀积,如图2所示;
2、通过离子注入或扩散方式将适量氮原子引入到金属钛膜中,如图3所示;
3、进行热退火,热退火温度为500~1000oC,时间为1秒~10分钟,使得最终生成的含有氮原子的硅化钛薄膜与衬底硅接触界面硅化钛薄膜一侧10纳米厚度内氮原子平均体浓度为1015-1024cm-3,最终结果如图6所示。
第二种方案工艺步骤:
1、基于已经过清洗处理的清洁表面硅片衬底进行金属钛薄膜的淀积,如图1所示;
2、进行热退火,热退火温度为500~1000oC,时间为1秒~10分钟,如图4所示;
3、利用离子注入或扩散工艺将适量氮原子引入到硅化钛薄膜中,如图5所示,使得最终生成的含有氮原子的硅化钛薄膜与衬底硅接触界面硅化钛薄膜一侧10纳米厚度内氮原子平均体浓度为1015-1024cm-3,最终结果如图6所示。

Claims (4)

1.一种调节硅化钛/硅肖特基接触势垒的方法,其特征在于具体步骤为:向硅化钛/硅肖特基整流二极管中的硅化钛薄膜中引入适量氮原子,实现接触势垒调节。
2.根据权利要求1所述的方法,其特征在于所述引入氮原子的方法有两种,它们分别是:
(1)在硅衬底上淀积金属钛膜后,通过离子注入或扩散方式将氮原子引入到金属钛膜中,再利用退火过程,使金属钛膜与衬底硅发生固相反应,在形成硅化钛/硅肖特基整流接触的同时,将氮原子掺入形成的硅化钛薄膜中;
(2)在硅衬底上淀积金属钛膜后,先利用退火过程使金属钛与衬底硅发生固相反应,生成硅化钛/硅肖特基整流接触,再利用离子注入或扩散工艺将氮原子引入到硅化钛薄膜中。
3.根据权利要求2所述的方法,其特征在于所述的热退火温度为500~1000oC,时间为1秒~10分钟。
4.根据权利要求2所述的方法,其特征在于最终生成的含有氮原子的硅化钛薄膜与衬底硅接触界面硅化钛薄膜一侧10纳米厚度内氮原子平均体浓度为1015-1024cm-3
CN201410199891.8A 2014-05-13 2014-05-13 一种调节硅化钛/硅肖特基接触势垒的方法 Expired - Fee Related CN105097503B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410199891.8A CN105097503B (zh) 2014-05-13 2014-05-13 一种调节硅化钛/硅肖特基接触势垒的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410199891.8A CN105097503B (zh) 2014-05-13 2014-05-13 一种调节硅化钛/硅肖特基接触势垒的方法

Publications (2)

Publication Number Publication Date
CN105097503A true CN105097503A (zh) 2015-11-25
CN105097503B CN105097503B (zh) 2017-11-17

Family

ID=54577662

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410199891.8A Expired - Fee Related CN105097503B (zh) 2014-05-13 2014-05-13 一种调节硅化钛/硅肖特基接触势垒的方法

Country Status (1)

Country Link
CN (1) CN105097503B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112864240A (zh) * 2021-01-14 2021-05-28 长鑫存储技术有限公司 半导体结构的制造方法及两种半导体结构
US11887854B2 (en) 2021-01-14 2024-01-30 Changxin Memory Technologies, Inc. Semiconductor structure manufacturing method and two semiconductor structures

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060175664A1 (en) * 2005-02-07 2006-08-10 Micron Technology, Inc. Semiconductor constructions, and methods of forming metal silicides
CN102119445A (zh) * 2008-08-13 2011-07-06 E.I.内穆尔杜邦公司 用于形成光伏器件的组合物和方法
CN103456612A (zh) * 2012-05-29 2013-12-18 北大方正集团有限公司 一种形成肖特基接触的方法及肖特基结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060175664A1 (en) * 2005-02-07 2006-08-10 Micron Technology, Inc. Semiconductor constructions, and methods of forming metal silicides
CN102119445A (zh) * 2008-08-13 2011-07-06 E.I.内穆尔杜邦公司 用于形成光伏器件的组合物和方法
CN103456612A (zh) * 2012-05-29 2013-12-18 北大方正集团有限公司 一种形成肖特基接触的方法及肖特基结构

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112864240A (zh) * 2021-01-14 2021-05-28 长鑫存储技术有限公司 半导体结构的制造方法及两种半导体结构
CN112864240B (zh) * 2021-01-14 2022-05-31 长鑫存储技术有限公司 半导体结构的制造方法及两种半导体结构
US11887854B2 (en) 2021-01-14 2024-01-30 Changxin Memory Technologies, Inc. Semiconductor structure manufacturing method and two semiconductor structures

Also Published As

Publication number Publication date
CN105097503B (zh) 2017-11-17

Similar Documents

Publication Publication Date Title
Zhao et al. Doping, contact and interface engineering of two‐dimensional layered transition metal dichalcogenides transistors
Leonhardt et al. Material-Selective Doping of 2D TMDC through Al x O y Encapsulation
US9190509B2 (en) High mobility, thin film transistors using semiconductor/insulator transition-metal dichalcogenide based interfaces
El-Atab et al. Diode behavior in ultra-thin low temperature ALD grown zinc-oxide on silicon
Gorji et al. Embedded nanoparticles in Schottky and Ohmic contacts: a review
Balsano et al. Schottky barrier height measurements of Cu/Si (001), Ag/Si (001), and Au/Si (001) interfaces utilizing ballistic electron emission microscopy and ballistic hole emission microscopy
Schulte-Braucks et al. Negative differential resistance in direct bandgap GeSn pin structures
Chawanda et al. Thermal annealing behaviour of platinum, nickel and titanium Schottky barrier diodes on n-Ge (1 0 0)
Dai et al. Novel heterogeneous integration technology of III–V layers and InGaAs finFETs to silicon
Jackson et al. Reduction of the potential energy barrier and resistance at wafer-bonded n-GaAs/n-GaAs interfaces by sulfur passivation
CN102723265B (zh) 一种硅片的铝掺杂方法
Wang et al. Identification and suppression of majority surface states in the dry-etched β-Ga2O3
Nag et al. Impact of the low temperature gate dielectrics on device performance and bias-stress stabilities of a-IGZO thin-film transistors
Low et al. GaN-based MIS-HEMTs with Al2O3 dielectric deposited by low-cost and environmental-friendly mist-CVD technique
CN105097503A (zh) 一种调节硅化钛/硅肖特基接触势垒的方法
Huet et al. Laser thermal annealing: A low thermal budget solution for advanced structures and new materials
Yu et al. Low-Temperature Fabrication of High Quality Gate Insulator in Metal–Oxide–Semiconductor Capacitor Using Laser Annealing
CN103904132B (zh) 一种调节硅化钛/硅肖特基接触势垒的方法
Cheng et al. Gate-first AlGaN/GaN HEMT technology for enhanced threshold voltage stability based on MOCVD-grown in situ SiNx
Tao et al. High hole mobility in physical vapour deposition-grown tellurium-based transistors
Barnett et al. Advanced techniques for achieving ultra-shallow junctions in future CMOS devices
Wang et al. The physical mechanism on the threshold voltage temperature stability improvement for GaN HEMTs with pre-fluorination argon treatment
Kim et al. Universal Metal–Interlayer–Semiconductor Contact Modeling Considering Interface-State Effect on Contact Resistivity Degradation
CN105304568A (zh) 一种降低高k金属栅器件阈值电压波动的方法
Choi et al. Electrical effect of titanium diffusion on amorphous indium gallium zinc oxide

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20171117

Termination date: 20200513