CN105097015B - dual-port SRAM - Google Patents

Abstract

A kind of dual-port SRAM, including comparing unit, control unit and N number of selecting unit.The comparing unit is suitable to export the first level when address signal in two group address ports is identical to N number of selecting unit and described control unit, otherwise exports second electrical level to N number of selecting unit and described control unit；Nth selected unit is suitable to the data output that nth data port in first group of FPDP is selected when receiving first level, and the data output of nth data port in second group of FPDP is selected when receiving the second electrical level.The dual-port SRAM that technical solution of the present invention provides, reduces two entities while reads the noise of the memory cell of same address in the dual-port SRAM.

Description

Dual-port SRAM

Technical field

The present invention relates to memory technology field, more particularly to a kind of dual-port SRAM.

Background technology

Static RAM (SRAM, Static Random Access Memory) is random access memory One kind.So-called " static state ", as long as referring to that this memory remains powered on, the constant holding of data can of the inside storage.Phase Over the ground, inside dynamic random access memory (DRAM, Dynamic Random Access Memory) stored by data just Need to be updated periodically.When supply of electric power stops, the data of SRAM storages still can disappear, and this with that can also store up after a loss of power The read-only storage (ROM, Read-Only Memory) or flash memory (Flash Memory) for depositing data are different.

It is often shared same in order to transmit data between CPU in the control system of decentralized processing is carried out with multiple CPU One SRAM.In order to improve the efficiency that multiple CPU access same SRAM, generally use dual-port SRAM data storages.Dual-port SRAM uses address bus, data/address bus and the controlling bus of two groups of independence, it is allowed to which two independent entities (such as CPU) are same When line access is entered to it.Fig. 1 is a kind of common dual-port SRAM10 structural representation, and the dual-port SRAM10 includes the One group address port ADDR1, the second group address port ADDR2, first group of FPDP DOUT1, second group of FPDP DOUT2, the first chip selection signal input port, the second chip selection signal input port, the first clock signal input terminal mouth CLK1, second clock signal input port CLK2, the first output enable port, second output enable port, first Write enable portAnd second write enable port。

Specifically, the first group address port ADDR1 and the second group address port ADDR2 deposits suitable for receiving access The address signal of storage unit, its port number are identical with the digit of the address signal；First group of FPDP DOUT1 and Second group of FPDP DOUT2 is suitable to transmission data, and its port number is identical with the data bits transmitted；Described first Select signal input portWith the second chip selection signal input portSuitable for receiving chip selection signal；First clock Signal input port CLK1 and the second clock signal input port CLK2 are suitable to input clock signal；First output makes Can portWith the described second output enable portSuitable for Rreceive output enable signal；Described first writes enable portEnable port is write with described secondSuitable for receiving write enable signal.The chip selection signal controls whether can be to described Dual-port SRAM10 is operated, and the output enable signal controls the whether exportable data of dual-port SRAM10, described Write enable signal controls whether that write operation can be carried out to the dual-port SRAM10.Those skilled in the art know the dual-port SRAM10 concrete operating principle, will not be repeated here.

Inside the dual-port SRAM10, in addition to the first internal clock generator circuit, the first internal clocking receiving terminal, Second internal clock generator circuit, the second internal clocking receiving terminal, the first row decoding circuit, the first array decoding circuit, the second row Decoding circuit, the second array decoding circuit and multiple memory cell.First internal clock generator circuit is suitable to according to First chip selection signal input portThe chip selection signal of reception and the first clock signal input terminal mouth CLK1 receive when Clock signal produces the first internal clock signal, and first internal clock signal is exported to first internal clocking and received End.After the first internal clocking receiving terminal receives first internal clocking, the first row decoding circuit and described First array decoding circuit enters row decoding to the first group address port ADDR1 address signals received, passes through wordline and bit line Corresponding memory cell is operated.Second internal clock generator circuit is suitable to be inputted according to second chip selection signal PortThe clock signal that the chip selection signal of reception and the second clock signal input port CLK2 are received is produced in second Portion's clock signal, and second internal clock signal is exported to the second internal clocking receiving terminal.In described second After portion's clock receiving terminal receives second internal clocking, the second row decoding circuit and second array decoding circuit pair The address signal that the second group address port ADDR2 is received enters row decoding, by wordline and bit line to corresponding memory cell Operated.

Fig. 2 is a kind of circuit diagram of common dual-port SRAM memory cell, and the dual-port SRAM memory cell includes： First pull up transistor P21, second pull up transistor P22, the first pull-down transistor N21, the second pull-down transistor N22, first Transmission transistor N23, the second transmission transistor N24, the 3rd transmission transistor N25 and the 4th transmission transistor N26.Wherein, Described first P22 that pull up transistor of P21 and described second that pull up transistor are PMOS, the first pull-down transistor N21, institute State the second pull-down transistor N22, the first transmission transistor N23, the second transmission transistor N24, the 3rd transmission Transistor N25 and the 4th transmission transistor N26 is NMOS tube.

Specifically, described first P21 source electrode is pulled up transistor and second source electrode for pulling up transistor P22 connects One power end Vdd, the described first grid for pulling up transistor P21 connect the grid of the first pull-down transistor N21, described the Two pull up transistor the draining of P22, the draining of the second pull-down transistor N22, the source electrode of the second transmission transistor N24 And the source electrode of the 4th transmission transistor N26, the described first drain electrode for pulling up transistor P21 connect first time crystal pulling The draining of body pipe N21, described second pull up transistor P22 grid, the grid of the second pull-down transistor N22, described The source electrode of one transmission transistor N23 source electrode and the 3rd transmission transistor N25；The first pull-down transistor N21's Source electrode connects second source end Vss, the electricity that the second source end Vss is provided with the source electrode of the second pull-down transistor N22 Source voltage is less than the supply voltage that the first power end Vdd is provided；The grid of the first transmission transistor N23 and described The drain electrode that two transmission transistor N24 grid connects the first wordline WL1, the first transmission transistor N23 connects the first bit line BL1；The grid of the 3rd transmission transistor N25 connects the second wordline WL2 with the grid of the 4th transmission transistor N26, The drain electrode of the 3rd transmission transistor N23 connects the second bit line BL2；The drain electrode connection the of the second transmission transistor N24 Three bit line BLB1；The drain electrode of the 4th transmission transistor N26 connects the 4th bit line BLB2.By to the first wordline WL1, The second wordline WL2, the first bit line BL1, the second bit line BL2, the 3rd bit line BLB1 and the described 4th Bit line BLB2 applies corresponding voltage, can be written and read operation to the first back end D1 and the second back end D2.

For the dual-port SRAM memory cell shown in Fig. 2, two independent entities can not be allowed while row write is entered to it Operation, but allow two independent entities to carry out read operation to it simultaneously.However, when simultaneously two independent entities are carried out to it During read operation, flow through that the electric current of pull-down transistor is larger, cause the noise of the dual-port SRAM memory cell to increase.

The content of the invention

What the present invention solved be two independent entities at the same read the memory cell of same address in dual-port SRAM and The problem of producing big noise.

To solve the above problems, the present invention provides a kind of dual-port SRAM, including the first group address port, the second group address Port, first group of FPDP, second group of FPDP, the first internal clock generator circuit, the first internal clocking receiving terminal, Two internal clock generator circuits and the second internal clocking receiving terminal, the dual-port SRAM also include comparing unit, control list First and N number of selecting unit, N are the port number of first group of FPDP；

The comparing unit is suitable to address signal and the second group address port in the first group address port The first level is exported when address signal is identical to N number of selecting unit and described control unit, otherwise exports second electrical level extremely N number of selecting unit and described control unit；

Described control unit is suitable to forbid second internal clock generator circuit defeated when receiving first level Go out internal clock signal to the second internal clocking receiving terminal, allow when receiving the second electrical level inside described second Clock generation circuit exports internal clock signal to the second internal clocking receiving terminal；

Nth selected unit is suitable to select when receiving first level in first group of FPDP n-th The data output of FPDP, nth data end in second group of FPDP is selected when receiving the second electrical level The data output of mouth, 1≤n≤N.

Optionally, the comparing unit includes first and gate circuit and M same OR circuits, and M is first group address The port number of port；

M-th of first input end with OR circuit connects m-th of address port in the first group address port, m Second input of individual same OR circuit connects m-th of address port in the second group address port, m-th of same OR circuit Output end connect described first and m-th of input of gate circuit, described first with the output end of gate circuit as the ratio Compared with the output end of unit, 1≤m≤M.

Optionally, described control unit includes the first phase inverter and second and gate circuit；

The input of first phase inverter is suitable to receive first level or the second electrical level, and described first is anti-phase The output end of device connects the described second first input end with gate circuit；

Described second is suitable to receive the interior of the second internal clock generator circuit output with the second input of gate circuit Portion's clock signal, described second is connected the second internal clocking receiving terminal with the output end of gate circuit.

Optionally, the nth selected unit includes the second phase inverter, the first transmission gate and the second transmission gate；

The input of second phase inverter connects the first control terminal of first transmission gate and second transmission gate The second control terminal and suitable for receiving first level or the second electrical level, the output end connection institute of second phase inverter State the second control terminal of the first transmission gate and the first control terminal of second transmission gate；

Nth data port in input connection first group of FPDP of first transmission gate, described first The output end of transmission gate connects the output end of second transmission gate and as the output end of the nth selected unit；

The input of second transmission gate connects nth data port in second group of FPDP.

Optionally, first transmission gate includes the first PMOS and the first NMOS tube, and second transmission gate includes the Two PMOSs and the second NMOS tube；

The grid of first PMOS be first transmission gate the second control terminal, the source electrode of first PMOS Connect the drain electrode of first NMOS tube and connected as the input of first transmission gate, the drain electrode of first PMOS The source electrode of first NMOS tube and as the output end of first transmission gate, the grid of first NMOS tube are described the First control terminal of one transmission gate；

The grid of second PMOS be second transmission gate the second control terminal, the source electrode of second PMOS Connect the drain electrode of second NMOS tube and connected as the input of second transmission gate, the drain electrode of second PMOS The source electrode of second NMOS tube and as the output end of second transmission gate, the grid of second NMOS tube are described the First control terminal of two transmission gates.

Compared with prior art, technical scheme has advantages below：

Dual-port SRAM provided by the invention, the address signal and second of the first group address port is compared by comparing unit Whether simultaneously whether the address signal of group address port is identical, it can be determined that two independent entities storage list to same address Member is read out.If two independent entities are the memory cell of same address to be read out simultaneously, allow by described First group address port is read, and no thoroughfare that the second group address port is read, single by selection Output data of the data output of member first group of FPDP of selection as second group of FPDP；If two independent entities are not It is that the memory cell of same address is read out simultaneously, then allows by the first group address port and described second group Location port is read, and the selecting unit selects the data output of second group of FPDP.

By dual-port SRAM provided by the invention, when simultaneously two independent entities read the memory cell of same address When, it is actual that the memory cell is only read by a group address port.Therefore, the pull-down transistor in the memory cell is flowed through Electric current be reduced to half of the prior art, the noise of the memory cell reduces.

Further, the noise of the memory cell reduces, when the supply voltage of the SRAM reduces, the memory cell The ability enhancing of data is kept, the SRAM is applied in the system of low supply voltage.Also, when two independent realities When body reads the memory cell of same address simultaneously, the current potential of a bit line need to only be dragged down, and in the prior art by two positions The current potential of line, which drags down, to be compared, and improves reading speed.

Further, by dual-port SRAM provided by the invention, when two independent entities read same address simultaneously During memory cell, no thoroughfare, and the second group address port is read, with the supporting work in the second group address port The circuit unit of work does not work, saves circuit power consumption.

Brief description of the drawings

Fig. 1 is a kind of common dual-port SRAM structural representation；

Fig. 2 is a kind of circuit diagram of common dual-port SRAM memory cell；

Fig. 3 is dual-port SRAM provided in an embodiment of the present invention structural representation；

Fig. 4 is the electrical block diagram of comparing unit provided in an embodiment of the present invention；

Fig. 5 is the electrical block diagram of control unit provided in an embodiment of the present invention；

Fig. 6 is a kind of electrical block diagram of selecting unit provided in an embodiment of the present invention；

Fig. 7 is the electrical block diagram of another selecting unit provided in an embodiment of the present invention；

Fig. 8 is the electrical block diagram of another selecting unit provided in an embodiment of the present invention.

Embodiment

Dual-port SRAM memory cell with reference to shown in figure 2, the first back end D1 and second back end D2 stores binary data 0 and 1 respectively.When two independent entities read the dual-port SRAM memory cell simultaneously, institute The first bit line BL1, the 3rd bit line BLB1, the second bit line BL2 and the 4th bit line BLB2 is stated first to be precharged To a predeterminated voltage (being usually the supply voltage that the first power end Vdd is provided), the first transmission crystal is then controlled Pipe N23, the second transmission transistor N24, the 3rd transmission transistor N25 and the 4th transmission transistor N26 are led Logical, the binary data of the first back end D1 storages is read the first bit line BL1 and the second bit line BL2 On, the binary data of the second back end D2 storages is read the 3rd bit line BLB1 and the 4th bit line BLB2 On.Data on the first bit line BL1 and the 3rd bit line BLB1 are back to an entity by one group of FPDP, and described Data on two bit line BL2 and the 4th bit line BLB2 are back to another entity by another group of FPDP.

It is assumed that the first back end D1 storages binary data 0, the second back end D2 storage binary numbers According to 1, when reading the memory cell, the first pull-down transistor N21 conductings, the second pull-down transistor N22 ends.Two When individual independent entity reads the dual-port SRAM memory cell simultaneously, the electric current of the first pull-down transistor N21 is flowed through Corresponding increase, therefore, the voltage rise of the first back end D1, the dual-port SRAM memory cell keep the energy of data Power weakens, i.e., the noise of described dual-port SRAM memory cell becomes big.When the supply voltage drop that the first power end Vdd is provided When low, the dual-port SRAM memory cell keeps the ability of data further to weaken, thus dual-port SRAM storages are single Member may not apply in the system of low supply voltage.Also, deposited when two independent entities read the dual-port SRAM simultaneously , it is necessary to which institute could be obtained after the current potential of the current potential of the first bit line BL1 and the second bit line BL2 is dragged down during storage unit The binary data 0 of the first back end D1 storages is stated, reading speed is slow.

Based on this, the present invention provides a kind of dual-port SRAM, and depositing for same address is read simultaneously in two independent entities During storage unit, no thoroughfare, and the second group address port is read, and will be read out behaviour by the first group address port The data for making to obtain are supplied to described two independent entities, to reduce the noise of the dual-port SRAM memory cell.

It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

Fig. 3 is dual-port SRAM provided in an embodiment of the present invention structural representation, and the dual-port SRAM includes first Group address port, the second group address port, first group of FPDP, second group of FPDP, the first chip selection signal input port, the second chip selection signal input port, the first clock signal input terminal mouth CLK1, second clock signal input port CLK2, the first output enable port, second output enable port, first write enable port, second write and make Can port, the first internal clock generator circuit 301, the first internal clocking receiving terminal 302, the second internal clocking produce electricity The internal clocking receiving terminal 304 of road 303 and second.The dual-port SRAM also includes the first row decoding circuit, the first column decoding Circuit, the second row decoding circuit, the second array decoding circuit and memory cell, the structure of the memory cell can be such as Fig. 2 institutes Show or the structure similar with Fig. 2.The first chip selection signal input port, second chip selection signal input Port, the first clock signal input terminal mouth CLK1, the second clock signal input port CLK2, described first Export enable port, it is described second output enable port, described first write enable portAnd described Two write enable port, it is first internal clock generator circuit 301, the first internal clocking receiving terminal 302, described Second internal clock generator circuit 303, the second internal clocking receiving terminal 304, the first row decoding circuit, described first The function of array decoding circuit, the second row decoding circuit and second array decoding circuit with similar in the prior art, This is repeated no more.

Generally, the first group address port and the second group address port include multiple address ports, each Location port is suitable to one bit address signal of input, the port number of the first group address port and the second group address port Port number is identical；First group of FPDP and second group of FPDP include multiple FPDPs, per number It is suitable to the port of transmission a data, the port number of first group of FPDP and second group of FPDP according to port Quantity is identical.The port number of the port number of the first group address port and first group of FPDP is according to described double The quantity of memory cell in port SRAM determines, more clearly to describe dual-port SRAM provided by the invention, in the present invention In embodiment, two address ports are included with the first group address port, first group of FPDP includes two data Illustrated exemplified by port.

Specifically, the first group address port includes address port A11 and address port A12, second group address Port includes address port A21 and address port A22, the address port A21 and the address port A11 are corresponding, describedly The location port A22 and address port A12 is corresponding；First group of FPDP includes FPDP D11 and FPDP D12, second group of FPDP include FPDP D21 and FPDP D22, the FPDP D21 and the data Port D11 is corresponding, and the FPDP D22 and the FPDP D12 are corresponding.

The dual-port SRAM also includes comparing unit 31, control unit 32 and N number of selecting unit, and N is described first The port number of group FPDP.In the present embodiment, the port number of first group of FPDP is 2, therefore, described double Port SRAM also includes the comparing unit 31, described control unit 32, selecting unit 331 and selecting unit 332.

The comparing unit 31 is suitable to the address signal of the first group address port and the second group address end The address signal of mouth, comparative level is exported by the output end Out1 of the comparing unit 31 according to comparative result.Described first group The address signal of address port is provided by the entity that the dual-port SRAM is read by the first group address port, and described the The address signal of two group address ports is provided by the entity that the dual-port SRAM is read by the second group address port.Tool Body, it is described when the address signal of the first group address port is identical with the address signal of the second group address port Comparing unit 31 exports the first level to the selecting unit 331, the selecting unit 332 and described control unit 32； It is described relatively more single when the address signal of the first group address port and the address signal of the second group address port differ Member 31 exports second electrical level to the selecting unit 331, the selecting unit 332 and described control unit 32.

In the prior art, internal clock signal caused by the first internal clock generator circuit in dual-port SRAM is directly defeated Go out to the first internal clocking receiving terminal, internal clock signal caused by the second internal clock generator circuit is directly output in second Portion's clock receiving terminal.And in technical solution of the present invention, internal clocking caused by first internal clock generator circuit 301 is believed Number be still directly output to the first internal clocking receiving terminal 302, but caused by second internal clock generator circuit 303 in Control of portion's clock signal by described control unit 32.Specifically, described control unit 32 is when receiving first level Forbid second internal clock generator circuit 303 to export internal clock signal to the second internal clocking receiving terminal 304, make The second row decoding circuit and second array decoding circuit can not be to the address signals of input the second group address port Enter row decoding, no thoroughfare, and the dual-port SRAM is read in the second group address port；Described control unit 32 is receiving Allow second internal clock generator circuit 303 to export clock signal to second internal clocking during second electrical level to connect Receiving end 304, make the ground of the second row decoding circuit and second array decoding circuit to input the second group address port Location signal enters row decoding, it is allowed to reads the dual-port SRAM by the second group address port.First level and institute Stating the specific level magnitudes of second electrical level can be set according to the actual requirements, in embodiments of the present invention, first electricity It is low level to put down as high level, the second electrical level.

In N number of selecting unit, nth selected unit is suitable to select described first when receiving first level The data output of nth data port, second group of data are selected when receiving the second electrical level in group FPDP The data output of nth data port in port, 1≤n≤N.

Specifically, the selecting unit 331 is suitable to receive level, the FPDP that the comparing unit 31 exports The data of D11 data and the FPDP D12.When the comparing unit 31 exports first level, the choosing The output end Out2 for selecting unit 331 exports the data of the FPDP D11；Second electricity is exported in the comparing unit 31 Usually, the output end Out2 of the selecting unit 331 exports the data of the FPDP D21.

The selecting unit 332 is suitable to receive level, the data of the FPDP D12 that the comparing unit 31 exports And the data of the FPDP D22.When the comparing unit 31 exports first level, the selecting unit 332 Output end Out3 export the data of the FPDP D12；It is described when the comparing unit 31 exports the second electrical level The output end Out3 of selecting unit 332 exports the data of the FPDP D22.

Exemplified by two independent entities to access the dual-port SRAM are the first CPU and the 2nd CPU, say briefly below The bright dual-port SRAM provided in an embodiment of the present invention operation principle.

When the first CPU and the 2nd CPU reads the dual-port SRAM simultaneously, the first CPU is to described First group address port, which provides, needs the access unit address signal that reads, and the 2nd CPU is to the second group address end Mouth provides the access unit address signal for needing to read.Meanwhile the first CPU is also to the first chip selection signal input Mouthful, the first clock signal input terminal mouth CLK1, the first output enable portAnd described first write and make Can portCorresponding signal is provided, the 2nd CPU is also to the second chip selection signal input port, described Two clock signal input terminal mouth CLK2, the second output enable portAnd described second write enable portCarry For corresponding signal.Those skilled in the art know how to provide corresponding signal, will not be repeated here.

If the first CPU and the 2nd CPU are that the same storage in the dual-port SRAM is singly read out, The first group address port is identical with the address of the second group address port, and the comparing unit 31 produces institute by comparing State the first level.After described control unit 32 receives first level, forbid second internal clock generator circuit 303 Internal clock signal is provided to the second internal clocking receiving terminal 304, the second row decoding circuit and the secondary series are translated Code circuit can not enter row decoding to the 2nd CPU address signals provided, forbid the 2nd CPU by described second group Read the dual-port SRAM in location port.First CPU reads the dual-port SRAM by the first group address port, The data of reading return to the first CPU by first group of FPDP.N number of selecting unit is receiving described first After level, the data output of first group of FPDP is selected.Because what the first CPU and the 2nd CPU was read is The memory cell of same address, therefore, the data of N number of selecting unit output are the 2nd CPU data to be read.

If the first CPU and the 2nd CPU are not that the same storage in the dual-port SRAM is singly read out, Then the address of the first group address port and the second group address port differs, and the comparing unit 31 is by comparing production The raw second electrical level.After described control unit 32 receives the second electrical level, it is allowed to which second internal clocking produces electricity Road 303 provides internal clock signal, the second row decoding circuit and described second to the second internal clocking receiving terminal 304 Array decoding circuit enters row decoding to the 2nd CPU address signals provided, it is allowed to which the 2nd CPU is by described second group Read the dual-port SRAM in location port.First CPU reads the dual-port SRAM by the first group address port, The data of reading return to the first CPU by first group of FPDP；2nd CPU passes through the second group address end Mouth reads the dual-port SRAM, and the data of reading are exported by second group of FPDP.N number of selecting unit is receiving To after the second electrical level, the data output of second group of FPDP is selected, the data of N number of selecting unit output are For the 2nd CPU data to be read.

Dual-port SRAM provided by the invention, when two independent entities read simultaneously it is same in the dual-port SRAM It is actual that the dual-port SRAM is only read by a group address port during memory cell of location.Therefore, compared with prior art, The electric current for flowing through the pull-down transistor in the memory cell is reduced to half of the prior art, the noise of the memory cell Reduce.The noise of the memory cell reduces, and when the supply voltage of the SRAM reduces, the memory cell keeps data Ability strengthens, and the SRAM is applied in the system of low supply voltage.Also, when simultaneously two independent entities are read During the memory cell of same address, the current potential of a bit line need to only be dragged down, with the prior art drawing the current potential of two bit lines Low phase ratio, improves reading speed.Further, when two independent entities read the memory cell of same address simultaneously, prohibit Only it is read by the second group address port, it is supporting with the second group address port in the dual-port SRAM The circuit unit of work does not work, saves circuit power consumption.

The embodiment of the present invention provides a kind of particular circuit configurations of the comparing unit 31, as shown in Figure 4.It is described relatively more single Member 31 includes first and gate circuit 43 and M same OR circuits, and M is the port number of the first group address port.In this reality Apply in example, exemplified by still including two ports by the first group address port, the comparing unit 31 includes two with OR gate electricity Road：With OR circuit 41 and with OR circuit 42.The same OR circuit 41 and the same OR circuit 42 be two inputs with or Gate circuit, described first with gate circuit 43 be two input and gate circuit.

Specifically, the first input end of the same OR circuit 41 connects the address port A11, the same to OR circuit 41 the second input connects the address port A21, output end connection described first and the door electricity of the same OR circuit 41 First input on road 43；The first input end of the same OR circuit 42 connects the address port A21, the same to OR gate Second input of circuit 42 connects the address port A22, the output end connection described first of the same OR circuit 42 with Second input of gate circuit 43.Described first with the output end of the output end of gate circuit 43 as the comparing unit 31 Out1, suitable for exporting first level or the second electrical level.

When the address signal of the first group address port is identical with the address signal of the second group address port, institute State same OR circuit 41 and the same OR circuit 42 exports high level, carry out and handle with gate circuit 43 by described first Afterwards, described first high level, i.e., described first level are exported with gate circuit 43；When the address signal of the first group address port When being differed with the address signal of the second group address port, in the same OR circuit 41 and the same OR circuit 42 extremely Rare output low level, after described first carries out and handle with gate circuit 43, described first exports with gate circuit 43 Low level, i.e., described second electrical level.

It should be noted that the comparing unit 31 is not limited to the particular circuit configurations of the present embodiment offer, this area Technical staff can also realize the function of the comparing unit 31, therefore, the tool that the present embodiment provides using other logic circuits Body circuit structure should not be used as the restriction to the comparing unit 31.

The embodiment of the present invention provides a kind of particular circuit configurations of described control unit 32, as shown in Figure 5.The control is single Member 32 includes the first phase inverter INV1 and second and gate circuit 50, and described second and gate circuit 50 are two inputs and gate circuit.

Specifically, the input of the first phase inverter INV1 is suitable to receive first level or the second electrical level, I.e. described first phase inverter INV1 input connects the output end Out1, the first phase inverter INV1 of the comparing unit 31 Output end connect described second and the first input end of gate circuit 50；Described second is suitable to the second input of gate circuit 50 Receive the internal clock signal that second internal clock generator circuit 303 exports, described second with the output end of gate circuit 50 Connect the second internal clocking receiving terminal 304.

The embodiment of the present invention provides a kind of particular circuit configurations of the selecting unit 331 and the selecting unit 332, by It is similar with the structure of the selecting unit 332 in the selecting unit 331, in the present embodiment, only with the selecting unit 331 Exemplified by illustrate.With reference to figure 6, the selecting unit 331 includes the second phase inverter INV2, the first transmission gate PG1 and second and passed Defeated door PG2.

Specifically, the input of the second phase inverter INV2 connect the first transmission gate PG1 the first control terminal and The second control terminal of the second transmission gate PG2 is simultaneously suitable to reception first level or the second electrical level, i.e., and described second Phase inverter INV2 input connects the second control of the first control terminal of the first transmission gate PG1, the second transmission gate PG2 The output end Out1, the second phase inverter INV2 of end processed and the comparing unit 31 output end connection first transmission Door PG1 the second control terminal and the first control terminal of the second transmission gate PG2.

The first transmission gate PG1 includes the first PMOS P51 and the first NMOS tube N51.The first PMOS P51's Grid is the second control terminal of the first transmission gate PG1, and the source electrode of the first PMOS P51 connects first NMOS tube N51 drain electrode simultaneously connects described first as the input of the first transmission gate PG1, the drain electrode of the first PMOS P51 NMOS tube N51 source electrode and as the output end of the first transmission gate PG1, the grid of the first NMOS tube N51 is described First transmission gate PG1 the first control terminal.

The second transmission gate PG2 includes the second PMOS P52 and the second NMOS tube N52.The second PMOS P52's Grid is the second control terminal of the second transmission gate PG2, and the source electrode of the second PMOS P52 connects second NMOS tube N52 drain electrode simultaneously connects described second as the input of the second transmission gate PG2, the drain electrode of the second PMOS P52 NMOS tube N52 source electrode and as the output end of the second transmission gate PG2, the grid of the second NMOS tube N52 is described Second transmission gate PG2 the first control terminal.

The input of the first transmission gate PG1 connects the FPDP D11, the output of the first transmission gate PG1 End connects the output end of the second transmission gate PG2 and as the output end Out2 of the selecting unit 331, second transmission Door PG2 input connects the FPDP D21.

When the comparing unit 31 produces first level, the first NMOS tube N51 and first PMOS P51 is turned on, and the second NMOS tube N52 and the second PMOS P52 cut-offs, the selecting unit 331 select the data Port D11 data output；When the comparing unit 31 produces the second electrical level, the first NMOS tube N51 and described First PMOS P51 ends, and the second NMOS tube N52 and the second PMOS P52 conductings, the selecting unit 331 are selected Select the data output of the FPDP D21.

The embodiment of the present invention also provides a kind of particular circuit configurations of the selecting unit 331 and the selecting unit 332, Because the selecting unit 331 is similar with the structure of the selecting unit 332, in the present embodiment, only with the selecting unit Illustrated exemplified by 331.With reference to figure 7, the selecting unit 331 includes first switch K11 and second switch K12.

Specifically, the control terminal of the first switch K11 connects the control terminal of the second switch K12 and suitable for receiving institute The first level or the second electrical level are stated, i.e., described first switch K11 control terminal connects the control terminal of the second switch K12 And the output end Out1, the first switch K11 of the comparing unit 31 first end connect the FPDP D11, institute The second end for stating first switch K11 connects the second end of the second switch K12 and as the output end of the selecting unit 331 Out2；The first end of the second switch K12 connects the FPDP D21.

When the control terminal of the first switch K11 receives first level, the first end of the first switch K11 Turn on the second end of the first switch K11, otherwise disconnect；Described is received in the control terminal of the second switch K12 During two level, the first end of the second switch K12 and the second switch K12 the second end conducting, otherwise disconnect.

In the present embodiment, the first switch K11 is can be with the 3rd NMOS tube, and the second switch K12 is can be with the Three PMOSs.The grid of 3rd NMOS tube is the control terminal of the first switch K11, and the drain electrode of the 3rd NMOS tube is The first end of the first switch K11, the source electrode of the 3rd NMOS tube are the second end of the first switch K11；Described The grid of three PMOSs is the control terminal of the second switch K12, and the source electrode of the 3rd PMOS is the second switch K12 First end, the 3rd PMOS drain electrode for the second switch K12 the second end.In other embodiments, described The one switch K11 and second switch K12 can also have the device of switching function for other, and this is not limited by the present invention.

The embodiment of the present invention also provides a kind of particular circuit configurations of the selecting unit 331 and the selecting unit 332, Because the selecting unit 331 is similar with the structure of the selecting unit 332, in the present embodiment, only with the selecting unit Illustrated exemplified by 331.With reference to figure 8, the selecting unit 331 includes the 3rd phase inverter INV3, the 3rd switch K13 and the 4th is opened Close K14.

The input of the 3rd phase inverter INV3 is suitable to receive first level or the second electrical level, i.e., and described the Three phase inverter INV3 input connects the output end Out1 of the comparing unit 31, the output end of the 3rd phase inverter INV3 Connect the control terminal of the 3rd switch K13 and the control terminal of the 4th switch K14；The first end of the 3rd switch K13 Connect the FPDP D11, the second end connection the 4th switch K14 of the 3rd switch K13 the second end and conduct The output end Out2 of the selecting unit 331；The first end of the 4th switch K14 connects the FPDP D21.

When the input of the 3rd phase inverter INV3 receives first level, the of the 3rd switch K13 One end and the conducting of the second end of the first switch K13, otherwise disconnect；Received in the input of the 3rd phase inverter INV3 During the second electrical level, the first end of the 4th switch K14 and the second end conducting of the second switch K14, otherwise disconnect.

In the present embodiment, the 3rd switch is the PMOSs of K13 the 4th, and the 4th switch K14 is the 4th NMOS tube. The grid of 4th PMOS is the described 3rd switch K13 control terminal, and the source electrode of the 4th PMOS is the described 3rd K13 first end is switched, the drain electrode of the 4th PMOS is the described 3rd the second end for switching K13；4th NMOS tube Grid for the described 4th switch K14 control terminal, the 4th NMOS tube drain electrode for the described 4th switch K14 first End, the source electrode of the 4th NMOS tube is the described 4th the second end for switching K14.In other embodiments, the 3rd switch K13 and the 4th switch K14 can also have the device of switching function for other, and this is not limited by the present invention.

Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims (10)

1. a kind of dual-port SRAM, including the first group address port, the second group address port, first group of FPDP, second group FPDP, the first internal clock generator circuit, the first internal clocking receiving terminal, the second internal clock generator circuit and second Internal clocking receiving terminal, it is characterised in that also including comparing unit, control unit and N number of selecting unit, N is described first group The port number of FPDP；

The comparing unit is suitable to the address signal in the first group address port and the address of the second group address port The first level is exported when signal is identical to N number of selecting unit and described control unit, otherwise exports second electrical level to the N Individual selecting unit and described control unit；

Described control unit is suitable to when receiving first level forbid in the second internal clock generator circuit output Portion's clock signal allows second internal clocking when receiving the second electrical level to the second internal clocking receiving terminal Generation circuit exports internal clock signal to the second internal clocking receiving terminal；

Nth selected unit is suitable to select nth data in first group of FPDP when receiving first level The data output of port, nth data port in second group of FPDP is selected when receiving the second electrical level Data output, 1≤n≤N.

2. dual-port SRAM as claimed in claim 1, it is characterised in that the comparing unit includes first and gate circuit and M Individual same OR circuit, M are the port number of the first group address port；

M-th of first input end with OR circuit connects m-th of address port in the first group address port, and m-th same Second input of OR circuit connects m-th of address port in the second group address port, and m-th the same as the defeated of OR circuit Go out end connection described first and m-th of input of gate circuit, described first with the output end of gate circuit as compared with described singly The output end of member, 1≤m≤M.

3. dual-port SRAM as claimed in claim 1 or 2, it is characterised in that described control unit include the first phase inverter and Second and gate circuit；

The input of first phase inverter is suitable to receive first level or the second electrical level, first phase inverter Output end connects the described second first input end with gate circuit；

Described second with the second input of gate circuit when being suitable to receive the inside of the second internal clock generator circuit output Clock signal, described second is connected the second internal clocking receiving terminal with the output end of gate circuit.

4. dual-port SRAM as claimed in claim 3, it is characterised in that the nth selected unit include the second phase inverter, First transmission gate and the second transmission gate；

The input of second phase inverter connect first transmission gate the first control terminal and second transmission gate the Two control terminals are simultaneously suitable to receive first level or the second electrical level, the output end connection of second phase inverter described the First control terminal of the second control terminal of one transmission gate and second transmission gate；

The input of first transmission gate connects nth data port in first group of FPDP, first transmission The output end of door connects the output end of second transmission gate and as the output end of the nth selected unit；

The input of second transmission gate connects nth data port in second group of FPDP.

5. dual-port SRAM as claimed in claim 4, it is characterised in that first transmission gate includes the first PMOS and the One NMOS tube, second transmission gate include the second PMOS and the second NMOS tube；

The grid of first PMOS is the second control terminal of first transmission gate, and the source electrode of first PMOS connects The drain electrode of first NMOS tube and as the input of first transmission gate, described in the drain electrode connection of first PMOS The source electrode of first NMOS tube simultaneously passes as the output end of first transmission gate, the grid of first NMOS tube for described first First control terminal of defeated door；

The grid of second PMOS is the second control terminal of second transmission gate, and the source electrode of second PMOS connects The drain electrode of second NMOS tube and as the input of second transmission gate, described in the drain electrode connection of second PMOS The source electrode of second NMOS tube simultaneously passes as the output end of second transmission gate, the grid of second NMOS tube for described second First control terminal of defeated door.

6. dual-port SRAM as claimed in claim 3, it is characterised in that the nth selected unit include first switch and Second switch；

The control terminal of the first switch connects the control terminal of the second switch and suitable for receiving first level or described Second electrical level, the first end of the first switch connect nth data port in first group of FPDP, and described first opens The second end closed connects the second end of the second switch and as the output end of the nth selected unit；

The first end of the second switch connects nth data port in second group of FPDP；

When the control terminal of the first switch receives first level, the first end of the first switch and described first The second end conducting of switch, otherwise disconnects；

When the control terminal of the second switch receives the second electrical level, the first end of the second switch and described second The second end conducting of switch, otherwise disconnects.

7. dual-port SRAM as claimed in claim 6, it is characterised in that the first switch is the 3rd NMOS tube, described Two switches are the 3rd PMOS；

The grid of 3rd NMOS tube is the control terminal of the first switch, and the drain electrode of the 3rd NMOS tube is described first The first end of switch, the source electrode of the 3rd NMOS tube are the second end of the first switch；

The grid of 3rd PMOS is the control terminal of the second switch, and the source electrode of the 3rd PMOS is described second The first end of switch, the drain electrode of the 3rd PMOS are the second end of the second switch.

8. dual-port SRAM as claimed in claim 6, it is characterised in that the nth selected unit include the 3rd phase inverter, 3rd switch and the 4th switch；

The input of 3rd phase inverter is suitable to receive first level or the second electrical level, the 3rd phase inverter The control terminal of output end connection the 3rd switch and the control terminal of the 4th switch；

The first end of 3rd switch connects nth data port in first group of FPDP, the 3rd switch Second end connects the second end of the 4th switch and as the output end of the nth selected unit；

The first end of 4th switch connects nth data port in second group of FPDP；

When the input of the 3rd phase inverter receives first level, the first end and described the of the 3rd switch The second end conducting of one switch, otherwise disconnects；

When the input of the 3rd phase inverter receives the second electrical level, the first end and described the of the 4th switch The second end conducting of two switches, otherwise disconnects.

9. dual-port SRAM as claimed in claim 8, it is characterised in that the 3rd switch is the 4th PMOS, described the Four switches are the 4th NMOS tube；

The grid of 4th PMOS is the control terminal of the described 3rd switch, and the source electrode of the 4th PMOS is the described 3rd The first end of switch, the drain electrode of the 4th PMOS is the described 3rd the second end switched；

The grid of 4th NMOS tube is the control terminal of the described 4th switch, and the drain electrode of the 4th NMOS tube is the described 4th The first end of switch, the source electrode of the 4th NMOS tube are the second end of the described 4th switch.

10. dual-port SRAM as claimed in claim 1, it is characterised in that also include including memory cell, the memory cell First pulls up transistor, second pulls up transistor, the first pull-down transistor, the second pull-down transistor, the first transmission transistor, Two transmission transistors, the 3rd transmission transistor and the 4th transmission transistor；

First source electrode to pull up transistor connects the first power end with second source electrode to pull up transistor, and described first The grid that pulls up transistor connect the grid of first pull-down transistor, described second pull up transistor drain, described the The source electrode of the draining of two pull-down transistors, the source electrode of second transmission transistor and the 4th transmission transistor, it is described First drain electrode to pull up transistor connects the draining of first pull-down transistor, second grid to pull up transistor, institute State the source electrode of the grid of the second pull-down transistor, the source electrode of first transmission transistor and the 3rd transmission transistor；

The source electrode of first pull-down transistor connects second source end with the source electrode of second pull-down transistor, and described second The supply voltage that power end provides is less than the supply voltage that first power end provides；

The grid of first transmission transistor connects the first wordline with the grid of second transmission transistor, and described first passes The drain electrode of defeated transistor connects the first bit line；

The grid of 3rd transmission transistor connects the second wordline with the grid of the 4th transmission transistor, and the described 3rd passes The drain electrode of defeated transistor connects the second bit line；

The drain electrode of second transmission transistor connects the 3rd bit line；

The drain electrode of 4th transmission transistor connects the 4th bit line.