CN105097015A - Dual-port SRAM - Google Patents

Dual-port SRAM Download PDF

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Publication number
CN105097015A
CN105097015A CN201410182749.2A CN201410182749A CN105097015A CN 105097015 A CN105097015 A CN 105097015A CN 201410182749 A CN201410182749 A CN 201410182749A CN 105097015 A CN105097015 A CN 105097015A
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China
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switch
transistor
port
fpdp
connects
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CN201410182749.2A
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CN105097015B (en
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李智
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中芯国际集成电路制造(上海)有限公司
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Abstract

A dual-port SRAM comprises a comparison unit, a control unit and N selection units. The comparison unit is adapted to output a first level to N selection units and the control unit when the address signals of two groups of address ports are equal, Otherwise the comparison unit outputs a second level to N selection units and the control unit. The n-th selection unit is adapted to select the data of the n-th data port in the first group of the data ports to output when receiving the first level, and select the data of the n-th data port in the second group of the data ports to output when receiving the second level. The dual-port SRAM provided in the invention reduces noise when two entities read the memory cell for the same address in the dual-port SRAM simultaneously.

Description

Dual-port SRAM

Technical field

The present invention relates to memory technology field, particularly a kind of dual-port SRAM.

Background technology

Static RAM (SRAM, StaticRandomAccessMemory) is the one of random access memory.So-called " static state ", as long as refer to that this storer keeps energising, the data that the inside stores just can constantly keep.Relatively, the data stored by dynamic RAM (DRAM, DynamicRandomAccessMemory) the inside just need to be updated periodically.When electric power supply stops, the data that SRAM stores still can disappear, and this is different with the ROM (read-only memory) (ROM, Read-OnlyMemory) that can also store data after a loss of power or flash memory (FlashMemory).

Carrying out in the control system of dispersion treatment having multiple CPU, in order to transmit data between CPU, often sharing same SRAM.Accessing the efficiency of same SRAM in order to improve multiple CPU, usually adopting dual-port SRAM to store data.Dual-port SRAM adopts two groups of independently address bus, data bus and control buss, allow two independently entity (such as CPU) it is accessed simultaneously.Fig. 1 is the structural representation of common a kind of dual-port SRAM10, and described dual-port SRAM10 comprises the first group address port ADDR1, the second group address port ADDR2, first group of FPDP DOUT1, second group of FPDP DOUT2, first select signal input port , the second chip selection signal input port , the first clock signal input terminal mouth CLK1, second clock signal input port CLK2, the first output enable port , the second output enable port , first write enable port and second writes enable port .

Particularly, described first group address port ADDR1 and described second group address port ADDR2 is suitable for the address signal receiving storage unit access, and its port number is identical with the figure place of described address signal; Described first group of FPDP DOUT1 and described second group of FPDP DOUT2 is suitable for transmitting data, and its port number is identical with the data bits of transmission; Described first selects signal input port with described second chip selection signal input port be suitable for receiving chip selection signal; Described first clock signal input terminal mouth CLK1 and described second clock signal input port CLK2 is suitable for input clock signal; Described first output enable port with described second output enable port be suitable for receiving output enable signal; Described first writes enable port enable port is write with described second be suitable for receiving write enable signal.Whether described chip selection signal controls to operate described dual-port SRAM10, and described output enable signal controls the whether exportable data of described dual-port SRAM10, and described write enable signal controls whether can carry out write operation to described dual-port SRAM10.Those skilled in the art know the specific works principle of described dual-port SRAM10, do not repeat them here.

Inner at described dual-port SRAM10, also comprise the first internal clock generator circuit, the first internal clocking receiving end, the second internal clock generator circuit, the second internal clocking receiving end, the first row decoding scheme, first row decoding scheme, the second column decode circuitry, secondary series decoding scheme and multiple storage unit.Described first internal clock generator circuit is suitable for selecting signal input port according to described first the clock signal that the chip selection signal received and described first clock signal input terminal mouth CLK1 receive produces the first internal clock signal, and exports described first internal clock signal to described first internal clocking receiving end.After described first internal clocking receiving end receives described first internal clocking, described the first row decoding scheme and described first row decoding scheme carry out decoding to the address signal that described first group address port ADDR1 receives, and are operated corresponding storage unit by wordline and bit line.Described second internal clock generator circuit is suitable for according to described second chip selection signal input port the clock signal that the chip selection signal received and described second clock signal input port CLK2 receive produces the second internal clock signal, and exports described second internal clock signal to described second internal clocking receiving end.After described second internal clocking receiving end receives described second internal clocking, described second column decode circuitry and described secondary series decoding scheme carry out decoding to the address signal that described second group address port ADDR2 receives, and are operated corresponding storage unit by wordline and bit line.

Fig. 2 is the circuit diagram of common a kind of dual-port SRAM memory cell, and described dual-port SRAM memory cell comprises: first P21, second that pulls up transistor pulls up transistor P22, the first pull-down transistor N21, the second pull-down transistor N22, the first transmission transistor N23, the second transmission transistor N24, the 3rd transmission transistor N25 and the 4th transmission transistor N26.Wherein, described first P21 and described second P22 that pulls up transistor that pulls up transistor is PMOS, and described first pull-down transistor N21, described second pull-down transistor N22, described first transmission transistor N23, described second transmission transistor N24, described 3rd transmission transistor N25 and described 4th transmission transistor N26 are NMOS tube.

Particularly, described first source electrode pulling up transistor P21 is connected the first power end Vdd with described second source electrode pulling up transistor P22, described first grid pulling up transistor P21 connects the grid of described first pull-down transistor N21, described second drain electrode pulling up transistor P22, the drain electrode of described second pull-down transistor N22, the source electrode of described second transmission transistor N24 and the source electrode of described 4th transmission transistor N26, described first drain electrode pulling up transistor P21 connects the drain electrode of described first pull-down transistor N21, described second grid pulling up transistor P22, the grid of described second pull-down transistor N22, the source electrode of described first transmission transistor N23 and the source electrode of described 3rd transmission transistor N25, the source electrode of described first pull-down transistor N21 is connected second source end Vss with the source electrode of described second pull-down transistor N22, the supply voltage that the supply voltage that described second source end Vss provides provides lower than described first power end Vdd, the grid of described first transmission transistor N23 is connected the first wordline WL1 with the grid of described second transmission transistor N24, and the drain electrode of described first transmission transistor N23 connects the first bit line BL1, the grid of described 3rd transmission transistor N25 is connected the second wordline WL2 with the grid of described 4th transmission transistor N26, and the drain electrode of described 3rd transmission transistor N23 connects the second bit line BL2, the drain electrode of described second transmission transistor N24 connects the 3rd bit line BLB1, the drain electrode of described 4th transmission transistor N26 connects the 4th bit line BLB2.By applying corresponding voltage to described first wordline WL1, described second wordline WL2, described first bit line BL1, described second bit line BL2, described 3rd bit line BLB1 and described 4th bit line BLB2, read-write operation can be carried out to the first back end D1 and the second back end D2.

For the dual-port SRAM memory cell shown in Fig. 2, cannot allow two independently entity write operation is carried out to it simultaneously, but allow two independently entity read operation is carried out to it simultaneously.But when two independently entity carries out read operation to it simultaneously, the electric current flowing through pull-down transistor is comparatively large, causes the noise of described dual-port SRAM memory cell to increase.

Summary of the invention

What the present invention solved is two independently entity read the storage unit of same address in dual-port SRAM simultaneously and produce the problem of large noise.

For solving the problem, the invention provides a kind of dual-port SRAM, comprise the first group address port, the second group address port, first group of FPDP, second group of FPDP, the first internal clock generator circuit, the first internal clocking receiving end, the second internal clock generator circuit and second internal clocking receiving end, described dual-port SRAM also comprises comparing unit, control module and N number of selection unit, and N is the port number of described first group of FPDP;

Described comparing unit is suitable for exporting the first level when the address signal of described first group address port is identical with the address signal of described second group address port to described N number of selection unit and described control module, otherwise exports second electrical level to described N number of selection unit and described control module;

Described control module is suitable for forbidding that when receiving described first level described second internal clock generator circuit exports internal clock signal to described second internal clocking receiving end, allows described second internal clock generator circuit to export internal clock signal to described second internal clocking receiving end when receiving described second electrical level;

N-th selection unit is suitable for selecting when receiving described first level the data of the n-th FPDP in described first group of FPDP to export, the data of the n-th FPDP in described second group of FPDP are selected to export when receiving described second electrical level, 1≤n≤N.

Optionally, described comparing unit comprises the first AND circuit and M same OR circuit, and M is the port number of described first group address port;

M the first input end with OR circuit connects m address port in described first group address port, m the second input end with OR circuit connects m address port in described second group address port, m the output terminal with OR circuit connects m input end of described first AND circuit, the output terminal of described first AND circuit as the output terminal of described comparing unit, 1≤m≤M.

Optionally, described control module comprises the first phase inverter and the second AND circuit;

The input end of described first phase inverter is suitable for receiving described first level or described second electrical level, and the output terminal of described first phase inverter connects the first input end of described second AND circuit;

Second input end of described second AND circuit is suitable for the internal clock signal receiving described second internal clock generator circuit output, and the output terminal of described second AND circuit connects described second internal clocking receiving end.

Optionally, described n-th selection unit comprises the second phase inverter, the first transmission gate and the second transmission gate;

The input end of described second phase inverter connects the first control end of described first transmission gate and the second control end of described second transmission gate and is suitable for receiving described first level or described second electrical level, and the output terminal of described second phase inverter connects the second control end of described first transmission gate and the first control end of described second transmission gate;

The input end of described first transmission gate connects the n-th FPDP in described first group of FPDP, the output terminal of described first transmission gate connect described second transmission gate output terminal and as the output terminal of described n-th selection unit;

The input end of described second transmission gate connects the n-th FPDP in described second group of FPDP.

Optionally, described first transmission gate comprises the first PMOS and the first NMOS tube, and described second transmission gate comprises the second PMOS and the second NMOS tube;

The grid of described first PMOS is the second control end of described first transmission gate, the source electrode of described first PMOS connect described first NMOS tube drain electrode and as the input end of described first transmission gate, the drain electrode of described first PMOS connects the source electrode of described first NMOS tube and as the output terminal of described first transmission gate, the grid of described first NMOS tube is the first control end of described first transmission gate;

The grid of described second PMOS is the second control end of described second transmission gate, the source electrode of described second PMOS connect described second NMOS tube drain electrode and as the input end of described second transmission gate, the drain electrode of described second PMOS connects the source electrode of described second NMOS tube and as the output terminal of described second transmission gate, the grid of described second NMOS tube is the first control end of described second transmission gate.

Compared with prior art, technical scheme of the present invention has the following advantages:

Dual-port SRAM provided by the invention, whether the address signal being compared the first group address port by comparing unit identical with the address signal of the second group address port, can judge two independently entity whether the storage unit of same address is read simultaneously.If two independently entity be the storage unit of same address is read simultaneously, then allow to carry out read operation by described first group address port, and no thoroughfare, and described second group address port carries out read operation, selected the output data of data output as second group of FPDP of first group of FPDP by selection unit; If two independently entity be not the storage unit of same address is read simultaneously, then allow to carry out read operation by described first group address port and described second group address port, described selection unit selects the data of second group of FPDP to export.

By dual-port SRAM provided by the invention, when two independently entity reads the storage unit of same address simultaneously, actual is read described storage unit by a group address port.Therefore, the electric current flowing through the pull-down transistor in described storage unit is reduced to half of the prior art, and the noise of described storage unit reduces.

Further, the noise of described storage unit reduces, and when the supply voltage of described SRAM reduces, described storage unit keeps the ability of data to strengthen, and described SRAM is applied in the system of low supply voltage.Further, when two independently entity reads the storage unit of same address simultaneously, only the current potential of a bit lines need be dragged down, compared with being dragged down by the current potential of two bit lines with prior art, improve reading speed.

Further, by dual-port SRAM provided by the invention, when two independently entity reads the storage unit of same address simultaneously, no thoroughfare, and described second group address port carries out read operation, all do not work with the circuit unit of described second group address port auxiliary work, save circuit power consumption.

Accompanying drawing explanation

Fig. 1 is the structural representation of common a kind of dual-port SRAM;

Fig. 2 is the circuit diagram of common a kind of dual-port SRAM memory cell;

Fig. 3 is the structural representation of the dual-port SRAM that the embodiment of the present invention provides;

Fig. 4 is the electrical block diagram of the comparing unit that the embodiment of the present invention provides;

Fig. 5 is the electrical block diagram of the control module that the embodiment of the present invention provides;

Fig. 6 is the electrical block diagram of a kind of selection unit that the embodiment of the present invention provides;

Fig. 7 is the electrical block diagram of the another kind of selection unit that the embodiment of the present invention provides;

Fig. 8 is the electrical block diagram of the another kind of selection unit that the embodiment of the present invention provides.

Embodiment

With reference to the dual-port SRAM memory cell shown in figure 2, described first back end D1 and described second back end D2 stores binary data 0 and 1 respectively.When two independently entity reads described dual-port SRAM memory cell simultaneously, described first bit line BL1, described 3rd bit line BLB1, described second bit line BL2 and described 4th bit line BLB2 is first precharged to a predeterminated voltage (being generally the supply voltage that described first power end Vdd provides), then described first transmission transistor N23 is controlled, described second transmission transistor N24, described 3rd transmission transistor N25 and described 4th transmission transistor N26 conducting, the binary data that described first back end D1 stores is read on described first bit line BL1 and described second bit line BL2, the binary data that described second back end D2 stores is read on described 3rd bit line BLB1 and described 4th bit line BLB2.Data on described first bit line BL1 and described 3rd bit line BLB1 are back to an entity by one group of FPDP, and the data on described second bit line BL2 and described 4th bit line BLB2 are back to another entity by another group FPDP.

Assuming that described first back end D1 stores binary data 0, described second back end D2 stores binary data 1, when reading described storage unit, described first pull-down transistor N21 conducting, described second pull-down transistor N22 ends.When two independently entity reads described dual-port SRAM memory cell simultaneously, flow through the corresponding increase of electric current of described first pull-down transistor N21, therefore, the voltage of described first back end D1 raises, described dual-port SRAM memory cell keeps the reduced capability of data, and namely the noise of described dual-port SRAM memory cell becomes large.When the supply voltage that described first power end Vdd provides reduces, described dual-port SRAM memory cell keeps the ability of data to weaken further, and thus described dual-port SRAM memory cell can not be applied in the system of low supply voltage.And, when two independently entity reads described dual-port SRAM memory cell simultaneously, need the binary data 0 that could obtain described first back end D1 storage after all being dragged down by the current potential of the current potential of described first bit line BL1 and described second bit line BL2, reading speed is slow.

Based on this, the invention provides a kind of dual-port SRAM, when two independently entity reads the storage unit of same address simultaneously, no thoroughfare, and the second group address port carries out read operation, and the data of being carried out read operation acquisition by the first group address port are supplied to described two independently entities, to reduce the noise of described dual-port SRAM memory cell.

For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.

Fig. 3 is the structural representation of the dual-port SRAM that the embodiment of the present invention provides, and described dual-port SRAM comprises the first group address port, the second group address port, first group of FPDP, second group of FPDP, first select signal input port , the second chip selection signal input port , the first clock signal input terminal mouth CLK1, second clock signal input port CLK2, the first output enable port , the second output enable port , first write enable port , second write enable port , the first internal clock generator circuit 301, first internal clocking receiving end 302, second internal clock generator circuit 303 and the second internal clocking receiving end 304.Described dual-port SRAM also comprises the first row decoding scheme, first row decoding scheme, the second column decode circuitry, secondary series decoding scheme and storage unit, and the structure of described storage unit can as shown in Figure 2, also can be the structure similar with Fig. 2.Described first selects signal input port , described second chip selection signal input port , described first clock signal input terminal mouth CLK1, described second clock signal input port CLK2, described first output enable port , described second output enable port , described first write enable port and described second writes enable port , described first internal clock generator circuit 301, described first internal clocking receiving end 302, described second internal clock generator circuit 303, described second internal clocking receiving end 304, described the first row decoding scheme, described first row decoding scheme, similar in the function of described second column decode circuitry and described secondary series decoding scheme and prior art, do not repeat them here.

Usually, described first group address port and described second group address port include multiple address port, and each address port is suitable for input one bit address signal, and the port number of described first group address port is identical with the port number of described second group address port; Described first group of FPDP and described second group of FPDP include multiple FPDP, and each FPDP is suitable for transmitting a data, and the port number of described first group of FPDP is identical with the port number of described second group of FPDP.The port number of described first group address port and the port number of described first group of FPDP are determined according to the quantity of the storage unit in described dual-port SRAM, for more clearly describing dual-port SRAM provided by the invention, in embodiments of the present invention, comprise two address ports for described first group address port, described first group of FPDP comprise two FPDP and be described.

Particularly, described first group address port comprises address port A11 and address port A12, described second group address port comprises address port A21 and address port A22, and described address port A21 and described address port A11 is corresponding, and described address port A22 and described address port A12 is corresponding; Described first group of FPDP comprises FPDP D11 and FPDP D12, described second group of FPDP comprises FPDP D21 and FPDP D22, described FPDP D21 and described FPDP D11 is corresponding, and described FPDP D22 and described FPDP D12 is corresponding.

Described dual-port SRAM also comprises comparing unit 31, control module 32 and N number of selection unit, and N is the port number of described first group of FPDP.In the present embodiment, the port number of described first group of FPDP is 2, and therefore, described dual-port SRAM also comprises described comparing unit 31, described control module 32, selection unit 331 and selection unit 332.

Described comparing unit 31 is suitable for the address signal of more described first group address port and the address signal of described second group address port, exports comparative level according to comparative result by the output terminal Out1 of described comparing unit 31.The address signal of described first group address port is provided by the entity reading described dual-port SRAM by described first group address port, and the address signal of described second group address port is provided by the entity reading described dual-port SRAM by described second group address port.Particularly, when the address signal of described first group address port is identical with the address signal of described second group address port, described comparing unit 31 exports the first level to described selection unit 331, described selection unit 332 and described control module 32; When the address signal of described first group address port is not identical with the address signal of described second group address port, described comparing unit 31 exports second electrical level to described selection unit 331, described selection unit 332 and described control module 32.

In prior art, the internal clock signal that the first internal clock generator circuit in dual-port SRAM produces directly exports the first internal clocking receiving end to, and the internal clock signal that the second internal clock generator circuit produces directly exports the second internal clocking receiving end to.And in technical solution of the present invention, the internal clock signal that described first internal clock generator circuit 301 produces still directly exports described first internal clocking receiving end 302 to, but the internal clock signal that described second internal clock generator circuit 303 produces is subject to the control of described control module 32.Particularly, described control module 32 forbids that when receiving described first level described second internal clock generator circuit 303 exports internal clock signal to described second internal clocking receiving end 304, make described second column decode circuitry and described secondary series decoding scheme cannot carry out decoding to the address signal of the described second group address port of input, no thoroughfare, and described second group address port reads described dual-port SRAM; Described control module 32 allows described second internal clock generator circuit 303 clock signal to described second internal clocking receiving end 304 when receiving described second electrical level, make described second column decode circuitry and the address signal of described secondary series decoding scheme to the described second group address port of input carry out decoding, allow to read described dual-port SRAM by described second group address port.The concrete level magnitudes of described first level and described second electrical level can set according to the actual requirements, and in embodiments of the present invention, described first level is high level, and described second electrical level is low level.

In described N number of selection unit, n-th selection unit is suitable for selecting when receiving described first level the data of the n-th FPDP in described first group of FPDP to export, the data of the n-th FPDP in described second group of FPDP are selected to export when receiving described second electrical level, 1≤n≤N.

Particularly, described selection unit 331 is suitable for receiving level, the data of described FPDP D11 and the data of described FPDP D12 that described comparing unit 31 exports.When described comparing unit 31 exports described first level, the output terminal Out2 of described selection unit 331 exports the data of described FPDP D11; When described comparing unit 31 exports described second electrical level, the output terminal Out2 of described selection unit 331 exports the data of described FPDP D21.

Described selection unit 332 is suitable for receiving level, the data of described FPDP D12 and the data of described FPDP D22 that described comparing unit 31 exports.When described comparing unit 31 exports described first level, the output terminal Out3 of described selection unit 332 exports the data of described FPDP D12; When described comparing unit 31 exports described second electrical level, the output terminal Out3 of described selection unit 332 exports the data of described FPDP D22.

For access two of described dual-port SRAM independently entity be a CPU and the 2nd CPU, the principle of work of the described dual-port SRAM that the following brief description embodiment of the present invention provides.

When a described CPU and described 2nd CPU reads described dual-port SRAM simultaneously, a described CPU provides the access unit address signal needing to read to described first group address port, described 2nd CPU provides the access unit address signal needing to read to described second group address port.Meanwhile, a described CPU also selects signal input port to described first , described first clock signal input terminal mouth CLK1, described first output enable port and described first writes enable port there is provided corresponding signal, described 2nd CPU is also to described second chip selection signal input port , described second clock signal input port CLK2, described second output enable port and described second writes enable port corresponding signal is provided.How those skilled in the art provides corresponding signal if knowing, do not repeat them here.

If a described CPU and described 2nd CPU singly reads the same storage in described dual-port SRAM, then described first group address port is identical with the address of described second group address port, and described comparing unit 31 produces described first level through comparing.After described control module 32 receives described first level, forbid that described second internal clock generator circuit 303 provides internal clock signal to described second internal clocking receiving end 304, described second column decode circuitry and described secondary series decoding scheme cannot carry out decoding to the address signal that described 2nd CPU provides, and forbid that described 2nd CPU reads described dual-port SRAM by described second group address port.A described CPU reads described dual-port SRAM by described first group address port, and the data of reading return a described CPU by described first group of FPDP.Described N number of selection unit, after receiving described first level, selects the data of described first group of FPDP to export.What read due to a described CPU and described 2nd CPU is the storage unit of same address, and therefore, the data that described N number of selection unit exports are the data that described 2nd CPU will read.

If a described CPU and described 2nd CPU singly reads the same storage in described dual-port SRAM, then described first group address port is not identical with the address of described second group address port, and described comparing unit 31 produces described second electrical level through comparing.After described control module 32 receives described second electrical level, described second internal clock generator circuit 303 is allowed to provide internal clock signal to described second internal clocking receiving end 304, described second column decode circuitry and described secondary series decoding scheme carry out decoding to the address signal that described 2nd CPU provides, and allow described 2nd CPU to read described dual-port SRAM by described second group address port.A described CPU reads described dual-port SRAM by described first group address port, and the data of reading return a described CPU by described first group of FPDP; Described 2nd CPU reads described dual-port SRAM by described second group address port, and the data of reading are exported by described second group of FPDP.Described N number of selection unit, after receiving described second electrical level, selects the data of described second group of FPDP to export, and the data that described N number of selection unit exports are the data that described 2nd CPU will read.

Dual-port SRAM provided by the invention, when two independently entity reads the storage unit of same address in described dual-port SRAM simultaneously, actual is read described dual-port SRAM by a group address port.Therefore, compared with prior art, the electric current flowing through the pull-down transistor in described storage unit is reduced to half of the prior art, and the noise of described storage unit reduces.The noise of described storage unit reduces, and when the supply voltage of described SRAM reduces, described storage unit keeps the ability of data to strengthen, and described SRAM is applied in the system of low supply voltage.Further, when two independently entity reads the storage unit of same address simultaneously, only the current potential of a bit lines need be dragged down, compared with being dragged down by the current potential of two bit lines with prior art, improve reading speed.Further, when two independently entity reads the storage unit of same address simultaneously, no thoroughfare, and described second group address port carries out read operation, does not all work, save circuit power consumption in described dual-port SRAM with the circuit unit of described second group address port auxiliary work.

The embodiment of the present invention provides a kind of particular circuit configurations of described comparing unit 31, as shown in Figure 4.Described comparing unit 31 comprises the first AND circuit 43 and M same OR circuit, and M is the port number of described first group address port.In the present embodiment, still comprise two ports for described first group address port, described comparing unit 31 comprises two same OR circuit: with OR circuit 41 with OR circuit 42.Described same OR circuit 41 and described same OR circuit 42 are the same OR circuit of two inputs, and described first AND circuit 43 is two input AND circuit.

Particularly, the first input end of described same OR circuit 41 connects described address port A11, second input end of described same OR circuit 41 connects described address port A21, and the output terminal of described same OR circuit 41 connects first input end of described first AND circuit 43; The first input end of described same OR circuit 42 connects described address port A21, and the second input end of described same OR circuit 42 connects described address port A22, and the output terminal of described same OR circuit 42 connects second input end of described first AND circuit 43.The output terminal of described first AND circuit 43, as the output terminal Out1 of described comparing unit 31, is suitable for exporting described first level or described second electrical level.

When the address signal of described first group address port is identical with the address signal of described second group address port, described same OR circuit 41 and described same OR circuit 42 all export high level, through described first AND circuit 43 carry out with process after, described first AND circuit 43 exports high level, i.e. described first level; When the address signal of described first group address port is not identical with the address signal of described second group address port, an output low level is had at least in described same OR circuit 41 and described same OR circuit 42, through described first AND circuit 43 carry out with process after, described first AND circuit 43 output low level, i.e. described second electrical level.

It should be noted that, described comparing unit 31 is not limited to the particular circuit configurations that the present embodiment provides, those skilled in the art also can adopt other logical circuits to realize the function of described comparing unit 31, therefore, the particular circuit configurations that the present embodiment provides should as the restriction to described comparing unit 31.

The embodiment of the present invention provides a kind of particular circuit configurations of described control module 32, as shown in Figure 5.Described control module 32 comprises the first phase inverter INV1 and the second AND circuit 50, and described second AND circuit 50 is two input AND circuit.

Particularly, the input end of described first phase inverter INV1 is suitable for receiving described first level or described second electrical level, namely the input end of described first phase inverter INV1 connects the output terminal Out1 of described comparing unit 31, and the output terminal of described first phase inverter INV1 connects the first input end of described second AND circuit 50; Second input end of described second AND circuit 50 is suitable for the internal clock signal receiving described second internal clock generator circuit 303 output, and the output terminal of described second AND circuit 50 connects described second internal clocking receiving end 304.

The embodiment of the present invention provides the particular circuit configurations of a kind of described selection unit 331 and described selection unit 332, due to the similar of described selection unit 331 and described selection unit 332, in the present embodiment, be only described for described selection unit 331.With reference to figure 6, described selection unit 331 comprises the second phase inverter INV2, the first transmission gate PG1 and the second transmission gate PG2.

Particularly, the input end of described second phase inverter INV2 connects first control end of described first transmission gate PG1 and second control end of described second transmission gate PG2 and is suitable for receiving described first level or described second electrical level, namely the input end of described second phase inverter INV2 connects first control end of described first transmission gate PG1, described second control end of the second transmission gate PG2 and the output terminal Out1 of described comparing unit 31, the output terminal of described second phase inverter INV2 connects second control end of described first transmission gate PG1 and first control end of described second transmission gate PG2.

Described first transmission gate PG1 comprises the first PMOS P51 and the first NMOS tube N51.The grid of described first PMOS P51 is second control end of described first transmission gate PG1, the source electrode of described first PMOS P51 connect described first NMOS tube N51 drain electrode and as the input end of described first transmission gate PG1, the drain electrode of described first PMOS P51 connects the source electrode of described first NMOS tube N51 and as the output terminal of described first transmission gate PG1, the grid of described first NMOS tube N51 is first control end of described first transmission gate PG1.

Described second transmission gate PG2 comprises the second PMOS P52 and the second NMOS tube N52.The grid of described second PMOS P52 is second control end of described second transmission gate PG2, the source electrode of described second PMOS P52 connect described second NMOS tube N52 drain electrode and as the input end of described second transmission gate PG2, the drain electrode of described second PMOS P52 connects the source electrode of described second NMOS tube N52 and as the output terminal of described second transmission gate PG2, the grid of described second NMOS tube N52 is first control end of described second transmission gate PG2.

The input end of described first transmission gate PG1 connects described FPDP D11, the output terminal of described first transmission gate PG1 connects the output terminal of described second transmission gate PG2 and as the output terminal Out2 of described selection unit 331, the input end of described second transmission gate PG2 connects described FPDP D21.

When described comparing unit 31 produces described first level, described first NMOS tube N51 and described first PMOS P51 conducting, described second NMOS tube N52 and described second PMOS P52 cut-off, described selection unit 331 selects the data of described FPDP D11 to export; When described comparing unit 31 produces described second electrical level, described first NMOS tube N51 and described first PMOS P51 cut-off, described second NMOS tube N52 and described second PMOS P52 conducting, described selection unit 331 selects the data of described FPDP D21 to export.

The embodiment of the present invention also provides the particular circuit configurations of a kind of described selection unit 331 and described selection unit 332, due to the similar of described selection unit 331 and described selection unit 332, in the present embodiment, be only described for described selection unit 331.With reference to figure 7, described selection unit 331 comprises the first K switch 11 and second switch K12.

Particularly, the control end of described first K switch 11 connects the control end of described second switch K12 and is suitable for receiving described first level or described second electrical level, namely the control end of described first K switch 11 connects the control end of described second switch K12 and the output terminal Out1 of described comparing unit 31, the first end of described first K switch 11 connects described FPDP D11, the second end of described first K switch 11 connect described second switch K12 the second end and as the output terminal Out2 of described selection unit 331; The first end of described second switch K12 connects described FPDP D21.

When the control end of described first K switch 11 receives described first level, the first end of described first K switch 11 and the second end conducting of described first K switch 11, otherwise disconnect; When the control end of described second switch K12 receives described second electrical level, the first end of described second switch K12 and the second end conducting of described second switch K12, otherwise disconnect.

In the present embodiment, described first K switch 11 is can the 3rd NMOS tube, and described second switch K12 is can the 3rd PMOS.The grid of described 3rd NMOS tube is the control end of described first K switch 11, and the drain electrode of described 3rd NMOS tube is the first end of described first K switch 11, and the source electrode of described 3rd NMOS tube is the second end of described first K switch 11; The grid of described 3rd PMOS is the control end of described second switch K12, and the source electrode of described 3rd PMOS is the first end of described second switch K12, and the drain electrode of described 3rd PMOS is second end of described second switch K12.In other embodiments, the device that described first K switch 11 and described second switch K12 also can have switching function for other, the present invention is not construed as limiting this.

The embodiment of the present invention also provides the particular circuit configurations of a kind of described selection unit 331 and described selection unit 332, due to the similar of described selection unit 331 and described selection unit 332, in the present embodiment, be only described for described selection unit 331.With reference to figure 8, described selection unit 331 comprises the 3rd phase inverter INV3, the 3rd K switch 13 and the 4th K switch 14.

The input end of described 3rd phase inverter INV3 is suitable for receiving described first level or described second electrical level, namely the input end of described 3rd phase inverter INV3 connects the output terminal Out1 of described comparing unit 31, and the output terminal of described 3rd phase inverter INV3 connects the control end of described 3rd K switch 13 and the control end of described 4th K switch 14; The first end of described 3rd K switch 13 connects described FPDP D11, the second end of described 3rd K switch 13 connect described 4th K switch 14 the second end and as the output terminal Out2 of described selection unit 331; The first end of described 4th K switch 14 connects described FPDP D21.

When the input end of described 3rd phase inverter INV3 receives described first level, the first end of described 3rd K switch 13 and the second end conducting of described first K switch 13, otherwise disconnect; When the input end of described 3rd phase inverter INV3 receives described second electrical level, the first end of described 4th K switch 14 and the second end conducting of described second switch K14, otherwise disconnect.

In the present embodiment, described 3rd switch is K13 the 4th PMOS, and described 4th K switch 14 is the 4th NMOS tube.The grid of described 4th PMOS is the control end of described 3rd K switch 13, and the source electrode of described 4th PMOS is the first end of described 3rd K switch 13, and the drain electrode of described 4th PMOS is the second end of described 3rd K switch 13; The grid of described 4th NMOS tube is the control end of described 4th K switch 14, and the drain electrode of described 4th NMOS tube is the first end of described 4th K switch 14, and the source electrode of described 4th NMOS tube is the second end of described 4th K switch 14.In other embodiments, the device that described 3rd K switch 13 and described 4th K switch 14 also can have switching function for other, the present invention is not construed as limiting this.

Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (10)

1. a dual-port SRAM, comprise the first group address port, the second group address port, first group of FPDP, second group of FPDP, the first internal clock generator circuit, the first internal clocking receiving end, the second internal clock generator circuit and second internal clocking receiving end, it is characterized in that, also comprise comparing unit, control module and N number of selection unit, N is the port number of described first group of FPDP;
Described comparing unit is suitable for exporting the first level when the address signal of described first group address port is identical with the address signal of described second group address port to described N number of selection unit and described control module, otherwise exports second electrical level to described N number of selection unit and described control module;
Described control module is suitable for forbidding that when receiving described first level described second internal clock generator circuit exports internal clock signal to described second internal clocking receiving end, allows described second internal clock generator circuit to export internal clock signal to described second internal clocking receiving end when receiving described second electrical level;
N-th selection unit is suitable for selecting when receiving described first level the data of the n-th FPDP in described first group of FPDP to export, the data of the n-th FPDP in described second group of FPDP are selected to export when receiving described second electrical level, 1≤n≤N.
2. dual-port SRAM as claimed in claim 1, is characterized in that, described comparing unit comprises the first AND circuit and M same OR circuit, and M is the port number of described first group address port;
M the first input end with OR circuit connects m address port in described first group address port, m the second input end with OR circuit connects m address port in described second group address port, m the output terminal with OR circuit connects m input end of described first AND circuit, the output terminal of described first AND circuit as the output terminal of described comparing unit, 1≤m≤M.
3. dual-port SRAM as claimed in claim 1 or 2, it is characterized in that, described control module comprises the first phase inverter and the second AND circuit;
The input end of described first phase inverter is suitable for receiving described first level or described second electrical level, and the output terminal of described first phase inverter connects the first input end of described second AND circuit;
Second input end of described second AND circuit is suitable for the internal clock signal receiving described second internal clock generator circuit output, and the output terminal of described second AND circuit connects described second internal clocking receiving end.
4. dual-port SRAM as claimed in claim 3, it is characterized in that, described n-th selection unit comprises the second phase inverter, the first transmission gate and the second transmission gate;
The input end of described second phase inverter connects the first control end of described first transmission gate and the second control end of described second transmission gate and is suitable for receiving described first level or described second electrical level, and the output terminal of described second phase inverter connects the second control end of described first transmission gate and the first control end of described second transmission gate;
The input end of described first transmission gate connects the n-th FPDP in described first group of FPDP, the output terminal of described first transmission gate connect described second transmission gate output terminal and as the output terminal of described n-th selection unit;
The input end of described second transmission gate connects the n-th FPDP in described second group of FPDP.
5. dual-port SRAM as claimed in claim 4, it is characterized in that, described first transmission gate comprises the first PMOS and the first NMOS tube, and described second transmission gate comprises the second PMOS and the second NMOS tube;
The grid of described first PMOS is the second control end of described first transmission gate, the source electrode of described first PMOS connect described first NMOS tube drain electrode and as the input end of described first transmission gate, the drain electrode of described first PMOS connects the source electrode of described first NMOS tube and as the output terminal of described first transmission gate, the grid of described first NMOS tube is the first control end of described first transmission gate;
The grid of described second PMOS is the second control end of described second transmission gate, the source electrode of described second PMOS connect described second NMOS tube drain electrode and as the input end of described second transmission gate, the drain electrode of described second PMOS connects the source electrode of described second NMOS tube and as the output terminal of described second transmission gate, the grid of described second NMOS tube is the first control end of described second transmission gate.
6. dual-port SRAM as claimed in claim 3, it is characterized in that, described n-th selection unit comprises the first switch and second switch;
The control end of described first switch connects the control end of described second switch and is suitable for receiving described first level or described second electrical level, the first end of described first switch connects the n-th FPDP in described first group of FPDP, the second end of described first switch connect described second switch the second end and as the output terminal of described n-th selection unit;
The first end of described second switch connects the n-th FPDP in described second group of FPDP;
When the control end of described first switch receives described first level, the first end of described first switch and the second end conducting of described first switch, otherwise disconnect;
When the control end of described second switch receives described second electrical level, the first end of described second switch and the second end conducting of described second switch, otherwise disconnect.
7. dual-port SRAM as claimed in claim 6, it is characterized in that, described first switch is the 3rd NMOS tube, and described second switch is the 3rd PMOS;
The grid of described 3rd NMOS tube is the control end of described first switch, and the drain electrode of described 3rd NMOS tube is the first end of described first switch, and the source electrode of described 3rd NMOS tube is the second end of described first switch;
The grid of described 3rd PMOS is the control end of described second switch, and the source electrode of described 3rd PMOS is the first end of described second switch, and the drain electrode of described 3rd PMOS is the second end of described second switch.
8. dual-port SRAM as claimed in claim 3, it is characterized in that, described n-th selection unit comprises the 3rd phase inverter, the 3rd switch and the 4th switch;
The input end of described 3rd phase inverter is suitable for receiving described first level or described second electrical level, and the output terminal of described 3rd phase inverter connects the control end of described 3rd switch and the control end of described 4th switch;
The first end of described 3rd switch connects the n-th FPDP in described first group of FPDP, the second end of described 3rd switch connect described 4th switch the second end and as the output terminal of described n-th selection unit;
The first end of described 4th switch connects the n-th FPDP in described second group of FPDP;
When the input end of described 3rd phase inverter receives described first level, the first end of described 3rd switch and the second end conducting of described first switch, otherwise disconnect;
When the input end of described 3rd phase inverter receives described second electrical level, the first end of described 4th switch and the second end conducting of described second switch, otherwise disconnect.
9. dual-port SRAM as claimed in claim 8, it is characterized in that, described 3rd switch is the 4th PMOS, and described 4th switch is the 4th NMOS tube;
The grid of described 4th PMOS is the control end of described 3rd switch, and the source electrode of described 4th PMOS is the first end of described 3rd switch, and the drain electrode of described 4th PMOS is the second end of described 3rd switch;
The grid of described 4th NMOS tube is the control end of described 4th switch, and the drain electrode of described 4th NMOS tube is the first end of described 4th switch, and the source electrode of described 4th NMOS tube is the second end of described 4th switch.
10. dual-port SRAM as claimed in claim 1, it is characterized in that, also comprise storage unit, described storage unit comprise first to pull up transistor, second to pull up transistor, the first pull-down transistor, the second pull-down transistor, the first transmission transistor, the second transmission transistor, the 3rd transmission transistor and the 4th transmission transistor;
Described first source electrode pulled up transistor is connected the first power end with described second source electrode pulled up transistor, described first grid pulled up transistor connects the grid of described first pull-down transistor, described second drain electrode pulled up transistor, the drain electrode of described second pull-down transistor, the source electrode of described second transmission transistor and the source electrode of described 4th transmission transistor, described first drain electrode pulled up transistor connects the drain electrode of described first pull-down transistor, described second grid pulled up transistor, the grid of described second pull-down transistor, the source electrode of described first transmission transistor and the source electrode of described 3rd transmission transistor,
The source electrode of described first pull-down transistor is connected second source end with the source electrode of described second pull-down transistor, the supply voltage that the supply voltage that described second source end provides provides lower than described first power end;
The grid of described first transmission transistor is connected the first wordline with the grid of described second transmission transistor, and the drain electrode of described first transmission transistor connects the first bit line;
The grid of described 3rd transmission transistor is connected the second wordline with the grid of described 4th transmission transistor, and the drain electrode of described 3rd transmission transistor connects the second bit line;
The drain electrode of described second transmission transistor connects the 3rd bit line;
The drain electrode of described 4th transmission transistor connects the 4th bit line.
CN201410182749.2A 2014-04-30 2014-04-30 dual-port SRAM CN105097015B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1477642A (en) * 2002-08-22 2004-02-25 三菱电机株式会社 Semiconductor storage for storing 3 value data signal
CN1783341A (en) * 2004-10-29 2006-06-07 株式会社瑞萨科技 Multiport semiconductor memory device
CN101196856A (en) * 2008-01-04 2008-06-11 太原理工大学 Double-port access single dynamic memory interface

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1477642A (en) * 2002-08-22 2004-02-25 三菱电机株式会社 Semiconductor storage for storing 3 value data signal
CN1783341A (en) * 2004-10-29 2006-06-07 株式会社瑞萨科技 Multiport semiconductor memory device
CN101196856A (en) * 2008-01-04 2008-06-11 太原理工大学 Double-port access single dynamic memory interface

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