CN105070762B - 三态金属氧化物半导体薄膜晶体管及其制备方法 - Google Patents

三态金属氧化物半导体薄膜晶体管及其制备方法 Download PDF

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CN105070762B
CN105070762B CN201510430849.7A CN201510430849A CN105070762B CN 105070762 B CN105070762 B CN 105070762B CN 201510430849 A CN201510430849 A CN 201510430849A CN 105070762 B CN105070762 B CN 105070762B
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韩德栋
郁文
王漪
石盼
张翼
黄伶灵
丛瑛瑛
董俊辰
张盛东
刘晓彦
康晋锋
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Abstract

本发明提供一种三态金属氧化物半导体薄膜晶体管及其制备方法，属于半导体行业、平板显示领域。该三态金属氧化物半导体薄膜晶体管从下到上依次为衬底、底层源漏电极、底层沟道层、底层栅介质层、栅电极、顶层栅介质层、顶层沟道层、顶层源漏电极，其中，顶层栅介质的厚度大于底层栅介质的厚度，或者顶层栅介质的介电常数小于底层栅介质的介电常数，同时，顶层沟道材料的电导率优于底层沟道材料的电导率。由于该结构是一个顶栅结构和一个底栅结构的叠加，则在转移特性上是上下两个器件转移特性的叠加，突破了传统的金属氧化物半导体薄膜晶体管的性能。

Description

三态金属氧化物半导体薄膜晶体管及其制备方法
技术领域
本发明涉及一种玻璃衬底或者塑料衬底上制备半导体薄膜晶体管的方法，属于半导体行业、平板显示领域。
背景技术
二十一世纪是信息化的时代，显示技术也飞速地发展，先后诞生了CRT显示器、PDP显示器、LCD显示器、OLED显示器等，这些平板显示器在亮度、对比度、色彩、功耗和体积上都得到全面的提高。有关新型显示技术的研究一直都是平板显示领域的研究热点，包括目前受到广泛关注的透明显示、柔性显示、裸眼3D显示技术。
硅基材料由于对光敏感且稳定性较差，已经不能满足新型显示技术的需求。Poly-Si TFT虽然具有高迁移率，但是其均匀性较差，显示质量也受到了影响。然而，氧化物薄膜晶体管具有非晶硅和多晶硅材料都不具有的优势，表现如下：1、氧化物TFT载流子迁移率高(10-100cm2V-1s-1)，然而传统的非晶硅薄膜晶体管迁移率较低(>1cm2V-1s-1)。2、氧化物薄膜晶体管可以通过掺入重金属元素(如In、Ga等)来实现非晶态，在实际应用中具有很好的均匀性。3、氧化物半导体大多数为宽禁带材料，在可见光范围内是透明的，所以氧化物薄膜晶体管的发现大大加速了透明显示技术的发展。4、氧化物材料在光照射下难以产生光生载流子，对可见光的敏感度较低。5、氧化物TFT的制备工艺比较广泛。氧化物薄膜材料的制备工艺也是多种多样，如射频磁控溅射法、增强型等离子气相沉积法、原子层淀积法、脉冲激光淀积法、分子束外延法、溶液涂覆法等。这些方法有的可以满足低温制备要求，因此可以促进柔性显示技术的发展。
发明内容
本发明的目的在于提供一种双沟道共栅结构的三态金属氧化物半导体薄膜晶体管及其制备方法。
本发明的技术方案如下：
一种三态金属氧化物半导体薄膜晶体管，其特征在于，从下到上依次为衬底、底层源漏电极、底层沟道层、底层栅介质层、栅电极、顶层栅介质层、顶层沟道层、顶层源漏电极，其中，顶层栅介质的厚度大于底层栅介质的厚度，或者顶层栅介质的介电常数小于底层栅介质的介电常数，同时，顶层沟道材料的电导率优于底层沟道材料的电导率。
三态金属氧化物半导体薄膜晶体管的制备方法，包括以下步骤：
1)在玻璃或者塑料衬底上淀积一层透明导电薄膜材料，然后光刻刻蚀出底层源漏电极；
2)生成一层半导体沟道层，然后光刻刻蚀出底层沟道层；
3)生长一层栅介质层，然后光刻刻蚀出底层栅介质层；
4)淀积一层透明导电薄膜材料，然后光刻刻蚀出栅电极；
5)生长一层栅介质层，然后光刻刻蚀出顶层栅介质层；
6)生成一层半导体沟道层，然后光刻刻蚀出顶层沟道层；
7)淀积一层透明导电薄膜材料，然后光刻刻蚀出顶层源、漏电极。
步骤1)所生长的源、漏电极，由透明导电薄膜材料ITO、AZO、GZO等形成。
步骤2)所生长的底层沟道，利用溅射工艺进行生长，沟道材料可以采用IGZO、ITO、ZTO、AZO、TiZO、HfZO、CaZO、NiZO、MZO、GdZO等金属氧化物半导体材料。
步骤3)所生长的底层栅介质材料，由二氧化硅，或者氮化硅、氧化铪、氧化铝、氧化锆等绝缘材料形成。
步骤4)所生长的栅电极，由透明导电材料ITO、AZO、GZO等形成。
步骤5)所生长的顶层栅介质材料，由二氧化硅，或者氮化硅、氧化铪、氧化铝、氧化锆等绝缘材料形成，顶层栅介质的厚度应大于底层栅介质，或者介电常数应小于底层栅介质，目的是通过此种方法来增大底栅器件的开启电压。
步骤6)所生长的顶层沟道，利用溅射工艺进行生长，沟道材料可以采用IGZO、ITO、ZTO、AZO、TiZO、HfZO、CaZO、NiZO、MZO、GdZO等金属氧化物半导体材料，顶层沟道材料的电导率应该优于底层沟道材料，或者通过增大顶层沟道的厚度，减小顶层沟道的氧分压来增大顶层沟道的电导率。
步骤7)所生长的顶层源、漏电极，由透明导电材料ITO、AZO、GZO等形成。
本发明的优点和积极效果：本发明的顶层沟道材料的导电性优于底层沟道，目的在于使得底栅器件的开态电流远高于顶栅器件的开态电流；顶层栅介质若与底层栅介质的材料一致，则顶层栅介质的厚度应该大于底层栅介质的厚度，若选用不同的材料，则顶层栅介质的介电常数应该小于底层栅介质的介电常数，这种方法的目的在于增大底栅器件的开启电压，使得底栅器件能够晚于顶栅器件开启。由于该结构是一个顶栅结构和一个底栅结构的叠加，则在转移特性上应当是上下两个器件转移特性的叠加，由于位于上方的底栅器件的阈值电压大于位于下方的顶栅器件的阈值电压，且开态电流远高于位于下方的顶栅器件，则在最终叠加以后的转移特性曲线的亚阈区将会出现一个短暂的平台，将此输出的信号值定义为“1”，将输出的关态电流定义为“0”，将输出的开态电流定义为“1”。通过此种方法制备的薄膜晶体管可输出具有“0、1、2”三个状态的转移特性曲线，突破了传统的金属氧化物半导体薄膜晶体管的性能。
附图说明
图1为本发明具体实例所描述的玻璃或者塑料衬底上制备薄膜晶体管的剖面结构示意图；
图2为本发明的薄膜晶体管在制备过程中的主要工艺步骤。
上述图中1-衬底；2-底层源、漏电极；3-底层沟道；4-底层栅介质；5-栅电极；6-顶层栅介质；7-顶层沟道；8-顶层源、漏电极。
具体实施方式
下面通过实例对本发明做进一步说明。需要注意的是，公布实例的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附权利要求的精神范围内，各种替换和修改都是可能的。因此，本发明不应局限于实例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。
本发明三态金属氧化物半导体薄膜晶体管形成于玻璃或者塑料衬底上，如图1所示。该三态金属氧化物半导体薄膜晶体管包括底层源、漏电极，底层沟道，底层栅介质，栅电极，顶层栅介质，顶层沟道层，顶层源、漏电极。底层源、漏电极位于衬底之上，底层沟道位于源漏电极之上，底层栅介质位于底层沟道之上，栅电极位于底层栅介质之上，顶层栅介质位于栅电极之上，顶层沟道位于顶层栅介质之上，顶层源漏电极位于顶层沟道之上。
所述三态金属氧化物半导体薄膜晶体管的制作方法的具体实例由图2(a)至图2(h)所示，包括以下步骤：
如图2(a)所示，衬底选用透明玻璃或者塑料衬底基板。
如图2(b)所示，采用磁控溅射技术生长一层150纳米厚的ITO等导电薄膜，然后光刻刻蚀形成底层源、漏电极。
如图2(c)所示，利用溅射工艺生长一层金属氧化物半导体材料作为底层沟道层。溅射过程中注意调控好沟道层的厚度及氧分压。
如图2(d)所示，利用PECVD生长一层50～250纳米厚的二氧化硅层，然后光刻刻蚀形成底层栅介质。
如图2(e)所示，采用磁控溅射技术生长一层150纳米厚的ITO等导电薄膜，然后光刻刻蚀出栅电极。
如图2(f)所示，利用PECVD生长一层50～250纳米厚的二氧化硅层，然后光刻刻蚀形成顶层栅介质。
如图2(g)所示利用溅射工艺生长一层金属氧化物半导体材料作为顶层沟道层。溅射过程中注意调控好沟道层的厚度及氧分压。
如图2(h)所示，采用磁控溅射技术生长一层150纳米厚的ITO等导电薄膜，然后光刻刻蚀形成顶层源、漏电极。

Claims (7)

1.一种三态金属氧化物半导体薄膜晶体管，其特征在于，该三态金属氧化物半导体薄膜晶体管由一个顶栅器件结构和一个底栅器件结构叠加构成，底栅器件的阈值电压大于顶栅器件的阈值电压，且底栅器件的开态电流高于顶栅器件的开态电流，该晶体管的结构具体是，从下到上依次为衬底、底层源漏电极、底层沟道层、底层栅介质层、栅电极、顶层栅介质层、顶层沟道层、顶层源漏电极，其中，顶层栅介质与底层栅介质采用不同材料，顶层栅介质的介电常数小于底层栅介质的介电常数，同时，顶层沟道材料的电导率优于底层沟道材料的电导率。
2.如权利要求1所述的三态金属氧化物半导体薄膜晶体管，其特征在于，通过增大顶层沟道层的厚度或减小顶层沟道的氧分压来增大顶层沟道的电导率。
3.如权利要求1所述的三态金属氧化物半导体薄膜晶体管，其特征在于，底层源漏电极或顶层源漏电极采用透明导电薄膜材料ITO、AZO、GZO。
4.如权利要求1所述的三态金属氧化物半导体薄膜晶体管，其特征在于，底层沟道层或顶层沟道层采用IGZO、ITO、ZTO、AZO、TiZO、HfZO、CaZO、NiZO、MZO、GdZO金属氧化物半导体材料。
5.如权利要求1所述的三态金属氧化物半导体薄膜晶体管，其特征在于，底层栅介质或顶层栅介质采用二氧化硅，或者氮化硅、氧化铪、氧化铝、氧化锆。
6.如权利要求1所述的三态金属氧化物半导体薄膜晶体管，其特征在于，栅电极采用透明导电材料ITO、AZO、GZO。
7.如权利要求1所述的三态金属氧化物半导体薄膜晶体管的制备方法，包括以下步骤：
1)在玻璃或者塑料衬底上淀积一层透明导电薄膜材料，然后光刻刻蚀出底层源漏电极；
2)生成一层半导体沟道层，然后光刻刻蚀出底层沟道层；
3)生长一层二氧化硅或者氮化硅、氧化铪、氧化铝、氧化锆作栅介质层，然后光刻刻蚀出底层栅介质层；
4)淀积一层ITO、AZO、GZO透明导电薄膜材料，然后光刻刻蚀出栅电极；
5)生长一层二氧化硅或者氮化硅、氧化铪、氧化铝、氧化锆作栅介质层，然后光刻刻蚀出顶层栅介质层；
6)生成一层半导体沟道层，然后光刻刻蚀出顶层沟道层；
7)淀积一层ITO、AZO、GZO透明导电薄膜材料，然后光刻刻蚀出顶层源、漏电极。
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