CN105051921A - Light emitting diode semiconductor structures having active regions comprising InGaN - Google Patents

Abstract

Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

Description

There is the LED semiconductor structure of the active area comprising InGaN

Technical field

The disclosure relate to semiconductor structure bodies and by have the active area comprising InGaN this type of semiconductor structure bodies manufacture luminescent device, manufacture the method for this type of luminescent device and comprise the device of this type of luminescent device.

Background technology

As the luminescent devices such as light-emitting diode (LED) be LED active area between antianode and negative electrode apply voltage time launch the electronic device of the electromagnetic radiation of visible ray form.LED comprises one or more semiconductor material layer usually, and compound is carried out in the electronics supplied by anode in described semiconductor material layer and the hole supplied by negative electrode.Along with electronics and hole compound in LED active area, energy discharges with the form of the photon sent from LED active area.

LED can be fabricated to and comprise dissimilar semi-conducting material on a large scale, it comprises such as III-V group semi-conductor material and II-V race semi-conducting material.The wavelength of the light sent from any specific LED be electronics and hole-recombination time the function of energy that discharges.Therefore, the wavelength of the light sent from LED is the function of the relative energy difference between electron energy level and hole energy level.Electron energy level and hole energy level are the function of following parameter at least in part: the structure (that is, crystal structure and orientation) of semi-conducting material composition, doping type and concentration, semi-conducting material and the quality of semi-conducting material of electronics and hole-recombination wherein occurs.Therefore, by optionally customizing composition and the structure of semi-conducting material in LED, the wavelength of the light that LED sends can optionally be customized.

Known in the artly manufacture the LED comprised as III-V group semi-conductor material such as III-nitride material.This type of group III-nitride LED known can the blueness of electromagnetic radiation-emitting spectrum and the radiation of green visual field, and known its can with relatively high power and luminosity (luminosity) work.

Summary of the invention

This summary of the invention part is provided to introduce a part of concept set in simplified form.These concepts describe in further detail in the specific descriptions of hereafter disclosed illustrative embodiments.Content part of the present invention is also not intended to key feature or the essential feature of specifying theme required for protection, also and the scope be not intended to for limiting theme required for protection.

In some embodiments, the disclosure comprises a kind of semiconductor structure bodies, it comprises base layer, the active area be arranged on described base layer, electronic barrier layer, p-type In _pga _1-pn body layer and p-type In _cga _1-cn contact layer.Described active area comprises multiple InGaN layer, and described multiple InGaN layer comprises at least one and comprises In _wga _1-wwell layer and at least one of N comprise In _bga _1-bthe screen of N, wherein 0.10≤w≤0.40,0.01≤b≤0.10.Described electronic barrier layer is arranged on the side relative with described base layer on described active area.Described electronic barrier layer comprises In _ega _1-en, wherein 0.00≤e≤0.02.P-type In _pga _1-pn body layer is arranged on described electronic barrier layer, and described In _pga _1-p0.01≤p≤0.08 in N body layer.P-type In _cga _1-cn contact layer is arranged on described p-type In _pga _1-pon N body layer, and In _cga _1-c0.00≤c≤0.10 in N contact layer.

In other execution modes, the disclosure comprises the luminescent device manufactured by described semiconductor structure bodies.

Such as, in some embodiments, the disclosure comprises a kind of luminescent device, described luminescent device comprises base layer, the active area be arranged on described base layer, the electronic barrier layer be arranged on described active area, the p-type In be arranged on described electronic barrier layer _pga _1-pn body layer and be arranged on described p-type In _pga _1-pp-type In on N body layer _cga _1-cn contact layer.Described active area comprises multiple InGaN layer, and described multiple InGaN layer comprises at least one InGaN well layer and is set directly at least one the InGaN screen at least one well layer described.The critical strain of described luminescent device can be about less than 1800.

In other execution mode, the disclosure comprises the method forming semiconductor structure bodies, and described method comprises provides base layer; Described base layer grows multiple InGaN layer to be formed with source region; The side that described active area is relative with described base layer grows electronic barrier layer; Described electronic barrier layer grows p-type In _pga _1-pn body layer, wherein 0.01≤p≤0.08; With at described p-type In _pga _1-pn body layer grows p-type In _cga _1-cn contact layer, wherein 0.00≤c≤0.10.The step growing described multiple InGaN layer comprises at least one at least In of growth _wga _1-wn well layer and at least one In of growth _bga _1-bn screen, wherein 0.10≤w≤0.40, and wherein 0.01≤b≤0.10.

In other execution mode, the disclosure comprises luminescent device, and it comprises the container of the visible wavelength at least substantially transparent for electromagnetic radiation, and is in the LED one or more as herein described in described container.Such as, the LED in described container can comprise anode contact, cathode contact and the active area between described anode contact and described cathode contact.Described active area comprises multiple InGaN layer, and can at least substantially be made up of InGaN in some embodiments.Described multiple InGaN layer comprises at least one and comprises In _wga _1-wat least one of the well layer of N and vicinity at least one well layer described comprises In _bga _1-bthe screen of N, wherein 0.05≤w≤0.25,0.01≤b≤0.10.

Accompanying drawing explanation

Figure 1A is the simplified side view of the semiconductor structure bodies described in disclosure execution mode, and described semiconductor structure bodies comprises and is in one or more InGaN well layer in the active area of semiconductor structure bodies and one or more InGaN barrier layer.

Figure 1B shows the reduced graph of the relative different of conduction level in the energy band diagram of different materials in the different layers of Figure 1A semiconductor structure bodies.

Fig. 2 A is the simplified side view of another semiconductor structure bodies similar to the semiconductor structure bodies of Figure 1A, and this another semiconductor structure bodies also comprises the electron blocking layers be between the active area of semiconductor structure bodies and base layer.

Fig. 2 B is the simplification conduction band diagram of the semiconductor structure bodies of Fig. 2 A.

Fig. 3 A is the simplified side view of another semiconductor structure bodies similar to the semiconductor structure bodies of Figure 1A, and this another semiconductor structure bodies also comprises the strain relief layer be between the active area of semiconductor structure bodies and base layer.

Fig. 3 B is the simplification conduction band diagram of the semiconductor structure bodies of Fig. 3 A.

Fig. 4 A is the simplified side view of another semiconductor structure bodies similar to the semiconductor structure bodies of Figure 1A, and this another semiconductor structure bodies also comprises the thin barrier layer of additional GaN be in the active area of semiconductor structure bodies.

Fig. 4 B is the simplification conduction band diagram of the semiconductor structure bodies of Fig. 4 A.

Fig. 5 A is the simplified side view of another semiconductor structure bodies similar to the semiconductor structure bodies of Figure 1A, and this another semiconductor structure bodies also comprises the trap flow structure body (welloverflowstructure) be in the active area of semiconductor structure bodies.

Fig. 5 B is the simplification conduction band diagram of the semiconductor structure bodies of Fig. 5 A.

Fig. 6 A is the simplification vertical view of intermediate semiconductor structures body that can be used for manufacturing growth templates, and described growth templates is used for manufacturing semiconductor structure bodies according to the execution mode of method of the present disclosure.

Fig. 6 B is the fragmentary sectional side view of the intermediate semiconductor structures body of Fig. 6 A.

Fig. 6 C is the fragmentary sectional side view that can be used for manufacturing according to the execution mode of method of the present disclosure the growth templates of semiconductor structure bodies.

Fig. 6 D shows the growth duplexer of epitaxial deposition on growth templates.

Fig. 7 is the fragmentary sectional side view of the luminescent device manufactured by semiconductor structure bodies according to the execution mode of method of the present disclosure.

Fig. 8 is the fragmentary sectional side view of another luminescent device manufactured by semiconductor structure bodies according to the execution mode of method of the present disclosure.

Fig. 9 illustrates the graph of a relation between the internal quantum of the semiconductor structure bodies formed according to the execution mode of method of the present disclosure and total strain energy.

Figure 10 A is the simplified side view of previous known LED, and described LED comprises and is in InGaN well layer in the active area of this LED and GaN barrier layer.

Figure 10 B is the simplification conduction band diagram of the LED of Figure 10 A.

Figure 11 A shows the figure of the calculating band edge (bandedge) of conduction band and valence band when to apply 0 voltage in the active area of the LED to Figure 10 A, and this calculated value utilizes the computation model of LED to obtain.

Figure 11 B is the figure similar to Figure 11 A, but it illustrates and make the current density of the active area flowing through described LED be 125A/cm owing to applying voltage to the active area of LED ²time conduction band and the calculating band edge of valence band.

Figure 11 C shows the figure of the emitted radiation intensity calculated, and described emitted radiation intensity is the function of the wavelength of each InGaN quantum well layer in the LED of Figure 11 A.

Figure 11 D shows the figure of the Carrier Injection Efficiency calculated, and described Carrier Injection Efficiency is the function to the current density that the active area of the LED of Figure 11 A applies.

Figure 11 E shows the figure of the internal quantum calculated, and described internal quantum is the function to the current density that the active area of the LED of Figure 11 A applies.

Figure 12 A is the simplified side view of LED of the present disclosure, and described LED and Figure 1A is similar and comprise and be in InGaN well layer in the active area of LED and InGaN barrier layer.

Figure 12 B is the simplification conduction band diagram of the LED of Figure 12 A.

Figure 13 A shows the figure of the calculating band edge of conduction band and valence band when to apply 0 voltage in the active area of the LED to Figure 12 A, and this calculated value utilizes the computation model of LED to obtain.

Figure 13 B is the figure similar to Figure 13 A, but it illustrates and make the active area current density flowing through described LED be 125A/cm owing to applying voltage to the active area of LED ²time conduction band and the calculating band edge of valence band.

Figure 13 C shows the figure of the emitted radiation intensity calculated, and described emitted radiation intensity is the function of the wavelength of sound of laughing InGaN quantum well layer in the LED of Figure 13 A.

Figure 13 D shows the figure of the Carrier Injection Efficiency calculated, and described Carrier Injection Efficiency is the function to the current density that the active area of the LED of Figure 13 A applies.

Figure 13 E shows the figure of the internal quantum calculated, and described internal quantum is the function to the current density that the active area of the LED of Figure 13 A applies.

Figure 14 shows the example of the illuminating device comprising LED of the present disclosure.

Embodiment

The diagram presented herein the actual view be not intended to as any specific semi-conducting material, structure or device, and be only used to the idealized expression describing embodiment of the present disclosure.

Figure 1A shows the execution mode of semiconductor structure bodies 100.Semiconductor structure bodies 100 comprises multiple Ill-nitride layer (such as, indium nitride, gallium nitride, nitrogenize Aluminum-aluminum alloy), and the active area 106 comprising base layer 102, p-type contact layer 104 and be arranged between base layer 102 and p-type contact layer 104, active area 106 comprises multiple InGaN layer.In addition, active area 106 comprises at least one InGaN well layer and at least one InGaN barrier layer.In some embodiments, active area 106 can be made up of (but there is alloy) InGaN at least substantially.The p-type contact layer 104 that semiconductor structure bodies 100 also comprises the electronic barrier layer 108 be arranged on active area 106, is arranged at the p-type body layer 110 on electronic barrier layer 108 and is arranged on p-type body layer 110.

Base layer 102 can comprise optional In _nga _1-nn base layer 112, wherein In _nga _1-nthe growth plane of N base layer 112 is polar plane that growth plane lattice parameter is more than or equal to about 3.186 dusts.Luminescent device can be manufactured by semiconductor structure bodies 100 herein, such as light-emitting diode as described in detail subsequently.But, in brief, the first electrode contact (electrodecontact) can be formed in a part for base layer 102, and the second electrode contact can be formed in a part for p-type contact layer 104, thus the voltage crossing active area 106 can be provided between described electrode contact, the luminescent device manufactured by semiconductor structure bodies 100 is made to send electromagnetic radiation (such as, visible ray) thus.

The execution mode including the semiconductor structure bodies in source region (this active area comprises at least one InGaN well layer and at least one InGaN barrier layer) in the disclosure can utilize each class methods growing or otherwise formed Ill-nitride layer (as InGaN) to manufacture.As limiting examples, one or more that can utilize following methods grow or otherwise deposit various Ill-nitride layer: chemical vapour deposition (CVD) (CVD) method, Metalorganic Chemical Vapor Deposition (MOCVD), vapour phase epitaxy (VPE) method, ald (ALD) method, hydride gas-phase epitaxy (HVPE) method, molecular beam epitaxy (MBE) method, ald (ALD) method and chemical beam epitaxy (CBE) etc.

In some embodiments, can use and grow with the one or all disclosed method in Publication about Document or otherwise deposit various Ill-nitride layer: on July 15th, 2010 is with disclosed No. US2010/0176490A1st, the U.S. Patent Application Publication of the names such as Letertre; On May 6th, 2010 is with No. US2010/0109126th, U.S. Patent Application Publication disclosed in Arena name; On August 23rd, 2012 is with No. US2012/0211870th, U.S. Patent Application Publication disclosed in Figuet name; With on September 6th, 2012 with No. US2012/0225539th, U.S. Patent Application Publication disclosed in Figuet name.These class methods can manufacture the Ill-nitride layer of composition and the thickness had hereinafter described, as InGaN layer (with other optional Ill-nitride layer).These class methods can be utilized to form growth templates 113, growth templates 113 can form follow-up Ill-nitride layer.

The example of these class methods of the growth templates 113 as shown in Figure 1A manufacturing embodiment of the present disclosure can be used for by briefly describing.

The semiconductor structure bodies 100 of Figure 1A comprises the multiple Ill-nitride layer be formed on growth templates 113.In some embodiments, the GaN crystal seed layer 656 that growth templates 113 comprises growth substrates 658 and is arranged in growth substrates 658, wherein the growth plane of GaN crystal seed layer comprises polar plane.Growth templates 113 also can comprise the group III-nitride nucleating layer 660 be arranged between growth substrates 658 and GaN crystal seed layer 656.

Growth substrates 658 can comprise homogeneous material or heterogeneous body (that is, compound) material.With limiting examples, growth substrates 658 can comprise sapphire, silicon, III-arsenide, quartz (SiO ₂), fused silica (SiO ₂) glass, glassceramic composites is (such as, by SchottNorthAmerica, Inc., Duryea, PA with trade mark sell those), fused silica glass composite material (such as, SiO ₂-TiO ₂or Cu ₂-Al ₂o ₃-SiO ₂), aluminium nitride (AlN) or carborundum (SiC).In some embodiments, growth substrate comprises c-plane sapphire, and wherein sapphire growth plane 659 comprises c-plane.

Group III-nitride nucleating layer 660 is formed by deposition process known in the art and technique, such as chemical vapour deposition (CVD) (CVD) method, Metalorganic Chemical Vapor Deposition (MOCVD), vapour phase epitaxy (VPE) method, ald (ALD) method, hydride gas-phase epitaxy (HVPE) method, molecular beam epitaxy (MBE) method, ald (ALD) method, chemical beam epitaxy (CBE) method etc.

Group III-nitride nucleating layer 660 can comprise such as aluminium nitride (AlN), indium nitride (InN) or gallium nitride (GaN).Group III-nitride nucleating layer 660 can be formed as having about 100 nanometers (100nm) below, about 20 nanometers (25nm) below or about 10 nanometer (10nm) average layer thickness below.Group III-nitride nucleating layer 660 also can comprise intentional or unintentional alloy.Group III-nitride nucleating layer 660 can be set directly in growth substrates 658 and between growth substrates 658 and GaN crystal seed layer 656.The chemical vapour deposition technique that group III-nitride nucleating layer can such as be undertaken by the depositing temperature below about 700 DEG C is formed.After group III-nitride nucleating layer 660 deposits, can at annealing temperature (that is, heating) the group III-nitride nucleating layer 660 higher than about 700 DEG C to improve the crystallographic property of group III-nitride nucleating layer 660.

GaN crystal seed layer 656 can be arranged in growth substrates 658.The growth plane 662 of GaN crystal seed layer 656 can comprise polar growth (such as, gallium polarity or nitrogen polarity) plane.In some embodiments, the growth plane 662 of GaN crystal seed layer 656 can comprise gallium polar growth plane.In other embodiments, GaN crystal seed layer 656 can such as be formed by deposition process, and GaN crystal seed layer 656 is formed with the state of elongation strain.In other words, can form GaN crystal seed layer 656 makes the crystal lattices at growth plane 662 place substantially mate with the crystal lattices of growth substrates 658.Such as, the lattice constant of the growth plane 662 of GaN crystal seed layer 656 can have the average lattice value equaling about 3.186 dusts.

GaN crystal seed layer 656 is formed by deposition process known in the art and technique, such as chemical vapour deposition (CVD) (CVD) method, Metalorganic Chemical Vapor Deposition (MOCVD), vapour phase epitaxy (VPE) method, ald (ALD) method, hydride gas-phase epitaxy (HVPE) method, molecular beam epitaxy (MBE) method, ald (ALD) method, chemical beam epitaxy (CBE) method etc.Such as, GaN crystal seed layer 656 useful chemical vapour deposition process is formed, and wherein the temperature of deposition process below about 1100 DEG C is carried out.

GaN crystal seed layer 656 can be formed as having scope extends to about 7 microns (7 μm) average layer thickness Ts from about 1 micron (1 μm).As a specific limiting examples, average layer thickness Ts can equal about 4 microns (4 μm).GaN crystal seed layer 656 also can comprise intentional or unintentional alloy.Such as, GaN crystal seed layer 656 carries out n-type doping by element (such as, silicon or the germanium) doping as electron donor.In GaN crystal seed layer 656, the concentration of alloy can be about 3e ¹⁷cm ^-3to about 1e ²⁰cm ^-3, or about 5e ¹⁷cm ^-3to about 4e ¹⁹cm ^-3.The growth rate of GaN crystal seed layer 656 can be about 25 nm/minute (25nm/min) to about 50 nm/minute (50nm/min).

GaN crystal seed layer 656 can be set directly on group III-nitride nucleating layer 660 side relative with growth substrates 658.Therefore, GaN crystal seed layer 656 can be arranged between nucleating layer 660 and active area 106.

In other embodiments, growth templates 113 can have the structure described referring below to Fig. 6 A to 6C, and can utilize and also formed in method described below.

Fig. 6 A is the vertical view of intermediate semiconductor structures body 650 that can be used for being formed (Fig. 6 C) growth templates 113, and described growth templates 113 can manufacture one or more semiconductor structure bodies of the present disclosure and follow-up luminescent device; And Fig. 6 B is the simplification sectional view of a part for the intermediate semiconductor structures body 650 utilized when forming growth templates 113.Growth templates 113 can manufacture as disclosed in No. US2010/0176490A1st, above-mentioned U.S. Patent Application Publication and/or No. US2010/0109126th, U.S. Patent Application Publication.Disclosed in the document, one or more In that intermediate semiconductor structures body 650 can comprise sacrificial substrate 652, be arranged on the conforming materials layer 654 in sacrificial substrate 652 and be arranged on conforming materials 654 _sga _1-sn crystal seed layer 656.One or more In _sga _1-sn crystal seed layer 656 can be used as " crystal seed (seed) ", can form the various succeeding layers of semiconductor structure bodies 100 as herein described thereon.

Initial In _sga _1-sn crystal seed layer can be formed on initial growth substrate, and utilize subsequently such as ion implantation, with initial In _sga _1-sa part of bonding of N crystal seed layer is also separated the methods such as (not shown) subsequently and is transferred to sacrificial substrate 652.Initial growth substrate can comprise the following growth substrates of feature: it has and initial In _sga _1-sthe growth plane lattice of N crystal seed layer mispairing thus make described In _sga _1-sn crystal seed layer is formed with contingency approach.Such as, initial growth substrate can comprise the Sapphire Substrate comprising gallium polar GaN crystal seed layer, thus makes formed In _sga _1-sn crystal seed layer comprises the gallium polar GaN crystal seed layer standing elongation strain.

Can by initial In _sga _1-sn crystal seed layer is formed or is grown to and makes In _sga _1-sn crystal seed layer comprises following growth plane, and this growth plane comprises the polar plane of group III-nitride.Such as, growth plane can be formed as making In _sga _1-sn crystal seed layer comprises gallium polar plane.In addition, can by initial In _sga _1-sn crystal seed layer grows or is otherwise formed as making In _sga _1-sthe composition of N crystal seed layer makes 0.02≤s≤0.05.As a specific limiting examples, In _sga _1-sthe value of the n in N crystal seed layer can equal about 0.03.Can also by In _sga _1-sn crystal seed layer grows or is otherwise formed to thickness and is greater than about 200 nanometers (200nm).But, In _sga _1-sn crystal seed layer is formed as follows: described In _sga _1-sn crystal seed layer is no more than In _sga _1-sn crystal seed layer critical thickness, this critical thickness is In _sga _1-sthickness when strain in N crystal seed layer can relax by forming extra defect.This phenomenon is so-called to be in the art separated.Therefore, In _sga _1-sn crystal seed layer can comprise the high-quality seed crystal material of strain.

Only for example be not construed as limiting, industrial known method SMART-CUT technique can be used to utilize conforming materials layer 654 as bonded layer by In _sga _1-sn crystal seed layer 656 is transferred to sacrificial substrate 652.These class methods are described in detail in the United States Patent (USP) RE39 of such as Bruel, No. 484, the United States Patent (USP) 6 of No. 6,303,468, the United States Patent (USP), Aspar etc. of Aspar etc., 335, No. 258, the United States Patent (USP) 6 of No. 6,756,286, the United States Patent (USP), Aspar etc. of Moriceau etc., 809, No. 6,946,365, the United States Patent (USP) of No. 044 and Aspar etc.

Sacrificial substrate 652 can comprise homogeneous material or heterogeneous body (that is, compound) material.With limiting examples, support that substrate 652 can comprise sapphire, silicon, III-arsenide, quartz (SiO ₂), fused silica (SiO ₂) glass, glassceramic composites is (such as, by SchottNorthAmerica, Inc., Duryea, PA with trade mark sell those), fused silica glass composite material (such as, SiO ₂-TiO ₂or Cu ₂-Al ₂o ₃-SiO ₂), aluminium nitride (AlN) or carborundum (SiC).

Conforming materials layer 654 can comprise such as glass transition temperature (T _g) be less than or equal to the material of about 800 DEG C.The thickness of conforming materials layer 654 can extending to about 10 μm, more particularly in the scope of about 1 μm ~ about 5 μm from about 0.1 μm.With limiting examples, conforming materials layer 100 can comprise at least one in following material: oxide, phosphosilicate glass (PSG), borosilicate (BSG), boron phosphorus silicate glass (BPSG), polyimides, doping or the inorganic siloxanes spin-coating glass of unadulterated standard (spin-on-glass, SOG), inorganic spin-coating glass (that is, methyl-, ethyl-, phenyl-or butyl-) and doping or unadulterated silicate.

Conforming materials layer 654 can utilize such as baking oven, smelting furnace or deposition reactor to be heated to be enough to the viscosity of conforming materials layer 654 is reduced with the temperature making conforming materials layer 654 flow again, thus makes one or more In _sga _1-sn crystal seed layer 656 makes crystal lattices strain relaxation at least in part.By reducing the viscosity of conforming materials layer 654, In _sga _1-selongation strain in N crystal seed layer 656 can be relaxed at least in part, even may disappear, and forms the In that growth plane lattice parameter is more than or equal to about 3.189 dusts thus _sga _1-sn crystal seed layer 656.

Therefore, by making In _sga _1-sbeing relaxed at least partially of crystal lattice stress in N, at In _sga _1-sthe growth plane lattice parameter being more than or equal to about 3.189 dusts can be obtained in N.The growth plane lattice parameter being more than or equal to about 3.189 dusts can correspond to the balanced growth in-plane lattice constant of buergerite GaN.Therefore, according to some execution mode of the present disclosure, at In of the present disclosure _sga _1-sabove N layer or on formed one or more GaN layer can with without strain regime formation, namely substantially there is no crystal lattice stress.

At one or more In _sga _1-safter N crystal seed layer 656 relaxes at least partly, can by In _sga _1-sn crystal seed layer 656 is transferred to support substrate, and conforming materials 654 and sacrificial substrate 652 can be removed the growth templates 113 that formed shown in Fig. 6 C subsequently.More specifically, and with reference to Fig. 6 B and Fig. 6 C, In lax at least partly can be made _sga _1-sn crystal seed layer 656 be attached to support substrate 659, and can utilize in such as laser lift-off, Wet-type etching, dry-etching and chemico-mechanical polishing one or more etc. method sacrificial substrate 652 and conforming materials 654 are removed.

Support that substrate 659 can comprise homogeneous material or heterogeneous body (that is, compound) material.With limiting examples, support that substrate 658 can comprise sapphire, silicon, III-arsenide, quartz (SiO ₂), fused silica (SiO ₂) glass, glassceramic composites is (such as, by SchottNorthAmerica, Inc., Duryea, PA with trade mark sell those), fused silica glass composite material (such as, SiO ₂-TiO ₂or Cu ₂-Al ₂o ₃-SiO ₂), aluminium nitride (AlN) or carborundum (SiC).

As shown in Figure 6 C, in some embodiments, growth templates 113 can comprise alternatively by the dielectric materials layer 661 overlayed on support substrate 659.Dielectric materials layer 661 can be formed at the first type surface or one or more In of supporting substrate 659 alternatively _sga _1-son N crystal seed layer 656, its dielectric material 661 is used as auxiliary In _sga _1-sn crystal seed layer 656 is bonded to the bonded layer supporting substrate 659.Dielectric materials layer 661 can comprise such as silicon oxynitride (SiON), silicon nitride (Si ₃n ₄) or silicon dioxide (SiO ₂), and such as chemical vapour deposition (CVD) (CVD), physical vapour deposition (PVD) (PVD) or ald (ALD) can be utilized to be formed.Therefore, as Fig. 6 C, growth templates 113 comprises to be supported substrate 659 and is arranged on the In supported on substrate 659 _sga _1-sn crystal seed layer 656.

In addition, In _sga _1-sn crystal seed layer 656 can be formed in be supported on substrate 659, and makes In _sga _1-sthe composition of N crystal seed layer 656 can in the scope of 0.02≤s≤0.05.As a specific limiting examples, In _sga _1-sthe value of the s in N crystal seed layer 656 can equal about 0.03.And, In _sga _1-sn crystal seed layer 656 can have the polar growth plane 662 that growth plane lattice parameter is greater than about 3.2 dusts.In _sga _1-sn crystal seed layer can also be formed as making total thickness T _sbe greater than about 100 nanometers (100nm).

As described above, growth templates 113 can form a part for the base layer 102 of Figure 1A, and can comprise growth templates 658, group III-nitride nucleating layer 660 and GaN crystal seed layer 656.In some embodiments, base layer 102 can also comprise optional In _nga _1-nn base layer 112, wherein said In _nga _1-nn base layer inherits some crystalline nature of adjacent GaN crystal seed layer.Therefore, In _nga _1-nn base layer 112 can also comprise the polar growth plane (such as, gallium polar growth plane) that growth plane lattice parameter is more than or equal to about 3.186 dusts.

In _nga _1-nn base layer 112 can comprise In _nga _1-nn layer, wherein 0.00≤n≤0.10, or wherein 0.02≤n≤0.08.As a specific non-limiting example execution mode, In _nga _1-nthe value of the n in N base layer 112 can equal about 0.05.In _nga _1-nthe average thickness T of N base layer 112 _ncan be about 10 nanometer (10nm) ~ about 3000 nanometers (3,000nm), or be about 10 nanometer (10nm) ~ about 1000 nanometers (1,000nm).Alternatively, In _nga _1-nn base layer 112 can adulterate.Such as, In _nga _1-nn base layer 112 can carry out n-type doping by element (such as, silicon or the germanium) doping being used as electron donor.Such as, In _nga _1-nin N base layer 112, the concentration of alloy can be about 3e ¹⁷cm ^-3~ about 1e ²⁰cm ^-3, or about 5e ¹⁷cm ^-3~ about 1e ¹⁹cm ^-3.

Formation comprise other various layers one or more of the semiconductor structure bodies 100 of InGaN after, can base layer 102 at least partially on form the first electrode contact to manufacture luminescent device by semiconductor structure bodies 100.

The base layer 102 completed as described in Figure 1A comprises growth templates 113 as described above and optional In _nga _1-nn base layer 112.The layer-by-layer methods that can describe in further detail below with this paper grows or otherwise forms the various Ill-nitride layer of semiconductor structure bodies 100.In some embodiments, base layer 102 can comprise the matrix of other layer of the semiconductor structure bodies 100 that it can grow or otherwise formed.Therefore, the various Ill-nitride layer of semiconductor structure bodies 100 direction from left to right can be passed and grow successively or otherwise formed from base layer 102 and along the visual angle by Figure 1A, but in fact described structure can be positioned as base layer 102 is arranged on bottom in the fabrication process.In other words, structure can turn 90 degrees location with the location of Figure 1A in the fabrication process counterclockwise.

As hereafter discussed in detail further, active area 106 is arranged between base layer 102 and p-type contact layer 104.Active area 106 comprises at least one InGaN well layer 114 and at least one InGaN barrier layer 116.In some embodiments, active area 106 can be made up of (but there is alloy) InGaN at least substantially, and the indium content of InGaN well layer 114 is strictly greater than the indium content of InGaN barrier layer 116.Especially, active area 106 can comprise at least one well layer 114, and this well layer 114 comprises In _wga _1-wn, wherein 0.10≤w≤0.40, or in some embodiments, wherein 0.12≤w≤0.25, or in other embodiments, wherein w equals about 0.14.Active area 106 also comprises at least one barrier layer 116, and this barrier layer 116 comprises In _bga _1-bn, wherein b<w and wherein 0.01≤b≤0.10, or in some embodiments, wherein 0.03≤b≤0.08, or in other embodiments, wherein b equals about 0.05.In some embodiments, InGaN barrier layer 116 can be close to (such as, being directly adjacent to) at least one InGaN well layer 114 described.

The active area 106 of semiconductor structure bodies be semiconductor structure bodies as lower area: when semiconductor structure bodies being fabricated to as luminescent devices such as light-emitting diodes (LED), electronics in this region and hole each other compound produce photon, and described photon is launched from LED.In some embodiments, photon is launched with the form of visible ray.Visible ray can have the one or more wavelength extended to from about 380 nanometers (380nm) within the scope of the electromagnetic radiation spectrum of about 560 nanometers (560nm) at least partially.

As mentioned before, the active area 106 of semiconductor structure bodies 100 comprises one or more InGaN well layer 114 and one or more InGaN barrier layer 116, and is at least substantially in some embodiments made up of (but there is alloy) InGaN.Therefore, in some embodiments, active area 106 can be made up of InGaN in fact.Active area 106 comprises one or more pairs of adjacent layer, and described adjacent layer comprises a well layer 114 and a barrier layer 116, and wherein each well layer 114 comprises In _wga _1-wn, wherein 0.10≤w≤0.40, and wherein each barrier layer 116 comprises In _bga _1-bn, wherein 0.01≤b≤0.10 and b<w.

In the execution mode shown in Figure 1A and 1B, the active area 106 of semiconductor structure bodies 100 comprises one (1) to active layer (well layer 114 and barrier layer 116), but in other execution mode, the active area 106 of semiconductor structure bodies 100 can comprise more than a pair active layer.Such as, the active area 106 of semiconductor structure bodies 100 can comprise one (1) to 25 (25) to adjacent active layer, often pair comprises well layer 114 and barrier layer 116, and active area 106 comprises the duplexer (comprising in the execution mode more than a pair) of well layer 114 alternately and barrier layer 116 thus.It should be understood, however, that the number of barrier layer 116 can be unequal with the number of well layer 114.Well layer 114 can be separate with barrier layer 116.Therefore, in some embodiments, the number of barrier layer 116 can equal the number of well layer, or more than it 1, or fewer than it 1.

Still with reference to Figure 1A, the average thickness T of each well layer 114 _wcan be about 1 nanometer (1nm) ~ about 1000 nanometer (1,000nm), about 1 nanometer (1nm) ~ about 100 nanometer (100nm) or about 1 nanometer (1nm) ~ about 10 nanometer (10nm).In some embodiments, well layer 114 can comprise quantum well.In these embodiments, the average thickness T of each well layer 114 _wcan be about 10 nanometers (10nm) below.In other embodiments, well layer 114 can not comprise quantum well, and the average thickness T of each well layer 114 _wabout 10 nanometers (10nm) can be greater than.In these embodiments, active area 106 can comprise the structure being called " double-heterostructure " in the art.The average thickness T of each barrier layer 116 _bcan be about 1 nanometer (1nm) ~ about 50 nanometer (100nm) or about 1 nanometer (1nm) ~ about 10 nanometer (10nm), but barrier layer 116 may be thicker in other embodiments.

One in well layer 114 and barrier layer 116 or both can adulterate.Such as, n-type doping can be carried out by element (such as, silicon or the germanium) doping being used as electron donor to the one in well layer 114 and barrier layer 116 or both.In some embodiments, the concentration of dopant in well layer 114 can be about 3e ¹⁷cm ^-3~ about 1e ¹⁹cm ^-3, can be maybe about 3e ¹⁷cm ^-3~ about 5e ¹⁷cm ^-3.Similarly, the concentration of dopant in barrier layer 116 can be about 3e ¹⁷cm ^-3~ about 1e ¹⁹cm ^-3, or can be about 1e ¹⁸cm ^-3~ about 3e ¹⁸cm ^-3.

One in well layer 114 and barrier layer 116 or both can have wurtzite crystal structure.In addition, in some embodiments, one in well layer 114 and barrier layer 116 or both can comprise polar growth surface (such as gallium polar growth surface), its average lattice constant in the growth plane parallel with the one or more interfaces between well layer 114 and barrier layer 116 is more than or equal to about 3.186 dusts.More specifically, in some embodiments, average production in-plane lattice constant c can be about 3.186 dusts ~ about 3.2 dusts.

The average total thickness comprising the active area 106 of at least one well layer and at least one barrier layer can in the scope of about 40 nanometer (40nm) ~ about 1000 nanometers (1,000nm), in the scope of about 40 nanometer (40nm) ~ about 750 nanometers (750nm) or in the scope of about 40 nanometer (40nm) ~ about 200 nanometers (200nm).

Still with reference to Figure 1A, semiconductor structure bodies 100 can comprise alternatively and is between active area 106 and p-type contact layer 104 and/or the extra play be between active area 106 and base layer 102.Such as, in some embodiments, semiconductor structure bodies 100 can comprise the wall 118 be between active area 106 and base layer 102.

Optional wall 118 can comprise In _spga _1-spn layer, wherein 0.01≤sp≤0.10, or wherein 0.03≤sp≤0.06, or wherein sp equals about 0.05.Wall 118 may be used for providing milder transition between base layer 102 and the layer of active area 106, and it is relative to base layer 102 and in some embodiments relative to In _nga _1-nn basalis 112 may have different compositions (and thus having different lattice parameters).Therefore, in some embodiments, In _spga _1-spn wall 118 can be set directly between base layer 102 and active area 106.By providing milder transition between base layer 102 and active area 106, the stress in the crystal lattices of each InGaN layer may reduce, and the defect that therefore may cause because of described stress also may reduce.In _spga _1-spthe average thickness T of N wall 118 _spcan be about 1 nanometer (1nm) ~ about 100 nanometer (100nm) or about 1 nanometer (1nm) ~ about 25 nanometer (25nm).As a specific limiting examples, average thickness T _spabout 10 nanometers (10nm) can be equaled.

Alternatively, In _spga _1-spn wall 118 can adulterate.Such as, can be come In by element (such as, silicon or the germanium) doping being used as electron donor _spga _1-spn wall 118 carries out n-type doping.Concentration of dopant in wall 118 can be about 3e ¹⁷cm ^-3~ about 1e ¹⁹cm ^-3.As a specific limiting examples, the concentration of dopant in wall 118 can equal about 2e ¹⁸cm ^-3.

Still with reference to Figure 1A, semiconductor structure bodies 100 can also comprise the optional In be arranged between active area 106 and p-type contact layer 104 _cpga _1-cpn end-blocking layer 120.Optional In _cpga _1-cpn end-blocking layer 120 can comprise In _cpga _1-cpn layer, wherein 0.01≤cp≤0.10, or wherein 0.03≤cp≤0.07.As a specific limiting examples, the value of cp can equal about 0.05.In _cpga _1-cpn end-blocking layer 120 may be used for avoiding the indium processed in the layer of the active area 106 covered at present at subsequent high temperature to dissolve and/or evaporation, and/or can play the function identical with wall.

In _cpga _1-cpthe average thickness T of N end-blocking layer 120 _cpcan be about 1 nanometer (1nm) ~ about 100 nanometer (100nm) or about 1 nanometer (1nm) ~ about 25 nanometer (25nm).As specific limiting examples, in some embodiments a T _cpabout 10 nanometers (10nm) can be equaled.Alternatively, end-blocking layer 120 can adulterate.Such as, the doping of p-type can be carried out by element (such as, magnesium, zinc or the carbon) doping being used as electron acceptor to end-blocking layer 120.But, in other embodiments, n-type doping can be carried out to end-blocking layer 120.Concentration of dopant in end-blocking layer 120 can be about 3e ¹⁷cm ^-3~ about 1e ¹⁹cm ^-3can be maybe about 1e ¹⁸cm ^-3~ about 5e ¹⁸cm ^-3.As a specific limiting examples, the concentration of dopant in some embodiments in end-blocking layer 120 can equal about 2e ¹⁸cm ^-3.

Semiconductor structure bodies 100 of the present disclosure can also comprise the one or more electronic barrier layers (EBL) be arranged between active area 106 and p-type contact layer 104.This type of electronic barrier layer can comprise the energy level of the band edge of the wherein conduction band material relatively high relative to the band edge of conduction band in active area 106, and it can play and to be limited in by electronics in active area 106 and to avoid the effect of charge carrier outside overflow from active area 106.

As limiting examples, Figure 1A shows the electronic barrier layer 108 being arranged on end-blocking layer 120 side relative with active area 106.In the execution mode comprising p-type body layer 110, as shown in Figure 1A, electronic barrier layer 108 can be set directly between end-blocking layer 120 and p-type body layer 110.

Electronic barrier layer 108 comprises group III-nitride.As limiting examples, electronic barrier layer 108 can be at least basic by In _ega _1-en forms (but there is alloy), wherein 0.00≤e≤0.02, and can at least substantially be made up of (but there is alloy) GaN in some embodiments.In other embodiments, electronic barrier layer 108 can be at least basic by Al _ega _1-en forms, wherein 0.00≤e≤0.20.In some embodiments, electronic barrier layer 108 can be at least basic by Al _ega _1-en forms (but there is alloy).

Electronic barrier layer 108 can carry out the doping of p-type with one or more alloys being selected from the group be made up of magnesium, zinc and carbon.The concentration of one or more alloys in electronic barrier layer 108 can be in from about 1e ¹⁷cm ^-3extend to about 1e ²¹cm ^-3scope, or about 3e can be equaled in some embodiments ¹⁹cm ^-3.In some embodiments, the average thickness T of electronic barrier layer 108 _ethe scope extending to about 50 nanometers (50nm) from about 5 nanometers (5nm) can be in, or in some embodiments, its average thickness T _eabout 20 nanometers (20nm) can be equaled.

In other execution mode of semiconductor structure bodies 100 of the present disclosure, semiconductor structure bodies 100 can have the electronic barrier layer similar to electronic barrier layer 108, but wherein said electronic barrier layer has the superlattice structure comprising different material layer alternately, as shown in the insertion Figure 122 in Figure 1A.Such as, electronic barrier layer 108 can have the GaN layer 124 and In that comprise and replace _ega _1-ethe superlattice structure of N layer 126, wherein 0.01≤e≤0.02.In other embodiments, electronic barrier layer can have the GaN layer 124 and Al that comprise and replace _ega _1-ethe superlattice structure of N layer 126, wherein 0.01≤e≤0.20.The average thickness of each layer in this type of superlattice structure all can be about 1 nanometer (1nm) ~ about 20 nanometer (20nm).

As mentioned before, semiconductor structure bodies 100 of the present disclosure also can comprise the p-type body layer 110 be arranged between electronic barrier layer 108 and p-type contact layer 104.This type of p-type body layer can comprise the III-nitride material of p-doping, the In of such as p-doping _pga _1-pn.This type of p-type body layer can as the source of such as holoe carrier and for strengthening the electrical conductivity and light extraction that enter and leave active area 106.For carrier flow reason, it is helpful for adding indium at p-type body layer 110, contributes to carrier confinement in active area.

P-type body layer 110 can be at least basic by In _pga _1-pn forms (but there is alloy), wherein 0≤p≤0.08, and preferred wherein 0.01≤p≤0.08.In a specific limiting examples, p-type body layer 110 can be at least basic by In _pga _1-pn forms, and wherein p equals about 0.02.P-type body layer 110 can carry out the doping of p-type with one or more alloys being selected from the group be made up of magnesium, zinc and carbon.The concentration of one or more alloys in p-type body layer 110 can be in from about 1e ¹⁷cm ^-3extend to about 1e ²¹cm ^-3scope.As a specific limiting examples, the concentration of the alloy in p-type body layer 110 can equal about 3e ¹⁹cm ^-3.In some embodiments, the average thickness T of p-type body layer 110 _pthe scope extending to about 600 nanometers (600nm) from about 50 nanometers (50nm) can be in.As a specific limiting examples, the average thickness T of p-type body layer 110 _pabout 175 nanometers (175nm) can be equaled.

Semiconductor structure bodies 100 can also comprise the p-type contact layer 104 being arranged on p-type body layer 110 side relative with electronic barrier layer 108.P-type contact layer 104 can comprise III group nitride.This type of p-type contact layer can be used for such as strengthening hole to the conduction in active area 106.P-type contact layer 104 can comprise one or more alloys of higher concentration (such as, p-type alloy), thus the resistance of the electrode contact formed in a part for p-type contact layer in the process being manufactured luminescent device by semiconductor structure bodies 100 is limited.

As limiting examples, p-type contact layer 104 can comprise the In through the doping of p-type _cga _1-cn.Such as, p-type contact layer 104 can be at least basic by In _cga _1-cn forms, and wherein 0.01≤c≤0.10 (but there is alloy), and in some embodiments, p-type contact layer 104 can be made up of (but there is alloy) GaN at least substantially.In p-type contact layer 104, add indium is helpful, and reason is that it can reduce with the energy barrier of the metal electrode be formed on device thus obtain lower device operating voltages.P-type contact layer 104 can carry out the doping of p-type with one or more alloys being selected from the group be made up of magnesium, zinc and carbon.The concentration of one or more alloys in p-type contact layer 104 can be in from about 1e ¹⁷cm ^-3extend to about 1e ²¹cm ^-3scope.As a specific limiting examples, the concentration of one or more alloys in p-type contact layer 104 can equal about 1e ²⁰cm ^-3.The average thickness T of p-type contact layer 104 _cthe scope extending to about 50 nanometers (50nm) from about 2 nanometers (2nm) can be in.As a specific limiting examples, the average thickness T of p-type contact layer 104 _cabout 15 nanometers (15nm) can be equaled.As shown in Figure 1A, p-type contact layer 104 can directly be formed on p-type body layer 110.

As described in more detail below, the semiconductor structure bodies 100 completed may be used in the manufacture of one or more light emitting semiconductor devices (as LED).In brief, can in a part for the semiconductor layer of base layer 102 (such as, In _nga _1-nin a part for N base layer 112 or the going up at least partially of GaN crystal seed layer 656) form electrode contact, and can p-type contact layer 104 at least partially on form another electrode contact, enable electric charge carrier be injected with in source region 106 thus and produce electromagnetic radiation (it can be the form of visible ray).

Figure 1B shows the reduced graph (note, eliminate growth substrates 658 and group III-nitride nucleating layer 660) of the energy level relative different of (in energy band diagram) conduction band 128 of different semi-conducting material in the various layers of the semiconductor structure bodies 100 of Figure 1A.Semiconductor structure bodies 100 vertical alignment of Figure 1B and Figure 1A.Vertical dotted line in Figure 1B is alignd with the interface between each layer in the semiconductor structure bodies 100 of Figure 1A.The longitudinal axis in Figure 1B is energy, and higher energy level is vertically positioned on lower energy level.It should be noted, Figure 1B shows the limiting examples of the conduction level of exemplary semiconductor structure body 100.Therefore, relative level conduction level may at least as the composition of individual semiconductor layer and the compositing range of doping and each semiconductor layer as described above function and change to some extent on relative position.Therefore, Figure 1B can be used for the relative different of energy level of the conduction band 128 checked in each layer of semiconductor structure bodies 100.As shown in Figure 1B, the energy level of the conduction band 128 in well layer 114 may lower than the energy level of the conduction band 128 in other layer of semiconductor structure bodies 100.

As known in the art, for the such as group III-nitride such as InGaN, the energy level of conduction band 128 is the functions of the multiple variablees including but not limited to indium content and dopant levels.Well layer 114 and barrier layer 116 can be formed as the energy level of energy level lower than the conduction band 128 in barrier layer 116 having certain composition or be otherwise configured the conduction band 128 made in well layer 114.Therefore, at the duration of work of the luminescent device manufactured by semiconductor structure bodies 100, electric charge carrier (such as, electronics) may be accumulated in well layer 114, and barrier layer 116 may play the effect hindering electric charge carrier (such as, electronics) to move across active area 106.Therefore, in some embodiments, the indium content in each well layer 114 may higher than the indium content in each barrier layer 116.Such as, (namely indium content in each well layer 114 and the difference between the indium content in each barrier layer 116 may be more than or equal to about 0.05, w-b >=0.05), or about 0.20 (that is, w-b >=0.20) may be more than or equal in some embodiments.In some embodiments, the concentration of dopant in barrier layer 116 may be different from the concentration of dopant in well layer 114.High-dopant concentration may cause the defect in InGaN crystal structure, and this kind of defect may cause the non-radiation type of electron-hole pair to combine.In some embodiments, concentration of dopant in well layer 114 may lower than the concentration of dopant in barrier layer 116, and the speed that the speed combined to make the non-radiation type of the electron-hole pair in well layer 114 combines relative to the non-radiation type of the electron-hole pair in barrier layer 116 reduces.In other embodiments, the concentration of dopant in barrier layer 116 may higher than the concentration of dopant in well layer 114.

As shown in Figure 1B, the energy barrier that electronic barrier layer 108 provides may be produced by the energy level difference of the conduction band 128 in electronic barrier layer 108 and end-blocking layer 120 (or at electronic barrier layer 108 other layer near side next-door neighbour's electronic barrier layer 108 of active area 106).The height of energy barrier can change by changing the composition of electronic barrier layer 108.Such as, as shown in Figure 1B, conduction level 130 (with solid line display) can illustrate at least basic conduction level being made up of the electronic barrier layer of (but there is alloy) GaN.At least basic by In by being formed _ega _1-ethe electronic barrier layer of N composition (wherein 0.01≤e≤0.02), is illustrated that by conduction level 132 conduction level in the electronic barrier layer of (showing with dotted line) can reduce relative to GaN electronic barrier layer.In other embodiments, at least basic by Al by being formed _ega _1-eby conduction level 134, the electronic barrier layer of N composition (wherein 0.01≤e≤0.20), illustrates that the conduction level of (showing with dotted line) can increase relative to GaN electronic barrier layer.Therefore, the conduction level in electronic barrier layer can be changed, to provide required conduction band offset between electronic barrier layer 108 and other Ill-nitride layer of semiconductor structure bodies 100.

Have at electronic barrier layer 108 in the execution mode of the semiconductor structure bodies 100 of the superlattice structure comprising different material layer alternately, conduction level can increase in the quasi-periodic mode of class or reduce, as shown in insertion Figure 136 of Figure 1B.Such as, electronic barrier layer 108 can have the GaN layer 138 and Al that comprise and replace _ega _1-ethe superlattice structure of N layer 140, wherein 0.01≤e≤0.20, or alternately, superlattice structure can comprise GaN layer alternately and In _ega _1-en layer, wherein 0.01≤e≤0.02.The amplitude that conduction band between different material layer alternately can offset can by GaN layer and Al _ega _1-en layer or In _ega _1-ecomposition difference between N layer and selecting.

Semiconductor structure bodies of the present disclosure can also comprise the electron blocking layers be arranged between the active area 106 of described semiconductor structure bodies and the base layer 102 of semiconductor structure bodies.This kind of electron blocking layers can comprise the III-nitride material of n-doping, the energy level of the band edge of conduction band and In in described material _nga _1-nthe band edge of the conduction band in N base layer is compared relatively higher, and this plays and electronics is limited in the effect in active area further and charge carrier can be avoided from active area overflow, provides the charge carrier homogeneity of improvement thus in active area.

As limiting examples, Fig. 2 A and 2B shows the execution mode of the semiconductor structure bodies 200 comprising this type of electron blocking layers 202.Semiconductor structure bodies 200 is similar to semiconductor structure bodies 100 and include source region 106, and this active area 106 comprises as above about the one or more InGaN well layer 114 described by semiconductor structure bodies 100 and one or more InGaN barrier layer 116.Semiconductor structure bodies 200 also comprises as above about the base layer 102 described by semiconductor structure bodies 100, wall 118, end-blocking layer 120, electronic barrier layer 108, p-type body layer 110 and p-type contact layer 104.The electron blocking layers 202 of semiconductor structure bodies 200 is arranged between basalis 102 and active area 106, and can be arranged on In _nga _1-nbetween N base layer 112 and wall 118.

Electron blocking layers 202 comprises group III-nitride.As limiting examples, electron blocking layers 202 can comprise the AlGaN through n-type doping.Such as, in some embodiments, electron blocking layers 202 can be at least basic by Al _stga _1-stn forms (but there is alloy), wherein 0.01≤st≤0.20.In other embodiments, electron blocking layers 202 can have as inserted the superlattice structure shown in Figure 20 4, and it comprises Al alternately _stga _1-stn layer 206 (wherein, 0.01≤st≤0.20) and GaN layer 208.Semiconductor structure bodies 200 can comprise the Al replaced of arbitrary number (such as, about one (1) to about 20 (20)) _stga _1-stn layer 206 and GaN layer 208.Layer 206 in this type of superlattice structure and the average thickness of layer 208 can be about 1 nanometer (1nm) ~ about 100 nanometer (100nm).

Electron blocking layers 202 can carry out n-type doping with one or more alloys being selected from the group be made up of silicon and germanium.The concentration of one or more alloys in electron blocking layers 202 can be in from about 0.1e ¹⁸cm ^-3extend to 20e ¹⁸cm ^-3scope.In some embodiments, the average thickness T of electron blocking layers 202 _stthe scope of about 50 nanometers (50nm) can be extended to from about 1 nanometer (1nm).

Fig. 2 B is the conduction band diagram simplified, and shows the relative energy-level of the conduction band 228 of various material in semiconductor structure bodies 200.As shown in Figure 2 B, in the execution mode of the semiconductor structure bodies 200 of Fig. 2 A, the energy level (Fig. 2 B) of the conduction band 228 interior at least partially of the electron blocking layers 202 of semiconductor structure bodies 200 may compare In _nga _1-nthe energy level of the conduction band 228 in the energy level of the conduction band 200 in N base layer 112 and/or wall 118 is relatively higher.(it comprises Al alternately to comprise superlattice structure as shown in insertion Figure 21 0 of Fig. 2 B at electron blocking layers 202 _stga _1-stn layer 206 and GaN layer 208, wherein 0.01≤st≤0.20) execution mode in, conduction level can change in a periodic manner.

In other execution mode, semiconductor structure bodies of the present disclosure can comprise be between active area and base layer 102 with helping manufacture one or more material layers of semiconductor structure bodies.Such as, in some embodiments, one or more luminescent devices of semiconductor structure bodies of the present disclosure and the thus manufacture of class formation body can comprise the strain relief layer be arranged between active area and 102 base layers, wherein said strain relief layer is configured and is configured to the strain in the crystal lattices of each layer crystal body structure of the semiconductor structure bodies regulated between base layer 102 and p-type contact layer, and these layers can superpose epitaxial growth mutually with layer-by-layer methods.

As limiting examples, Fig. 3 A and 3B shows the execution mode of the semiconductor structure bodies 300 comprising this type of strain relief layer 302.Semiconductor structure bodies 300 is similar to semiconductor structure bodies 100 and include source region 106, and this active area 106 comprises as above about the one or more InGaN well layer 114 described by semiconductor structure bodies 100 and one or more InGaN barrier layer 116.Semiconductor structure bodies 300 also comprises as above about the base layer 102 described by semiconductor structure bodies 100, wall 118, end-blocking layer 120, electronic barrier layer 108, p-type body layer 110 and p-type contact layer 104.The strain relief layer 302 of semiconductor structure bodies 300 is arranged between base layer 102 and wall 118.In the execution mode of Fig. 3 A and Fig. 3 B, strain relief layer 302 is set directly at In _nga _1-nn base layer 112 and In _spga _1-spbetween N wall 118.

Strain relief layer 302 can comprise group III-nitride.As limiting examples, strain relief layer 302 can have as inserted the superlattice structure shown in Figure 30 4, and it comprises In alternately _sraga _1-sran layer 306 (wherein, 0.01≤sra≤0.10) and In _srbga _1-srbn layer 308 (wherein, 0.01≤srb≤0.10).In addition, sra can be greater than srb.Semiconductor structure bodies 300 can comprise the In replaced of arbitrary number (such as, about one (1) to about 20 (20)) _sraga _1-sran layer 306 and In _srbga _1-srbn layer 308.Layer 306 in this type of superlattice structure and the average thickness of layer 308 can be about 1 nanometer (1nm) ~ about 20 nanometer (20nm).

Strain relief 302 can carry out n-type doping with one or more alloys being selected from the group be made up of silicon and germanium.The concentration of one or more alloys in strain relief 302 can be in from about 0.1e ¹⁸cm ^-3extend to 20e ¹⁸cm ^-3scope.In some embodiments, the average thickness of strain relief layer 302 can be in the scope extending to about 50 nanometers (50nm) from about 1 nanometer (1nm).

Fig. 3 B is the conduction band diagram simplified, and shows the relative energy-level of the conduction band 328 of various material in semiconductor structure bodies 300.As shown in Figure 3 B, in the execution mode of the semiconductor structure bodies 300 of Fig. 3 A, the energy level of the conduction band 328 interior at least partially of the strain relief layer 302 of semiconductor structure bodies 300 (Fig. 3 A) compares In _nga _1-nthe energy level of the conduction band 328 in the energy level of the conduction band 328 in N base layer 112 and/or wall 118 is relatively lower.In other embodiments, the energy level of the conduction band 328 interior at least partially of the strain relief layer 302 of semiconductor structure bodies 300 (Fig. 3 A) compares In _nga _1-nthe energy level of the conduction band 328 in the energy level of the conduction band 328 in N base layer 112 and/or wall 118 is relatively higher.(it comprises In alternately to comprise superlattice structure as shown in insertion Figure 31 0 of Fig. 3 B at strain relief layer 302 _sraga _1-sran layer 306 and In _srbga _1-srbn layer 308) execution mode in, conduction level can change in a periodic manner.

Fig. 4 A and 4B shows the semiconductor structure bodies 400 of the another execution mode of the disclosure.Semiconductor structure bodies 400 is similar to semiconductor structure bodies 100, and includes source region 406, and this active area 406 comprises as above about the one or more InGaN well layer 114 described by semiconductor structure bodies 100 and one or more InGaN barrier layer 116.Semiconductor structure bodies 400 also comprises as above about the base layer 102 described by semiconductor structure bodies 100, wall 118, end-blocking layer 120, electronic barrier layer 108, p-type body layer 110 and p-type contact layer 104.The active area 406 of semiconductor structure bodies 400 also comprises extra GaN barrier layer 402.Extra GaN barrier layer 402 can be arranged between InGaN well layer 114 and InGaN barrier layer 116 separately.Described extra GaN barrier layer 402 can play the effect be limited in further by electronics in well layer 114, and electronics will more may make the possibility of emitted radiation increase with hole-recombination in well layer 114.

In some embodiments, each GaN barrier layer 402 can carry out n-type doping with one or more alloys being selected from the group be made up of silicon and germanium.Such as, the concentration of one or more alloys in GaN barrier layer 402 can be in from about 1.0e ¹⁷cm ^-3extend to 50e ¹⁷cm ^-3scope.In some embodiments, the average thickness T of each GaN barrier layer 402 _b2the scope extending to about 20 nanometers (20nm) from about 1/2 nanometer (0.5nm) can be in.

Fig. 4 B is the conduction band diagram simplified, and shows the relative energy-level of the conduction band 428 of various material in semiconductor structure bodies 400.As shown in Figure 4 B, in the execution mode of the semiconductor structure bodies 400 of Fig. 4 A, the energy level of the conduction band 428 in GaN barrier layer 402 (Fig. 4 A) may be relatively higher than the energy level of the conduction band 428 in InGaN barrier layer 116, and higher than the energy level of the conduction band 428 in InGaN well layer 114.

Fig. 5 A and 5B shows another execution mode of the present disclosure comprising semiconductor structure bodies 500.In these embodiments, can utilize the U.S. Patent Application No. 13/362 submitted on January 31st, 2012 with the name of Arena etc., method disclosed in 866 is formed with source region 506.Semiconductor structure bodies 500 is similar to semiconductor structure bodies 100, and includes source region 506, and this active area 506 comprises as above about the one or more InGaN well layer 514 described by semiconductor structure bodies 100 and one or more InGaN barrier layer 516.Semiconductor structure bodies 500 also comprises as above about the base layer described by semiconductor structure bodies 100, wall, end-blocking layer, electronic barrier layer, p-type body layer and p-type contact layer.For clarity sake, illustrate only the layer around active area 506, and these layers can comprise optional wall 118 and end-blocking layer 120 and In _nga _1-nn base layer 112 and electronic barrier layer 108.If omitted from semiconductor structure bodies 500 by described optional layer, then active area 506 can directly be arranged between base layer 102 and electronic barrier layer 108.

The active area 506 of semiconductor structure bodies 500 is similar to the active area of semiconductor structure bodies 100, but also comprise plural InGaN barrier layer, time wherein to check from right to left in Fig. 5 A and Fig. 5 B (, the direction of wall 118 is extended to from end-blocking layer 120), the band-gap energy between follow-up barrier layer increases in a stepped fashion.In semiconductor structure bodies 500, this configuration of active area 506 by avoiding charge carrier outside overflow and auxiliary be limited in active area 506 by electric charge carrier from active area 506, can improve the efficiency of the luminescent device manufactured by semiconductor structure bodies 500 thus.

Barrier region 516 _a-Cfollowing material the Nomenclature Composition and Structure of Complexes configuration can be had: it is selected as each blind zone 516 _a-Ccorresponding band-gap energy 550 is provided _a-C, wherein said band-gap energy is provided by the conduction band energy 528 of various semi-conducting materials and the energy difference of valence band energy 552 forming semiconductor structure bodies 500.First barrier region 516 _ain band-gap energy 550 _athe second barrier region 516 can be less than _bin band-gap energy 550 _b, and the second barrier region 516 _bin band-gap energy 550 _bthe 3rd barrier region 516 can be less than _cin band-gap energy 550 _c, as shown in the energy band diagram of Fig. 5 B.In addition, quantum well region 552 _a-Ceach band-gap energy all substantially can equal or barrier region 550 can be less than _a-Ceach band-gap energy 516 _a-C.

In the configuration, the first quantum well 514 _awith the second quantum well 514 _bbetween hole energy barrier 554 _athe second quantum well 516 can be less than _bwith the 3rd quantum well 516 _cbetween hole energy barrier 554 _b.In other words, across barrier region 516 _a-Chole energy barrier 554 _a-Ccan increase in a stepped fashion along the direction extending to wall 118 from end-blocking layer 120 across active area 506.Electron hole energy barrier 554 _a-Cit is quantum well region 514 _a-Cwith close on barrier region 516 _a-Cbetween the capacity volume variance of valence band 552 of both sides, interface.As making electron hole energy barrier 554 _a-Cacross barrier region 516 _a-Calong the result increased from end-blocking layer 120 to wall 108, can realize the increase of hole distribution homogeneity in active area 506, this can make the improved efficiency of the luminescent device duration of work manufactured by semiconductor structure bodies 500.

As mentioned before, barrier region 516 _a-Ccan have following material the Nomenclature Composition and Structure of Complexes configuration, it is selected as each barrier region 516 _a-Cthe corresponding band-gap energy 550 that they are different is provided _a-C.For example be not construed as limiting, each barrier region 516 _a-Cternary Ill-nitride material can be comprised, such as In _b3ga _1-b3n, wherein b3 is at least about 0.01.Reduce barrier region 516 _a-Cin _b3ga _1-b3indium content (that is, reducing the value of b3) in N can increase barrier region 516 _a-Cband-gap energy.Therefore, the second barrier region 516 _bcan have relative to the first barrier region 516 _alower indium content, and the 3rd barrier region 516 _cmay have relative to the second barrier region 516 _blower indium content.In addition, barrier region 516 _a-Cwith well region 514 _a-Ccan adulterate, and can have as above about the average thickness as described in semiconductor structure bodies 100.

As mentioned before, according to embodiment of the present disclosure, (Figure 1A) active area 106 can comprise at least one InGaN well layer and at least one InGaN barrier layer, and in some embodiments, active area 106 can form (such as by InGaN at least substantially, can be made up of InGaN in fact, but there is alloy).The great majority emitting device structure body comprising InGaN well layer known at present comprises GaN (at least substantially not containing indium) barrier layer.Conduction level difference between InGaN well layer and GaN barrier layer is relatively high, and according to instruction of the present invention, and this can improve the restriction of electric charge carrier in well layer and can make the improved efficiency of LED structure body.But the structure of prior art and method may cause device efficiency to reduce because of charge carrier overflow and piezoelectric polarization.

In charge carrier overflow theory, one or more quantum well layer can analogize to bucket, and it is captured and keeps the ability of the charge carrier injected to successively decrease with higher carrier injection.When the charge carrier injected is not captured and keeps, it is from active area overflow and loss, thus causes the decline of device efficiency.In the prior art structure comprising InGaN quantum well and GaN barrier layer, band skew (that is, the difference of the conduction level between quantum well and potential barrier) is significantly higher than the band skew of the basic active area be made up of InGaN as described in this paper execution mode.The reduction of the band skew in structure as herein described makes the charge carrier injected more effectively to distribute at the quantum well layer of active area, which thereby enhances the efficiency of the luminescent device manufactured by semiconductor structure bodies as herein described.

In addition, due to the lattice misfit between InGaN well layer and GaN barrier layer, in the active area of this kind of emitting device structure body, there is relatively strong piezoelectric polarization.Piezoelectric polarization can make the electron wave function in the active area of emitting device structure body reduce with overlapping between hole wave functions.Such as J.H.Son and J.L.Lee, NumericalAnalysisofEfficiencyDroopInducedbyPiezoelectric PolarizationinInGaN/GaNLight-EmittingDiodes, Appl.Phys.Lett.97, disclosed in 032109 (2010), piezoelectric polarization may cause the phenomenon being referred to as " efficiency decay " in this kind of emitting device structure body (such as, LED).Efficiency relaxation phenomenon is along with current density increases, the decay (decline) in internal quantum (IQE) figure of LED structure body.

The execution mode of ray structure body of the present disclosure (such as LED structure body) can alleviate or overcome and knownly at present has InGaN well layer and the relevant problem that decays to lattice misfit, charge carrier overflow, piezoelectric polarization phenomenon and efficiency in the LED structure body of GaN barrier layer.Can the LED of disclosure execution mode (the LED structure body such as manufactured by the semiconductor structure bodies 100 of Figure 1A and 1B) be configured and be designed its band structure, with the overlap making active area 106 show less piezoelectric polarization effect, larger electron wave function and hole wave functions.As a result, as the luminescent devices such as LED can show electric charge carrier across active area 106 homogeneity improve and efficiency decay with current density increase and reduce.

These advantages that can be obtained by embodiment of the present disclosure will discussed further below with reference to Figure 10 A and 10B, 11A ~ 11E, 12A and 12B and 13A ~ 13E.Figure 10 A with 10B shows the execution mode of the LED556 similar to existing known LED.LED556 includes source region 558, the GaN barrier layer 564 that this active area 558 comprises five (5) InGaN well layer 562 and is arranged between InGaN well layer 562.LED556 also comprises base layer 560, first wall 566, second wall 568, electronic barrier layer 570 and electrode layer 572.In LED556, InGaN well layer 562 comprises In _0.18ga _0.82n layer, its respective average thickness is about 2.5 nanometers (2.5nm).Barrier layer 564 comprises GaN layer, and its average thickness is about 10 nanometers (10nm).Base layer 560 comprises the doped gan layer that average thickness is about 325 nanometers (325nm), and it uses silicon with about 5e ¹⁸cm ^-3concentration carry out n-type doping.First wall 566 can comprise the non-Doped GaN that average thickness is about 25 nanometers (25nm).Second wall 568 also can comprise the non-Doped GaN that average thickness is about 25 nanometers (25nm).Electronic barrier layer 570 can comprise the AlGaN of p-doping.Electrode layer 572 can comprise doped gan layer, and the average thickness of this kind of electrode layer is about 125 nanometers (125nm), and it uses magnesium with about 5e ¹⁷cm ^-3concentration carry out the doping of p-type.Figure 10 B is the simplification conduction band diagram similar to Figure 1B, and the relative different of the energy level of the conduction band 574 (in energy band diagram) of different materials in the various layers of the LED556 of Figure 10 A is shown.Vertical dotted line in Figure 10 B is alignd with the interface between each layer in the LED556 of Figure 10 A.

As known in the art, such as S.L.Chuang and C.S.Chang can be used, kpMethodforStrainedWurtziteSemiconductors, Phys.Rev.B54,8 × 8Kane model disclosed in 2491 (1996) characterizes the valence band structure as III-nitride material such as GaN and InGaN.The division that can suppose the heavy branch of the valence band of Brillouin district center, light branch and split (split-off) branch is independent of embedded electric field.Therefore, valency subzone (valencesubband) can be obtained from the solution of the Poisson's equation of coupling and transport equation.The wave function in electronics and hole can be supposed to be respectively following form:

U _nΨ _vexp (k _nr), and

u _p,sΨ _v,s·exp(k _p·r),

Wherein, u _nand u _p,scorrespond to the electronics of Brilluene district center and the Bloch amplitude in hole, k _nand k _paccurate moment vector in face, Ψ _vand Ψ _v,senvelope function, and subscript " s " can be attached most importance to (hh), light (lh) or split (so) hole.One dimension Schrodinger equation for electronics and hole envelope function is respectively:

with

Wherein, with the effective electromotive force in electronics in quantum well and hole, E _vand E _v,selectronics and hole energy level, and with it is the effective mass in electronics on epitaxial growth direction and hole.By with the above-mentioned Schrodinger equation of the Boundary Condition for Solving of correspondence, can by the overlap integral of following acquisition electronics and hole wave functions:

$<{\mathrm{\&Psi;}}_i^e|{\mathrm{\&Psi;}}_j^h>=\underset{-\mathrm{\&infin;}}{\overset{\mathrm{\&infin;}}{\&Integral;}}{\mathrm{\&Psi;}}_i^e\left(z\right){\mathrm{\&Psi;}}_i^h\left(z\right)dz$

As S.L.Chuang, PhysicsofPhonicDevices, the 2nd edition, disclosed in (Wiley, NewJersey, 2009), the radiative recombination rate in electronics and hole can as follows given by:

$R^{rad}=B\&CenterDot;np\&CenterDot;\&lsqb;1-\exp (-\frac{F_n-F_p}{kT})\&rsqb;$

Wherein, B is radiative recombination coefficient, and n is electron concentration, and p is hole concentration, and F _n-F _pthat quasi-Fermi level is separated.Electronics is separated along with the position in LED active area with hole concentration and quasi-Fermi level and changes.Greatest irradiation recombination rate in any quantum well can be determined and thought the peak of radiation recombination rate of this corresponding quantum well.

Figure 11 A shows the figure of the calculating energy of the conduction band 574 of the LED550 of Figure 10 A and Figure 10 B and the band edge of valence band 576, and this calculating energy is the surface initial function with position (in nanometer) LED556 relative with active area 558 from base layer 560 when applying 0 electric current to LED556.Figure 11 B is the figure similar to Figure 11 A, but it illustrates and LED556 is being applied to 125 amperes of/square centimeter (125A/cm ²) current density time, the calculating energy of the conduction band 574 of the LED556 of Figure 10 A and Figure 10 B and the band edge of valence band 576.Figure 11 C shows and LED550 is being applied to 125 amperes of/square centimeter (125A/cm ²) current density time calculating strength and LED556 5 quantum well layers 562 in the figure of function of wavelength of each layer.Be leftmost side quantum well layer 562 from Figure 10 A and Figure 10 B, QW1, and QW5 is rightmost side quantum well layer 562.Figure 11 D shows the function of the calculating injection efficiency of LED556 and the current density of applying.As shown in Figure 11 D, LED550 is at applying 125A/cm ²current density time can show about 75.6% injection efficiency.Figure 11 E shows the calculating internal quantum (IQE) of LED556 and the function of the current density applied.As depicted in fig. 1 ie, LED556 is at applying 125A/cm ²current density time can show about 45.2% internal quantum.In addition as depicted in fig. 1 ie, the internal quantum of LED556 can from applying 20A/cm ²current density time drop to more than 50% apply 250A/cm ²current density time lower than 40%.As previously discussed, in this area, this decline of IQE is called that efficiency decays.

Following table 1 shows the Wave function overlap and peak of radiation recombination rate that calculate each layer in 5 quantum well layers 562 in the LED550 of Figure 10 A and Figure 10 B.

Table 1

	QW1	QW2	QW3	QW4	QW5
						Wave function overlap	0.328	0.326	0.325	0.341	0.362
Peak of radiation recombination rate	6.5e 26	3.3e 26	3.3e 26	6.8e 26	2.4e 27

As can be seen from Figure 11 C and upper table 1, radiation recombination is mainly from last well layer 562 (side closest to p-doping or negative electrode), and it is No. five quantum well (that is, QW5) in LED556.In addition, as depicted in fig. 1 ie, LED556 shows efficiency decay, and this may at least in part because piezoelectric polarization caused, described piezoelectric polarization as herein above to discuss be caused by the use of InGaN well layer 562 and GaN barrier layer 564.

Of the present disclosurely include source region (it comprises at least one InGaN well layer and at least one InGaN barrier layer, active area 106 as LED100) the execution mode of the LED homogeneity that can show the radiation recombination occurred in well layer improve, and less efficiency decay can be shown.The contrast to LED execution mode of the present disclosure and LED550 is provided below with reference to Figure 12 A and 12B and 13A ~ 13E.

Figure 12 A and 12B shows another example of the LED600 of disclosure execution mode.LED600 includes source region 106, the InGaN barrier layer 116 that this active area 106 comprises five (5) InGaN well layer 114 and is arranged between InGaN well layer 114.InGaN well layer 114 and InGaN barrier layer 116 can as above with reference to Figure 1A and 1B about as described in semiconductor structure bodies 100.LED600 can also comprise base layer 112, first wall 118, end-blocking layer 120 and InGaN electrode layer 104.In LED600, InGaN well layer 114 comprises In _0.18ga _0.82n layer, its respective average thickness is about 2.5 nanometers (2.5nm).Barrier layer 116 comprises In _0.08ga _0.92n layer, and respective average thickness can be about 10 nanometers (10nm).Base layer 112 comprises the doping In that average thickness is about 300 nanometers (300nm) _0.05ga _0.95n layer, it uses silicon with about 5e ¹⁸cm ^-3concentration carry out n-type doping.First wall 118 can comprise the In that do not adulterate that average thickness is about 25 nanometers (25nm) _0.08ga _0.92n.End-blocking layer 120 also can comprise the In that do not adulterate that average thickness is about 25 nanometers (25nm) _0.08ga _0.92n.It can be the doping In of about 150 nanometers (150nm) that electrode layer 104 can comprise average thickness _0.05ga _0.95n layer, it uses magnesium with about 5e ¹⁷cm ^-3concentration carry out the doping of p-type.Figure 12 B is the conduction band diagram simplified, and it illustrates the relative different of the energy level of (in energy band diagram) conduction band 602 of different materials in each layer to the LED600 of Figure 12 A.

Figure 13 A shows the figure of the calculating energy of the conduction band 602 of the LED600 of Figure 12 A and 12B and the band edge of valence band 604, and this calculating energy is the surface initial function with position (in nanometer) LED600 relative with active area 106 from base layer 112 when applying 0 electric current to LED600.Figure 13 B schemes with like Figure 13 category-A, but it illustrates at applying 125 amperes of/square centimeter (125A/cm to LED600 ²) current density time, the calculating energy of the conduction band 602 of the LED600 of Figure 12 A and 12B and the band edge of valence band 604.Figure 13 C illustrates LED600 is being applied to 125 amperes of/square centimeter (125A/cm ²) current density time calculating strength and LED600 5 quantum well layers 108 in the figure of function of wavelength of each layer.Be leftmost side quantum well layer 108 from Figure 12 A and 12B, QW1, and QW5 is rightmost side quantum well layer 108.Figure 13 D shows the function of the calculating injection efficiency of LED600 and the current density of applying.As illustrated in figure 13d, LED600 is at applying 125A/cm ²current density time can show about 87.8% injection efficiency, and can from 20A/cm ²extend to about 250A/cm ²current density range in show Carrier Injection Efficiency at least about 80%.Figure 13 E shows the calculating internal quantum (IQE) of LED600 and the function of the current density applied.As shown in figure 13e, LED600 is at applying 125A/cm ²current density time can show about 58.6% internal quantum.In addition as shown in figure 13e, from 20A/cm ²extend to about 250A/cm ²applying current density range in, the internal quantum of LED600 can be maintained at about 55% ~ about 60%.Therefore, LED600 shows minimum efficiency decay, and the decay of its efficiency is significantly less than the efficiency decay that LED500 (this LED500 is not embodiment of the present disclosure) shows.

Following table 2 shows the Wave function overlap calculated to each layer in 5 quantum well layers 108 in the LED600 of Figure 12 A and Figure 12 B and peak of radiation recombination rate.

Table 2

	QW1	QW2	QW3	QW4	QW5
						Wave function overlap	0.478	0.493	0.494	0.494	0.471
Peak of radiation recombination rate	7.8e 26	7.7e 26	7.9e 26	8.1e 26	8.3e 26

As can be seen from Figure 13 C and upper table 2, compared with the well layer 508 in LED500, the radiation recombination in the well layer 108 of LED600 is more homogeneous.

The commercially available LED600 of SiLENSe software to LED550 and Figure 12 A and 12B of Figure 10 A and 10B from STRGroup, Inc. is utilized to carry out modeling.SiLENSe software also can be used for the figure generating Figure 11 A ~ 11E and 13A ~ 13E, and for obtaining the data listed in table 1 and 2.

According to some execution mode of the present disclosure, LED can from about 20A/cm ²extend to about 250A/cm ²current density range in show internal quantum at least about 45%, from about 20A/cm ²extend to about 250A/cm ²current density range in show internal quantum at least about 50%, or from about 20A/cm ²extend to about 250A/cm ²current density range in show internal quantum at least about 55%.In addition, LED can from about 20A/cm ²extend to about 250A/cm ²current density range in show at least substantially invariable Carrier Injection Efficiency.In some embodiments, LED of the present disclosure can from about 20A/cm ²extend to about 250A/cm ²current density range in show Carrier Injection Efficiency at least about 80%.

Schematically illustrate the limiting examples of the method for semiconductor structure bodies and the luminescent device (such as LED) that can utilize and manufacture embodiment of the present disclosure below with reference to Fig. 6 D, and describe the example of the luminescent device manufactured by these class methods with reference to Fig. 7 and Fig. 8.

With reference to Fig. 6 D, growth templates 113 (mentioned above so) can be set in settling chamber, growth templates comprises growth substrates 658, group III-nitride nucleating layer 660 and GaN crystal seed layer 656, and can on the crystal seed layer 656 of growth templates 113 continuously epitaxial growth comprise the layer of III-nitride material, it is commonly referred to growth duplexer.It should be noted, although crystal seed layer 656 illustrates with the continuous film be in growth substrates 658, in some embodiments, namely wherein crystal seed layer comprises multiple " island " crystal seed layer, and described crystal seed layer can comprise the discontinuous film be in growth substrates 658.

Fig. 6 D shows the semiconductor structure bodies 680 comprising growth templates 113, and growth templates 113 has each layer of the semiconductor structure bodies 100 that it deposited Figure 1A and 1B.Especially, the optional In of semiconductor structure bodies 100 _nga _1-nthe direct epitaxial deposition of N base layer 112 is on GaN crystal seed layer 656, and InGaN wall 118, InGaN well layer 114, InGaN barrier layer 116, InGaN end-blocking layer 120, electronic barrier layer 108, p-type body layer 110 and p-type contact layer 104 in turn epitaxial deposition are on growth templates 112.

Metal organic chemical vapor deposition (MOCVD) method and system such as can be utilized to deposit in single settling chamber comprise each layer of the semiconductor structure bodies 680 of growth duplexer 682, that is, without the need to this growth duplexer of load or unload in deposition process.Growth templates comprises in the embodiment of the present disclosure of growth substrates, group III-nitride nucleating layer 660 and GaN respect layer wherein, semiconductor structure bodies 680 can be formed overall in growth substrates 658, namely without the need to compression and decompression during deposition procedures in the single growth cycle.

Pressure in settling chamber can be decreased to about 50mTorr ~ about 500mTorr.In the deposition process of growth duplexer 682, can increase in deposition process and/or reduce the pressure in reative cell, and this pressure can adjust for certain layer to be deposited.As limiting examples, at deposition In _nga _1-nin the process of N base layer 112, InGaN wall 118, one or more well layer 114, one or more barrier layer 116, InGaN end-blocking layer 120 and electronic barrier layer 108, the scope of reative cell internal pressure can be about 50mTorr ~ about 500mTorr, and can equal about 440mTorr in some embodiments.Scope for depositing the reative cell internal pressure of p-type body layer 110 and p-type contact layer 104 for about 50mTorr ~ about 250mTorr, and can equal about 100mTorr in some embodiments.

Growth templates 113 can be heated to the temperature of about 600 DEG C ~ about 1000 DEG C in settling chamber.Then metallorganic precursors gas and other precursor gases (and optional carrier gas and/or sweep gas) can be made to flow through settling chamber and flow on the crystal seed layer 656 of growth templates 113.Metallorganic precursors gas can carry out reacting and/or decomposing, and makes Ill-nitride layer (as InGaN layer) epitaxial deposition on growth templates 113 thus.

As limiting examples, trimethyl indium (TMI) can be used as the metallorganic precursors of the indium of InGaN, triethyl-gallium (TMG) can be used as the metallorganic precursors of the gallium of InGaN, triethyl aluminum (TMA) can be used as the metallorganic precursors of the aluminium of AlGaN, and ammonia can be used as the precursor of the nitrogen of Ill-nitride layer.When needs carry out n-type doping to group III-nitride, SiH can be used ₄as precursor, silicon is introduced InGaN; When needs carry out the doping of p-type to group III-nitride, can use Cp2Mg (two (cyclopentadienyl group) magnesium), as precursor, magnesium is introduced group III-nitride.Advantageously, regulate indium precursor (such as, trimethyl indium) and the ratio of gallium precursor (such as, triethyl-gallium), make the concentration of the indium added in InGaN close to the saturation point of indium during depositing temperature in InGaN thus.By controlling growth temperature, can along with the percentage of the indium added in the epitaxial growth control InGaN of InGaN.To the indium of higher relative amounts be added when relatively lower temp, and will the indium of relatively low quantities be added when comparative high temperature.As limiting examples, can in the temperature range deposition InGaN well layer 108 extending to about 950 DEG C from about 600 DEG C.

Can raise and/or reduce the depositing temperature of each layer of growth duplexer 682 in deposition process, and can adjust for certain layer to be deposited.As limiting examples, In _nga _1-ndeposition temperature range between the depositional stage of N base layer 112, p-type body layer 110 and p-type contact layer 104 can be about 600 DEG C ~ about 950 DEG C, and can equal about 900 DEG C in some embodiments.In _nga _1-nthe growth rate scope of N base layer 112, p-type body layer 110 and p-type contact layer 104 can be about 1 nm/minute (1nm/min) ~ about 30 nm/minute (30nm/min).In in some embodiments _nga _1-nthe growth rate of N base layer 112, p-type body layer 110 and p-type contact layer 104 can equal about 6 nm/minute (6nm/min).

In other non-limiting example execution mode, between the depositional stage of wall 118, one or more well layer 114, one or more barrier layer 116, end-blocking layer 120 and electronic barrier layer 108, deposition temperature range can be about 600 DEG C ~ about 950 DEG C, and can equal about 750 DEG C in some embodiments.The growth rate scope of wall 118, one or more well layer 114/ barrier layer 116, end-blocking layer 120 and electronic barrier layer 108 can be about 1 nm/minute (1nm/min) ~ about 30 nm/minute (30nm/min), and the growth rate of wall 118, one or more well layer 114/ barrier layer 116, end-blocking layer 120 and electronic barrier layer 108 can equal about 1 nm/minute (1nm/min) in some embodiments.

In the execution mode comprising deposition InGaN layer, the velocity ratio of precursor gases can be selected to provide the InGaN layer of high-quality.Such as, can comprise for the formation of the method for the InGaN layer of semiconductor structure bodies 100 and select gas ratio to have fabricating low-defect-density to provide, substantially there is no strain relaxation and substantially there is no one or more InGaN layer of surperficial pitfall.

In limiting examples, the flow-rate ratio (%) of trimethyl indium (TMI) and triethyl-gallium (TMG) can be defined as:

And this flow-rate ratio can increase and/or reduce in deposition process, thus for specific InGaN layer adjustment to be deposited.As limiting examples, In _nga _1-nflow-rate ratio scope between N base layer 112 and p-type body layer 110 depositional stage can be about 50% ~ about 95%, and can equal about 85% in some embodiments.In other embodiments, wall 118, flow-rate ratio scope between one or more barrier layer 116 and end-blocking layer 120 depositional stage can be about 1% ~ about 50%, and can equal about 2% in some embodiments.In other execution mode, the flow-rate ratio scope between one or more quantum well layer 114 depositional stage can be about 1% ~ about 50%, and can equal about 30% in some embodiments.

In deposition process, growth templates 113 can be made alternatively to rotate in settling chamber.As limiting examples, growth templates 113 can rotate with the velocity of rotation of about 50 revs/min (RPM) ~ about 1500 rev/min (RPM) in deposition process in settling chamber, and can rotate with the rotary speed equaling about 450 revs/min (RPM) in some embodiments.Rotary speed in deposition process can increase and/or reduce between depositional stage, and thus can adjust for certain layer to be deposited.As limiting examples, at In _nga _1-nn base layer 112, wall 118, one or more well layer 114, or many barrier layers 116, between end-blocking layer 120 and electron barrier layer 108 depositional stage, growth templates rotary speed can be about 50 revs/min (RPM) ~ about 1500 rev/min (RPM), and can rotate with the rotary speed equaling about 440 revs/min (RPM) in some embodiments.Between p-type body layer 110 and p-type contact layer 104 depositional stage, the rotary speed of growth templates 113 can be about 50 revs/min (RPM) ~ about 1500 rev/min (RPM), and can rotate with the rotary speed equaling about 1000 revs/min (RPM) in some embodiments.

In the execution mode of semiconductor structure bodies of the present disclosure comprising depositing group III-nitride thing, particularly InGaN layer, the strain energy that comprise the one or more InGaN layer of growth duplexer 682 of epitaxial deposition on growth templates 113 may affect the efficiency of the luminescent device manufactured by described semiconductor structure bodies.In some embodiments, growing the total strain energy produced in duplexer 682 may be relevant to the efficiency of the semiconductor structure bodies of the present disclosure defined by internal quantum (IQE).

More specifically, the strain energy stored in n-th layer InGaN layer and the average total thickness T of described n-th layer InGaN layer _nbe directly proportional, and with the indium concentration %In in described n-th layer InGaN layer _nbe directly proportional.In addition, the average total thickness T of total strain energy and each InGaN layer stored in multiple InGaN layer of growth duplexer 682 is comprised _nsum is directly proportional, and with the indium concentration %In in each InGaN layer _nbe directly proportional, the total strain energy therefore comprised in the InGaN layer of growth duplexer 702 can be estimated in order to lower equation:

Total strain energy (a.u.) ∝ Σ (%In _n× T _n)

Wherein, the average total thickness T of n-th layer _nexpress with nanometer (nm), and the indium concentration %In in n-th layer InGaN layer _nexpress with atomic percent.Such as, if the average total thickness T of n-th layer InGaN layer _nbe 150 nanometers (150nm) and indium concentration %In _nfor 2.0at%, then the strain energy in n-th layer InGaN layer can be 300a.u. (300=150 (2)).

Fig. 9 shows the Figure 90 0 showing relation between the IQE (a.u.) of semiconductor structure bodies of the present disclosure and total strain energy (a.u.).As shown in the line 902 of Figure 90 0, at the total strain energy value place of " critical strain energy " being called semiconductor structure bodies, the IQE of semiconductor structure bodies of the present disclosure may reduce.IQE (being represented by line 904) lower than semiconductor structure bodies during critical strain energy may be obviously larger than the IQE (being represented by line 906) higher than semiconductor structure bodies during critical strain energy, such as, Figure 90 0 shows the IQE value (as shown in rectangle marked) of several semiconductor structure bodies of the present disclosure.In some embodiments, may than higher than the IQE about 500% during critical strain energy lower than IQE during critical strain energy.In other embodiments, may than higher than the IQE height about 250% during critical strain energy lower than IQE during critical strain energy.In other embodiments, may than higher than the IQE height about 100% during critical strain energy lower than IQE during critical strain energy.

For semiconductor structure bodies of the present disclosure, the value of the critical strain energy 902 that the sum of products being multiplied by each layer indium content (in %) by each layer thickness (in nm) defines can be about less than 1800, about less than 2800 or about less than 4500.

In the disclosure, multiple group III-nitride of the growth duplexer 682 comprising Fig. 6 D can be deposited as growth duplexer 682 is strained substantially completely with the crystal lattice match of the GaN crystal seed layer 656 with growth templates 113.In this type of execution mode, when grow duplexer 682 be grown to strain substantially completely time (that is, substantially there is no strain relaxation), this growth duplexer can inherit the crystal lattices of GaN crystal seed layer.In some execution mode of the present disclosure, GaN crystal seed layer can show the growth plane lattice parameter being more than or equal to about 3.186 dusts, and described growth duplexer can show the growth plane lattice parameter being more than or equal to about 3.186 dusts.Therefore, in limiting examples, semiconductor structure bodies 100,200,300,400 and 500 material be formed as by straining completely can be formed, and above-mentioned growth plane lattice parameter can be had.

In other embodiments, multiple group III-nitride of the growth duplexer 682 comprising Fig. 6 D can be deposited as and make growth duplexer 682 partial relaxation, that is, the lattice parameter growing duplexer 682 is different from down the GaN crystal seed layer covered.In this type of execution mode, strain relaxation percentage (R) can be defined as:

$R\left(\%\right)=\frac{a-a_s}{a_l-a_s}\&times;100$

Wherein, a is the average production plane lattice parameter of growth duplexer 682, a _sthe average production plane lattice parameter of GaN crystal seed, and a _lit is balance (or nature) the average production plane lattice parameter of growth duplexer.Such as, in some embodiments, growth duplexer 682 can show the strain relaxation percentage (R) being less than about 0.5%, grow duplexer 682 in other embodiments and can show the strain relaxation percentage (R) being less than about 10%, and in other execution mode, grow duplexer 682 can show the strain relaxation percentage (R) being less than about 50%.

After epitaxial deposition comprises each layer of the semiconductor structure bodies of III-nitride material, further processing can be carried out to complete the manufacture of semiconductor structure bodies to luminescent devices such as such as LED.Such as, can utilize known in the art and on III-nitride material layer, form electrode contact below with reference to the method that Fig. 7 and Fig. 8 briefly describes.

The example as the luminescent devices such as LED 700 manufactured by semiconductor structure bodies 100 has been shown in Fig. 7.Although following description describes the execution mode for manufacturing luminescent device from semiconductor structure bodies 100, should notice that this kind of manufacture method also can be applied to semiconductor structure bodies 200,300,400 and 500.

More specifically, the part that can remove semiconductor structure bodies 100 makes In thus _nga _1-na part for N base layer 112 exposes, and is eliminating In _nga _1-nthe part that can remove semiconductor structure bodies 100 in some execution mode of N base layer exposes to make GaN crystal seed layer 656.The removal (not shown) of the selected part to semiconductor structure bodies 100 can be realized by the surface applications photosensitizing chemical thing of the p-contact layer 100 exposed semiconductor structure bodies 100.Carry out electromagnetic radiation exposure at the transparent panel through patterning and after development subsequently, photosensitive layer can be utilized as " mask layer " selectivity In can be removed _nga _1-nill-nitride layer on N base layer 112.In _nga _1-nthe removing of selected part of the Ill-nitride layer above N base layer 112 can comprise etching process, such as, and wet chemical etch and/or dry plasma class etching (such as, reactive ion etching, inductively coupled plasma etching).

The In that can expose _nga _1-na part for N base layer 112 is formed the first electrode contact 702.First electrode contact 702 can comprise one or more metals, and it can comprise titanium, aluminium, nickel, gold and one or more its alloys.The second electrode contact 704 can be formed in a part for p-type contact layer 104.Second electrode contact 704 can comprise one or more metal level, and it can comprise nickel, gold, platinum, silver and one or more its alloys.After forming the first electrode contact 702 and the second electrode contact 704, electric current can be made by luminescent device 700 to produce electromagnetic radiation, such as, the electromagnetic radiation of visible ray form.It should be noted that luminescent device 700 is commonly referred to " transversal device " in the art because the current path between the first electrode contact 702 and the second electrode contact 704 comprise cross walkway at least partially.

Another example as the luminescent devices such as LED 800 manufactured by semiconductor structure bodies 100 has been shown in Fig. 8.Equally, although following description describes the execution mode for manufacturing luminescent device from semiconductor structure bodies 100, should notice that this kind of manufacture method also can be applied to semiconductor structure bodies 200,300,400 and 500.

More specifically, the whole or a part of of growth templates 113 can be removed from semiconductor structure bodies 100, thus GaN crystal seed layer 656 can be made to expose or make In in some embodiments _nga _1-nn base layer 112 exposes.Whole or a part of the removing of growth templates 113 can comprise one or more removing methods, comprises Wet-type etching, dry-etching, chemico-mechanical polishing, polishing and laser and divests.After removing the whole of growth templates 113 or a part, can as described above to In _nga _1-nn base layer 112 applies the first electrode contact 802.Subsequently, the second electrode contact 804 can be applied to a part for p-contact layer 104, form luminescent device 800 thus.After forming the first electrode contact 802 and the second electrode contact 804, electric current can be made by luminescent device 800 to produce electromagnetic radiation, such as, the electromagnetic radiation of visible ray form.It should be noted that luminescent device 800 is commonly referred to " longitudinal device " in the art, because the current path between the first electrode contact 802 and the second electrode contact 804 comprises basic longitudinal path.

Except the manufacture method for the manufacture of non-restrictive illustrative luminescent device 700 and 800 mentioned above and technique, should note, also other Method and process known in the art can be utilized, such as, surface roughening extracts, to be combined with metallic carrier technique and other known manufacture method of dispel the heat to improve, cut singualtion (dicingandsingulation), be called in interconnect (interconnection) and this area " back bonding (flip-chipbonding) " to improve light.

Can to manufacture in disclosure execution mode as luminescent devices such as LED and use it for and wherein be incorporated in any type luminescent device of one or more LED.The LED of disclosure execution mode is particularly suitable for being used in the LED that benefits from and work under relative high powers and needs in the application of relatively high illumination.Such as, LED of the present disclosure can be particularly suitable for being used in LED desk lamp and LED class bulb, and the latter may be used for architectural lighting, street lighting, automotive lighting etc.

Other execution mode of the present disclosure comprises the illuminating device for luminescence, and it comprises one or more LED as herein described, the luminescent device 700 of such as Fig. 7 and the luminescent device 800 of Fig. 8.As limiting examples, illuminating device can authorize the United States Patent (USP) 6 of Baretz etc. on July 29th, 2003 as such as, describe in 600, No. 175 (being incorporated to its overall disclosure herein by quoting), but comprise one or more LED as herein described.

Figure 14 shows the example embodiment of the illuminating device of the present disclosure 900 comprising luminescent device (device 700,800 as described hereinabove with respect to figures 7 and 8).As shown in figure 14, illuminating device 900 can comprise container 902, this container 902 at least partially at least substantially transparent of the electromagnetic radiation in the visual field of electromagnetic radiation spectrum.Container 902 can comprise such as amorphous or crystalline ceramic material (such as, glass) or polymeric material.LED800 is arranged in container 902, and can be arranged on (such as, printed circuit board (PCB) or other substrate) on the body support structure 904 in container 902.Illuminating device 900 can also comprise the first electrode contact structure body 906 and the second electrode contact structure body 908.First electrode contact structure body 906 can with of a LED electrode contact (such as, first electrode contact 802 (Fig. 8)) electric connection, and the second electrode contact structure body 908 can with another electrode contact of LED (such as, the second electrode contact 804 (Fig. 8)) electric connection.As limiting examples, the first electrode contact structure body 906 can pass through body support structure 904 and the first electrode contact 804 electric connection, and wire 910 can be used to be electrically connected with the second electrode contact 804 by second electrode contact structure body 908.Therefore, voltage can be applied between the first electrode contact structure body 906 of illuminating device 900 and the second electrode contact structure body 908, to provide voltage and corresponding electric current between first electrode contact 802 and the second electrode contact 804 of LED, LED is caused to send radiation thus.

Alternatively, illuminating device 900 can also comprise fluorescence or phosphor material, the electromagnetic radiation that this fluorescence or phosphor material can be launched by the one or more LED800 absorbed in container 902 is activated or excites and its own transmission electromagnetic radiation (such as, visible ray).Such as, the inner surface 912 of container 902 can be coated with this type of fluorescence or phosphor material at least partly.One or more LED800 can be transmitted in the electromagnetic radiation of one or more specific wavelength, and described fluorescence or phosphor material can comprise the mixture of the different materials by launching different visible wavelength radiation, thus make illuminating device 900 from container 902 outwards transmitting white.Various types of fluorescence or phosphor material are as known in the art and can be used in the execution mode of illuminating device of the present disclosure.Such as, some this kind of materials are disclosed in aforesaid U.S. Patent 6,600, in No. 175.

The other limiting examples of embodiment of the present disclosure is hereafter described.

Execution mode 1: a kind of semiconductor structure bodies, it comprises: base layer; Be arranged on the active area on described base layer, described active area comprises multiple InGaN layer, and described multiple InGaN layer comprises at least one and comprises In _wga _1-wwell layer and at least one of N comprise In _bga _1-bthe barrier layer of N, wherein 0.10≤w≤0.40,0.01≤b≤0.10; Be arranged on the electronic barrier layer on the side relative with described base layer, described active area, described electronic barrier layer comprises In _ega _1-en, wherein 0.00≤e≤0.02; Be arranged on the p-type In of described electronic barrier layer _pga _1-pn body layer, wherein 0.00≤p≤0.08; Be arranged on described p-type In _pga _1-pp-type In on N body layer _cga _1-cn contact layer, wherein 0.00≤c≤0.10.

Execution mode 2: the semiconductor structure bodies of execution mode 1, wherein, described base layer also comprises growth templates, and described growth templates comprises: growth substrates; With the GaN crystal seed layer be arranged in described growth substrates, the growth plane of wherein said GaN crystal seed layer comprises polar plane.

Execution mode 3: the semiconductor structure bodies of execution mode 1 or execution mode 2, wherein said base layer also comprises n-type In _nga _1-nn base layer, wherein 0.01≤n≤0.10.

Execution mode 4: any one semiconductor structure bodies in execution mode 1 to 3, it also comprises the In be arranged on the side relative with described base layer, active area _spga _1-spn wall, wherein 0.01≤sp≤0.10.

Execution mode 5: any one semiconductor structure bodies in execution mode 1 to 4, it also comprises the In be arranged between active area and electronic barrier layer _cpga _1-cpn end-blocking layer, wherein 0.01≤cp≤0.10.

Execution mode 6: the semiconductor structure bodies of execution mode 2, wherein, the average thickness of described GaN crystal seed layer is about 1.0 μm to about 5 μm.

Execution mode 7: any one semiconductor structure bodies in execution mode 2 to 6, wherein, described growth templates also comprises the group III-nitride nucleating layer be arranged between described growth substrates and described GaN crystal seed layer.

Execution mode 8: any one semiconductor structure bodies in execution mode 1 to 7, wherein, the average thickness of described active area is about 40nm to about 750nm.

Execution mode 9: the semiconductor structure bodies according to any one of execution mode 1 to 8, wherein said electronic barrier layer is at least basic to be made up of GaN.

Execution mode 10: the semiconductor structure bodies according to any one of execution mode 1 to 9, wherein said p-type In _pga _1-pthe average thickness of N body layer is about 50nm to about 600nm.

Execution mode 11: the semiconductor structure bodies described in execution mode 10, wherein said p-type In _pga _1-pthe average thickness of N body layer is about 175nm.

Execution mode 12: the semiconductor structure bodies according to any one of execution mode 1 to 11, wherein said p-type In _cga _1-cn contact layer is at least basic to be made up of GaN.

Execution mode 13: any one semiconductor structure bodies in execution mode 1 to 12, wherein, the critical strain of described semiconductor structure bodies can be about less than 1800.

Execution mode 14: any one semiconductor structure bodies in execution mode 1 to 13, wherein, described base layer, described active area, described electronic barrier layer, described p-type In _pga _1-pn body layer and described p-type In _cga _1-cn contact layer defines the growth duplexer showing the strain relaxation percentage being less than 10%.

Execution mode 15: any one semiconductor structure bodies in execution mode 1 to 14, it also comprises the first electrode contact gone up at least partially being in described base layer and the second electrode contact gone up at least partially being in described p-type contact layer.

Execution mode 16: a kind of luminescent device, described luminescent device comprises: base layer; Be arranged on the active area on described base layer, described active area comprises multiple InGaN layer, and described multiple InGaN layer comprises at least one well layer and is set directly at least one barrier layer at least one well layer described; Be arranged on the electronic barrier layer on described active area; Be arranged on the p-type In of described electronic barrier layer _pga _1-pn body layer; Be arranged on described p-type In _pga _1-pp-type In on N body layer _cga _1-cn contact layer, wherein, the critical strain of described luminescent device can be less than 1800.

Execution mode 17: the luminescent device of execution mode 16, wherein, described base layer also comprises growth templates, and described growth templates comprises: growth substrates; With the GaN crystal seed layer be arranged in described growth substrates, the growth plane of wherein said GaN crystal seed layer comprises polar plane.

Execution mode 18: the luminescent device of execution mode 16 or execution mode 17, wherein, at least one well layer described comprises In _wga _1-wn, wherein 0.10≤w≤0.40.

Execution mode 19: any one luminescent device in execution mode 16 to 18, wherein, at least one barrier layer described comprises In _bga _1-bn, wherein 0.01≤b≤0.10.

Execution mode 20: any one luminescent device in execution mode 16 to 18, wherein, described electronic barrier layer is at least basic to be made up of GaN.

Execution mode 21: any one luminescent device in execution mode 16 to 20, wherein, at p-type In _pga _1-pin N body layer, 0.00≤p≤0.08.

Execution mode 22: any one luminescent device in execution mode 16 to 21, wherein, at described p-type In _cga _1-cin N contact layer, 0.01≤c≤0.10.

Execution mode 23: any one luminescent device in execution mode 16 to 22, wherein, described p-type In _cga _1-cn contact layer is made up of GaN substantially.

Execution mode 24: any one luminescent device in execution mode 16 to 23, it also comprises the first electrode contact gone up at least partially that is in described base layer and is in described p-type In _cga _1-csecond electrode contact gone up at least partially of N contact layer.

Execution mode 25: any one luminescent device in execution mode 16 to 24, wherein, described active area, described electronic barrier layer, described p-type In _pga _1-pn body layer and described p-type In _cga _1-cn contact layer collectively defines the growth duplexer showing the strain relaxation percentage being less than 1%.

Execution mode 26: a kind of method forming semiconductor structure bodies, it comprises: arrange base layer; Described base layer grows multiple InGaN layer to be formed with source region, the step growing multiple InGaN layer comprises at least one In of growth _wga _1-wn well layer and at least one In of growth _bga _1-bn barrier layer, wherein 0.10≤w≤0.40, and wherein 0.01≤b≤0.10; The side that described active area is relative with described base layer grows electronic barrier layer; Described electronic barrier layer grows p-type In _pga _1-pn body layer, wherein 0.00≤p≤0.08; With at described p-type In _pga _1-pn body layer grows p-type In _cga _1-cn contact layer, wherein 0.00≤c≤0.10.

Execution mode 27: the method for execution mode 26, wherein, the step arranging described base layer also comprises formation growth templates, and the step forming described growth templates comprises: arrange growth substrates; With growing GaN crystal seed layer in described growth substrates, the growth plane of wherein said GaN crystal seed layer is polar plane.

Execution mode 28: the method for execution mode 26 or execution mode 27, the step wherein arranging base layer also comprises growing n-type In _nga _1-nn base layer, wherein 0.01≤n≤0.10.

Execution mode 29: any one method in execution mode 26 to 28, it is also included between described active area and described base layer and grows In _spga _1-spn wall, wherein, 0.01≤sp≤0.10.

Execution mode 30: any one method in execution mode 26 to 29, it is also included between described active area and described electronic barrier layer and grows In _cpga _1-cpn end-blocking layer, wherein, 0.01≤cp≤0.10.

Execution mode 31: the method described in execution mode 27, it also comprises makes described GaN crystal seed layer be grown to average layer thickness in the scope with about 1.0 μm to about 7 μm.

Execution mode 32: execution mode 27 or the method described in execution mode 31, the step wherein forming described growth templates also comprises the group III-nitride nucleating layer depositing and be arranged between described growth substrates and described GaN crystal seed layer.

Execution mode 33: the method any one of execution mode 26 to 32, it also comprises makes described active region growth be the average thickness with about 40nm to about 750nm.

Execution mode 34: the method any one of execution mode 26 to 33, it also comprises makes described electronic barrier layer be grown at least substantially to be made up of GaN.

Execution mode 35: the method any one of execution mode 26 to 34, it also comprises makes described p-type In _pga _1-pn body layer is grown to the average layer thickness with about 50nm to about 600nm.

Execution mode 36: the method any one of execution mode 26 to 35, it also comprises makes described p-type In _cga _1-cn contact layer is grown to and is at least substantially made up of GaN.

Execution mode 37: any one method in execution mode 26 to 36, it also comprises and forms described base layer, described active area, described electronic barrier layer, described p-type In _pga _1-pn body layer and described p-type In _cga _1-cn contact layer is to make to which together define the growth duplexer showing the strain relaxation percentage being less than 1%.

Execution mode 38: the method for execution mode 37, it also comprises formation critical strain can for the growth duplexer of about less than 1800.

Execution mode 39: the method according to any one of execution mode 26 to 38, it grows described active area, described electronic barrier layer, described p-type In under being also included in the pressure of about 50mTorr to about 500mTorr in single chemical gas-phase deposition system _pga _1-pn body layer and described p-type In _cga _1-ceach in N contact layer.

Execution mode 40: any one method in execution mode 26 to 39, it is also included in when making trimethyl indium (TMI) and triethyl-gallium (TMG) flow through reative cell at reaction indoor growing p-type In _pga _1-pn body layer, wherein, the flow-rate ratio (%) of the flow velocity of described trimethyl indium (TMI) and the flow velocity of described triethyl-gallium (TMG) is about 50% ~ 95%.

Example embodiment of the present disclosure as described above does not limit scope of the present invention, because these execution modes are only the examples of embodiments of the present invention, the present invention limited by the scope of appended claim book and legal equivalents thereof.Any equivalent embodiments all should be within the scope of the invention.In fact, from above-mentioned explanation, except those execution modes shown herein and describe, various version of the present disclosure (such as the alternately useful combination of described key element) will become apparent for those skilled in the art.These versions and execution mode also should fall in the scope of appended claims.

Claims (14)

1. a semiconductor EL structure, it comprises:

Base layer, described base layer comprises n-type doped layer;

Be arranged on the active area on described base layer, described active area comprises multiple InGaN layer, and described multiple InGaN layer comprises at least one and comprises In _wga _1-wwell layer and at least one of N comprise In _bga _1-bthe barrier layer of N, wherein 0.10≤w≤0.40,0.01≤b≤0.10;

Be arranged on the electronic barrier layer on the side relative with described base layer, described active area, described electronic barrier layer comprises In _ega _1-en, wherein 0.00≤e≤0.02;

Be arranged on the p-type In on described electronic barrier layer _pga _1-pn body layer, wherein 0.00≤p≤0.08; With

Be arranged on described p-type In _pga _1-pp-type In on N body layer _cga _1-cn contact layer, wherein 0.00≤c≤0.10.

2. semiconductor EL structure as claimed in claim 1, wherein, described base layer also comprises growth templates, and described growth templates comprises:

Growth substrates; With

Be arranged on the GaN crystal seed layer in described growth substrates, wherein, the growth plane of described GaN crystal seed layer comprises polar plane.

3. semiconductor EL structure as claimed in claim 2, wherein, described growth templates also comprises the group III-nitride nucleating layer be arranged between described growth substrates and described GaN crystal seed layer.

4. semiconductor EL structure as claimed in claim 1, wherein, described n-type doped layer is n-type In _nga _1-nn base layer, wherein 0.01≤n≤0.10.

5. semiconductor EL structure as claimed in claim 1, wherein, described electronic barrier layer is made up of GaN.

6. semiconductor EL structure as claimed in claim 1, described p-type In _cga _1-cn contact layer is made up of GaN.

7. semiconductor structure bodies as claimed in claim 1, wherein, the summation that the critical strain of described semiconductor structure bodies can be multiplied by the product of each layer indium content (in %) by each layer thickness (in nm) limits, and is equal to or less than 1800.

8. form a method for semiconductor EL structure, it comprises:

The base layer comprising n-type doped layer is set;

Described base layer grows multiple InGaN layer to be formed with source region, the step growing multiple InGaN layer comprises at least one In of growth _wga _1-wn well layer and at least one In of growth _bga _1-bn barrier layer, wherein 0.10≤w≤0.40, and wherein 0.01≤b≤0.10;

Side relative with described base layer on described active area grows electronic barrier layer;

Described electronic barrier layer grows p-type In _pga _1-pn body layer, wherein 0.00≤p≤0.08; With

At described p-type In _pga _1-pn body layer grows p-type In _cga _1-cn contact layer, wherein 0.00≤c≤0.10.

9. method as claimed in claim 8, wherein, arranges described In _nga _1-nthe step of N base layer also comprises formation growth templates, and the step forming described growth templates comprises:

Growth substrates is provided; With

Growing GaN crystal seed layer in described growth substrates, wherein, the growth plane of described GaN crystal seed layer is polar plane.

10. method as claimed in claim 9, wherein, the step forming described growth templates also comprises the group III-nitride nucleating layer depositing and be located between described growth templates and described GaN crystal seed layer.

11. methods as claimed in claim 8, wherein providing package also comprises growth n-type In containing the step of the described base layer of n-type doped layer _nga _1-nn base layer, wherein 0.01≤n≤0.10.

12. methods as claimed in claim 8, described method also comprises growing GaN electronic barrier layer.

13. methods as claimed in claim 8, described method is also included in GaN and grows described p-type In _cga _1-cn contact layer.

14. methods as claimed in claim 8, described method also comprises and forms following semiconductor structure bodies: the limit stress of described semiconductor structure bodies can be multiplied by the product of the indium content (in %) of each layer summation by the thickness (in nm) of each layer limited, and is equal to or less than 1800.