CN105049056A - One-hot code detection circuit - Google Patents
One-hot code detection circuit Download PDFInfo
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- CN105049056A CN105049056A CN201510483798.4A CN201510483798A CN105049056A CN 105049056 A CN105049056 A CN 105049056A CN 201510483798 A CN201510483798 A CN 201510483798A CN 105049056 A CN105049056 A CN 105049056A
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Abstract
The invention relates to a one-hot code detection circuit. An existing circuit has a great area and great time expenditure to extra long one-hot code detection. The one-hot code detection circuit comprises an input compression module group based on a bisection method, and a state detection module. The input compression module group is composed of multiple stages of compression modules for compressing multi-bit input data into a 2-bit output state; the state detection module judges that all the input bits are zero, one bit is 1 or a plurality of bits are 1 according to the 2-bit state output by the input compression modules. The input compression module group comprises multiple stages of input compression modules connected in series, wherein the Nth-stage input compression module is composed of two parallel (N-1)th-stage input compression modules. The one-hot code detection circuit is capable of realizing the one-hot code detection by use of the bisection method and especially suitable for the detection of extra long one-hot codes having the bit number over 1000. The one-hot code detection circuit is simple in design so that the circuit area is saved and the power consumption is reduced; the one-hot code detection circuit also has the advantage in speed.
Description
Technical field
The present invention relates to a kind of one-hot encoding testing circuit, belong to integrated circuit (IC) design technical field.
Background technology
One-hot encoding, is called one-hotcode in english literature, and directly perceived is exactly that how many states just have how many bits, and only has a bit to be 1, and other are a kind of code system of 0 entirely.One-hot encoding effectively can improve speed and the reliability of circuit, and at encoder state machine, application is waited until in the aspects such as transfer encoding.
One-hot coding has a lot of disarmed state, use one-hot encoding occasion should detect the validity of one-hot encoding.Otherwise once enter disarmed state, circuit will be in error condition.
Detection for the less one-hot encoding of status number can use simple combinational circuit to realize.But when status number increases, the testing circuit complexity of one-hot encoding sharply increases.One-hot encoding for overlength needs special circuit to realize.
For less or medium scale one-hot encoding testing circuit can by coding-1 again with original encoding step-by-step and, all bit phases of the data after operation or and export H; All bit phases of coding and output state position G.When coding only has 1 bit to be 1, G=0, H=1; When to have more than 1 bit be 1 to coding, G=1, H=1; When being encoded to complete zero, G=1, H=0.The state of one-hot encoding can be detected according to the value of G and H.But this method needs the subtracter of bit more than.After bit number increases, being on a grand scale of subtracter, and also speed cannot improve.
Chinese patent application " a kind of one-hot encoding detection method and one-hot encoding detector " (application number: the detection method and the detector that 201510023614) propose a kind of extendible one-hot encoding.But the circuit that this application proposes is complicated, overlength one-hot encoding is detected and there is larger area and the expense of time.
Summary of the invention
The object of the invention is to overcome deficiency of the prior art, a kind of one-hot encoding testing circuit is provided.
One-hot encoding testing circuit of the present invention comprises an input compression module group based on dichotomy and a state detection module.Described input compression module group is made up of multi-stage compression module, and many bit input data compressions are become 2 bit output states; Described state detection module according to 2 bit status that input compression module exports rule out input bit be complete zero, have 1 bit to be 1 or have many bits to be 1.
Input compression module group comprises the multistage input compression module of series connection, and N level input compression module is two N-1 levels input compression modules arranged side by side, N be greater than 1 natural number.
1st grade of input compression module has 4 input ports, 2 output ports; 2nd grade of input compression module has 8 input ports, 4 output ports; By that analogy, N level input compression module has 2
(N+1)individual input port, 2
nindividual output port.
The structure of the 1st grade of input compression module is: comprise two three value and gates, two two inputs or door and ten not gates; An input of the first three value and gate connects the output of first liang of input or door, the output of another two input termination first not gates and the second not gate, the output of the first three value and gate connects the input of the 3rd not gate, and two inputs of first liang of input or door connect the output of the 4th not gate and the output of the 5th not gate respectively; An input of the second three value and gate connects the output of second liang of input or door, the output of another two input termination the 6th not gates and the 7th not gate, the output of the second three value and gate connects the input of the 8th not gate, and two inputs of second liang of input or door connect the output of the 9th not gate and the output of the tenth not gate respectively; The input of the 4th not gate is connected with the input of the 7th not gate, as the first input end of this input compression module; The input of the 5th not gate is connected with the input of the 6th not gate, as the second input of this input compression module; The input of the first not gate is connected with the input of the tenth not gate, as the 3rd input of this input compression module; The input of the second not gate is connected with the input of the 9th not gate, as the four-input terminal of this input compression module; The output of the 3rd not gate and the output of the 8th not gate are as two outputs of this input compression module.The structure of the 2nd grade of input compression module is two the 1st grade input compression module arranged side by side, and its four outputs input compression module respectively four inputs with the 1st grade are connected; By that analogy, most end N level inputs 2 of compression module
(N+1)individual input is as the input of whole one-hot encoding testing circuit.
Described state detection module comprise two two inputs and door, one two input XOR gate and three not gates; First liang of input input connect the output of the 11 not gate and the output of the 12 not gate respectively with two of door, and the output of first liang of input and door connects the input of the 13 not gate; The input, two of the 11 not gate inputs an input of XOR gate, second liang of input connects with an input of door, as an input of state detection module; Another inputs of the input of the 12 not gate, two input XOR gate, second liang of input and door another input and connect, as another input of state detection module; The output of the output of the output of the 13 not gate, two input XOR gate, second liang of input and door, respectively as three outputs of state detection module, is also the output of whole one-hot encoding testing circuit; Two inputs of state detection module connect two outputs of the 1st grade of input compression module respectively.
The present invention uses dichotomy to realize the detection of one-hot encoding, is particularly suitable for the overlength one-hot encoding of bit number more than 1000 and detects.The present invention designs succinctly, saves circuit area, reduces power consumption, also has the advantage of speed.
Accompanying drawing explanation
Fig. 1 is circuit structure schematic diagram;
Fig. 2 is the structural representation of the 1st grade of input compression module in Fig. 1;
Fig. 3 is the structural representation of state detection module in Fig. 1.
Embodiment
As Fig. 1, a kind of one-hot encoding testing circuit comprises an input compression module group C and based on a dichotomy state detection module D.Described input compression module group C is made up of multi-stage compression module, and many bit input data compressions are become 2 bit output states; Described state detection module D according to 2 bit status that input compression module exports rule out input bit be complete zero, have 1 bit to be 1 or have many bits to be 1.
Input compression module group C comprises the multistage input compression module of series connection, and N level input compression module C (N) is arranged side by side two N-1 levels input compression module C (N-1), N be greater than 1 natural number.
1st grade of input compression module C (1) has 4 input ports, 2 output ports; 2nd grade of input compression module C (2) has 8 input ports, 4 output ports; By that analogy, N level input compression module C (N) has 2
(N+1)individual input port, 2
nindividual output port.
As Fig. 2, the structure of the 1st grade of input compression module C (1) is: comprise two three value and gates, two two inputs or door and ten not gates; An input of the first three value and gate 11 connects the output of first liang of input or door 21, the output of another two input termination first not gates 301 and the second not gate 302, the output of the first three value and gate 11 connects the input of the 3rd not gate 303, and two inputs of first liang of input or door 21 connect the output of the 4th not gate 304 and the output of the 5th not gate 305 respectively; An input of the second three value and gate 12 connects the output of second liang of input or door 22, the output of another two input termination the 6th not gates 306 and the 7th not gate 307, the output of the second three value and gate 12 connects the input of the 8th not gate 308, and two inputs of second liang of input or door 22 connect the output of the 9th not gate 309 and the output of the tenth not gate 310 respectively; The input of the 4th not gate 304 is connected with the input of the 7th not gate 307, as the first input end of this input compression module; The input of the 5th not gate 305 is connected with the input of the 6th not gate 306, as the second input of this input compression module; The input of the first not gate 301 is connected with the input of the tenth not gate 310, as the 3rd input of this input compression module; The input of the second not gate 302 is connected with the input of the 9th not gate 309, as the four-input terminal of this input compression module; The output of the 3rd not gate 303 and the output of the 8th not gate 308 are as two outputs of this input compression module.
The structure of the 2nd grade of input compression module C (2) is two the 1st grade input compression module C (1) arranged side by side, and its four outputs input compression module C (1) respectively four inputs with the 1st grade are connected; By that analogy, most final stage input compression module C (N) 2
(N+1)individual input is as the input of whole one-hot encoding testing circuit.
As Fig. 3, state detection module D comprise two two inputs and door, one two input XOR gate and three not gates; First liang of input input connect the output of the 11 not gate 311 and the output of the 12 not gate 312 respectively with two of door 41, and the output of first liang of input and door 41 connects the input of the 13 not gate 313; The input, two of the 11 not gate 311 inputs an input of XOR gate 51, second liang of input connects with an input of door 42, as an input of state detection module; Another inputs of the input of the 12 not gate 312, two input XOR gate 51, second liang of input and door 42 another input and connect, as another input of state detection module; The output d3 of the output d2 of the output d1 of the 13 not gate 313, two input XOR gate 51, second liang of input and door 42, as three outputs of state detection module, is also the output of whole one-hot encoding testing circuit; Two inputs of state detection module connect two outputs of the 1st grade of input compression module respectively.
When the bit number K of input one-hot encoding testing circuit is greater than 2
n, and be less than 2
(N+1)time, then input increase by 2
(N+1)the zero-signal of-K bit, the bit number of the final process of order is 2
(N+1), N be greater than 1 natural number.
When the bit number K of input one-hot encoding testing circuit equals 2
(N+1)time, be 2 by an input bit number
(N+1)input compression module group export 2 bits, 2 bits of input compression module group export the detection module that gets the hang of.
Be described for the one-hot encoding testing circuit of 7 bits below.Because 2
2< 7 < 2
(2+1), so get N=2.By 0 of the one-hot encoding of 7 bits input increase by 1 bit, form the one-hot encoding input of 8 bits.Because one-hot encoding increases the number that 0 of any bit can not change 1 of one-hot encoding.So the input increasing 0 of any bit can not change the output of one-hot encoding testing circuit.Input bit number be 8 input compression module be made up of C (2) and the C (1) of cascade.Input bit number is that 2 bits of the input compression module of 8 export the input being connected to state detection module.The output of state detection module is the output of the one-hot encoding testing circuit of 7 bits.When the one-hot encoding of input 7 bit is full 0, one-hot encoding testing circuit exports as d1=1, d2=0, d3=0, and judgement input coding bit is complete zero; When the one-hot encoding of input 7 bit has and only has 1 bit to be 1, one-hot encoding testing circuit exports as d1=0, d2=1, d3=0, and judgement input coding bit is 1 for there being 1 bit; When to have more than 1 bit be 1 for the one-hot encoding of input 7 bit, one-hot encoding testing circuit exports as d1=0, d2=0, d3=1, and judgement input coding is 1 than peculiar many bits.Namely the function of the one-hot encoding testing circuit of 7 bits is completed.
This understanding be above-mentioned example just to explanation of the present invention, instead of limitation of the present invention, any innovation and creation do not exceeded in spirit of the present invention, all fall within protection scope of the present invention.
Claims (2)
1. an one-hot encoding testing circuit, comprises an input compression module group based on dichotomy and a state detection module; It is characterized in that: described input compression module group is made up of multi-stage compression module, many bit input data compressions are become 2 bit output states; Described state detection module according to 2 bit status that input compression module exports rule out input bit be complete zero, have 1 bit to be 1 or have many bits to be 1;
Input compression module group comprises the multistage input compression module of series connection, and N level input compression module is two N-1 levels input compression modules arranged side by side, N be greater than 1 natural number;
1st grade of input compression module has 4 input ports, 2 output ports; 2nd grade of input compression module has 8 input ports, 4 output ports; By that analogy, N level input compression module has 2
(N+1)individual input port, 2
nindividual output port;
The structure of the 1st grade of input compression module is: comprise two three value and gates, two two inputs or door and ten not gates; An input of the first three value and gate (11) connects the output of first liang of input or door (21), the output of another two inputs termination first not gate (301) and the second not gate (302), the output of the first three value and gate (11) connects the input of the 3rd not gate (303), and two inputs of first liang of input or door (21) connect the output of the 4th not gate (304) and the output of the 5th not gate (305) respectively; An input of the second three value and gate (12) connects the output of second liang of input or door (22), the output of another two inputs termination the 6th not gate (306) and the 7th not gate (307), the output of the second three value and gate (12) connects the input of the 8th not gate (308), and two inputs of second liang of input or door (22) connect the output of the 9th not gate (309) and the output of the tenth not gate (310) respectively; The input of the 4th not gate (304) is connected, as the first input end of this input compression module with the input of the 7th not gate (307); The input of the 5th not gate (305) is connected with the input of the 6th not gate (306), as the second input of this input compression module; The input of the first not gate (301) is connected with the input of the tenth not gate (310), as the 3rd input of this input compression module; The input of the second not gate (302) is connected, as the four-input terminal of this input compression module with the input of the 9th not gate (309); The output of the 3rd not gate (303) and the output of the 8th not gate (308) are as two outputs of this input compression module;
The structure of the 2nd grade of input compression module is two the 1st grade input compression module arranged side by side, and its four outputs input compression module respectively four inputs with the 1st grade are connected; By that analogy, most end N level inputs 2 of compression module
(N+1)individual input is as the input of whole one-hot encoding testing circuit;
Described state detection module comprise two two inputs and door, one two input XOR gate and three not gates; First liang of input input connect the output of the 11 not gate (311) and the output of the 12 not gate (312) respectively with two of door (41), and the output of first liang of input and door (41) connects the input of the 13 not gate (313); The input, two of the 11 not gate (311) inputs an input of XOR gate (51), second liang of input connects with an input of door (42), as an input of state detection module; Another inputs of the input of the 12 not gate (312), two inputs XOR gate (51), second liang of input and door (42) another input and connect, as another input of state detection module; The output of the output of the output of the 13 not gate (313), two inputs XOR gate (51), second liang of input and door (42), respectively as three outputs of state detection module, is also the output of whole one-hot encoding testing circuit; Two inputs of state detection module connect two outputs of the 1st grade of input compression module respectively.
2. a kind of one-hot encoding testing circuit as claimed in claim 1, is characterized in that: when the bit number K of the described one-hot encoding testing circuit of input is greater than 2
n, and be less than 2
(N+1)time, then input increase by 2
(N+1)the zero-signal of-K bit, the bit number of the final process of order is 2
(N+1), N be greater than 1 natural number;
When the bit number K of the described one-hot encoding testing circuit of input equals 2
(N+1)time, be 2 by an input bit number
(N+1)input compression module group export 2 bits, 2 bits of input compression module group export the detection module that gets the hang of.
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