CN105047578A - Method for evaluating transistor - Google Patents
Method for evaluating transistor Download PDFInfo
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- CN105047578A CN105047578A CN201510424012.1A CN201510424012A CN105047578A CN 105047578 A CN105047578 A CN 105047578A CN 201510424012 A CN201510424012 A CN 201510424012A CN 105047578 A CN105047578 A CN 105047578A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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Abstract
The invention discloses a method for evaluating a transistor. The method comprises the following steps: applying a first pulse signal of which the cycle is T to the first end of the transistor; after at least n cycles, carrying out electric performance testing on the transistor to obtain a first parameter, wherein n is a positive integer which is greater than or equal to 1; and comparing an initial parameter of the transistor with the first parameter to evaluate the reliability of the transistor. According to the method, the reliability of the transistor can be rapidly evaluated; the process development cycle is shortened; and the reliability monitoring on each transistor wafer in the mass production process is realized.
Description
Technical field
The present invention relates to semiconductor technology, particularly relate to a kind of appraisal procedure of transistor.
Background technology
Transistor is a kind of semiconductor device, in the switching circuit being widely used in integrated circuit and amplifying circuit.Along with the sustainable development of integrated circuit technique, chip requires speed faster, also has higher requirement to the performance of transistor in chip so accordingly.Based on the raising of transistor performance, in the process exploitation and volume production process of transistor, need to continue to monitor and reliability testing to it, to ensure to produce qualified transistor.
In prior art, transistor reliability test event mainly comprises hot carrier (hotcarrierinjection, HCI) test, reliability of the gate oxide (GateOxideIntegrity, GOI) test, time correlation dielectric breakdown (timedependentdielectricbreakdown, TDDB) is tested, threshold voltage stability (Vtstability) test etc.In the process exploitation process of transistor, only have reliability testing project all to test and pass through, could illustrate that this technique can enter the volume production stage.But in prior art, to the time that the reliability testing project of transistor needs cost very long, very large for process exploitation cycle influences.
And after transistor enters the volume production stage, need regularly sampling to carry out reliability testing to monitor the stability of production line, because the testing time is longer, existing method for testing reliability can not fast reaction production line state, when pinpointing the problems, a lot of product may be had to miss the stop.In addition, existing method of testing is sample testing, and cannot monitor the reliability of each sheet transistor wafer, can only react continuous print variation long-term on production line, if there is random variation, be difficult to monitoring.
Summary of the invention
In view of this, the invention provides a kind of appraisal procedure of transistor, the reliability of transistor can be assessed fast, shorten the process exploitation cycle.
The invention provides a kind of appraisal procedure of transistor, comprising:
It is the first end that first pulse signal of T is applied to described transistor by the cycle;
After at least n cycle, electric performance test is carried out to described transistor, to obtain the first parameter, wherein, n be more than or equal to 1 positive integer;
Compare according to the initial parameter of described transistor and described first parameter, to assess the reliability of described transistor.
Further, the first end of described transistor is grid or the drain electrode of described transistor.
Further, the appraisal procedure of described transistor also comprises:
It is the second end that second pulse signal of T is applied to described transistor by the cycle;
After at least n cycle, electric performance test is carried out to described transistor, to obtain the second parameter, wherein, n be more than or equal to 1 positive integer;
Compare according to the initial parameter of described transistor and described second parameter, to assess the reliability of described transistor.
Further, the second end of described transistor is drain electrode or the grid of described transistor.
Further, the periodic width of described T is pulse width T 1 and space width T2.
Further, the periodic width of described T also comprises rising edge width T3 and trailing edge width T4.
Further, described pulse width T 1 is identical with described space width T2; Described rising edge width T3 is identical with described trailing edge width T4.
Further, described n is specially: the total degree that specified standard transistor carries out out in length of life/breaks.
The appraisal procedure of a kind of transistor provided by the invention, it is the first end that first pulse signal of T is applied to transistor by the cycle, after at least n cycle, electric performance test is carried out to transistor, to obtain the first parameter, the initial parameter of the first parameter and transistor is compared, according to the reliability of comparative result assessment transistor.The present invention can assess the reliability of transistor fast, shortens the process exploitation cycle, realizes carrying out reliability monitoring to each transistor wafer in volume production process.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is the flow chart of the appraisal procedure of a kind of transistor that the embodiment of the present invention one provides;
Fig. 2 (a) is the first pulse signal waveform figure that the embodiment of the present invention one provides;
Fig. 2 (b) is oscillogram when comprising 3 regular square-wave signals in the first pulse signal one-period of providing of the embodiment of the present invention one;
Fig. 3 (a) is the structure chart of the N-type transistor that the embodiment of the present invention one provides;
Fig. 3 (b) is the structural representation of the N-type transistor conducting state that the embodiment of the present invention one provides;
Fig. 3 (c) is the drain electrode of the N-type transistor that the embodiment of the present invention one provides view when adding the first pulse signal;
Fig. 4 is the flow chart of the appraisal procedure of a kind of transistor that the embodiment of the present invention two provides;
Fig. 5 (a) be the embodiment of the present invention two provide the first be applied to the oscillogram of the pulse signal on transistor;
Fig. 5 (b) is the oscillogram that the second that the embodiment of the present invention two provides is applied to the pulse signal on transistor;
Fig. 5 (c) be the embodiment of the present invention two provide the third be applied to the oscillogram of the pulse signal on transistor.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not full content.
Embodiment one
The appraisal procedure flow chart of a kind of transistor that Fig. 1 provides for the present embodiment one, as shown in Figure 1, described method comprises:
Step 101: be the first end that first pulse signal of T is applied to described transistor by the cycle;
In the present embodiment, as shown in Fig. 2 (a), the periodic width of described T is pulse width T 1 and space width T2; The periodic width of described T also comprises rising edge width T3 and trailing edge width T4, and wherein, described pulse width T 1 is identical with described space width T2; Described rising edge width T3 is identical with described trailing edge width T4.
In the present embodiment, described pulse width T 1 and described space width T2 are all preferably 1ms; Described rising edge width T3 and described trailing edge width T4 is all preferably 2 μ s; The high level of described first pulse signal is 1 ~ 1.2 times of the first end normal working voltage of described transistor.Wherein, the pulse width T 1 of described first pulse signal and space width T2 can arrange other width; Described rising edge width T3 and described trailing edge width T4 also can arrange other width.In one-period T, the magnitude of voltage of the high level of described first pulse signal can change in time; First pulse signal of described one-period can have multiple rule or irregular pulse signal, such as, as shown in Fig. 2 (b), comprises 3 regular square-wave signals in the first pulse signal one-period.
In the present embodiment, the first end arranging described transistor is the grid of described transistor.
Step 102: after at least n cycle, electric performance test is carried out to described transistor, to obtain the first parameter, wherein, n be more than or equal to 1 positive integer.
In the present embodiment, illustrate, Fig. 3 (a) is N-type transistor structure chart.As shown in Fig. 3 (a), be the grid 300 that first pulse signal of T is applied to transistor by the cycle.
When the first pulse signal is high level, source electrode 303 voltage and drain electrode 302 voltages are respectively 0V.As shown in Fig. 3 (b), after applying the first pulse signal of high level, electric field is formed in gate oxide 301 in transistor, few son (electronics) in P district 304 is gathered the surface in P district 304, make to form conducting channel, now transistor turns between the first N type semiconductor 305 and the second N type semiconductor 306.
When the first pulse signal is low level, in the gate oxide 301 of transistor, do not form electric field, between the source electrode 303 of transistor and drain electrode 302, do not form conducting channel, transistor cutoff.
In sum, within 1 cycle T time, transistor is in conducting state and cut-off state is each once.When the first pulse signal high level, along with the increase of pulse signal cycle number of times, if there is the defects such as cavity, crack, impurity in gate oxide 301, the pulse signal of long-time multicycle number of times is applied to grid 300, the defect of gate oxide 301 may cause the situations such as transistor gas discharge, electrothermal decomposition, gate oxide 301 even may be caused to puncture, damage transistor.
Puncturing principle is particularly, when the high level applied at the grid 300 of transistor, if the electric field strength in gate oxide 301 is lower than the intrinsic breakdown electric field strength of gate oxide 301, although the high level that so pulsatile once signal applies is not enough to the intrinsic breakdown causing gate oxide 301, but along with the increase of high level number of times in pulse signal, produce in gate oxide 301 and gather the cause of defect, certainly can puncture after certain hour.
Therefore the present invention is by applying the performance of the first pulse signal detection gate oxide 301 at the first end of transistor.
Step 103: compare, to assess the reliability of described transistor according to the initial parameter of described transistor and described first parameter.
When transistor dispatches from the factory, producer needs to dispatch from the factory test to the initial electrical performance parameter of transistor, in this default initial electrical performance parameter threshold scope, only has the initial electrical performance parameter of transistor within the scope of initial electrical performance parameter threshold, this transistor is just qualified spendable transistor, otherwise transistor is substandard products can not use.In the present embodiment, the initial electrical performance parameter arranging qualified spendable transistor is the initial parameter of transistor.
When assessing the reliability of transistor, user can according to the initial parameter threshold value of self-demand sets itself transistor, and the initial parameter threshold value of the transistor of different user setting may be different.The initial parameter threshold range of setting current transistor is in the scope from first threshold to Second Threshold, the first pulse signal is applied at the first end of this transistor, reliability assessment is carried out to transistor, obtains the first parameter, the first parameter and initial parameter are compared.Time within the scope that the first parameter is in first threshold and Second Threshold, then judge that the reliability of this transistor is high and effectively, time outside the scope that the first parameter is in first threshold and Second Threshold, then this transistor reliability is low and invalid.
In the present embodiment, described n is specially: the total degree that specified standard transistor carries out out in length of life/breaks; Namely at n all after date, transistor turns and each n time of cut-off.
As shown in Fig. 3 (a) He 3 (b), it is more than 100,000 times that usual standard N-type transistor need reach out/break number of times in length of life, i.e. 100,000 conductings and cut-off number of times, first pulse signal in 100,000 cycles is then applied above at the grid 300 of transistor, make transistor turns and cut-off number of times respectively more than 100,000 times, then carry out electric performance test.Such as threshold voltage test is carried out to transistor, obtain the threshold voltage of transistor.If the threshold voltage of transistor is compared with initial threshold voltage, in the threshold range that initial threshold voltage is preset, then gate oxide 301 is functional, and this transistor is effective; If the threshold voltage obtained is outside initial threshold voltage preset threshold range, then gate oxide 301 may puncture, and this transistor performance is poor, may lose efficacy during use.
Wherein, a cycle time of the first pulse signal is very short, and what be therefore applied above first pulse signal in 100,000 cycles is about 3.3 minutes total time, is applying the first pulse signal and can carry out the test of threshold voltage.Complete the reliability assessment of transistor gate oxide by this method, save a large amount of time and manpower, shorten the process exploitation cycle.
On the basis of above-described embodiment, the first end that can also arrange described transistor is drain electrode 302, and the performance of test transistor drain electrode 302.As shown in Fig. 3 (c), it is the drain electrode 302 that first pulse signal of T is applied to transistor by the cycle, when the first pulse signal is high level, (filled arrows is external electrical field direction to there is voltage between drain electrode 302 and source electrode 303, hollow arrow is internal electric field direction), the first PN junction A between drain electrode 302 and source electrode 303 and the second PN junction B is that be in positively biased with reverse-biased state respectively, so drain current is close to 0; Along with the increase being applied to the first pulse signal number of times in drain electrode 302, because of the existence of defect in the first PN junction A and the second PN junction B, can punch-through be produced, cause the damage of transistor.
As shown in Fig. 3 (c), if be applied above first pulse signal in 100,000 cycles at transistor drain, then the first PN junction A of transistor and the second PN junction B is in the number of times of the state of forward-biased and reverse-biased respectively more than 100,000 times, then carries out electric performance test.Such as, leakage current is tested, if the leakage current obtained is compared with initial leakage current (close to 0), the leakage current obtained is in the threshold range that initial leakage current is preset, then the PN junction of transistor is of good performance, and this transistor is effective, otherwise, transistor PN junction punctures, and this transistor is invalid.So, by applying the method for periodic first pulse signal in the drain electrode of transistor, the reliability of transistor PN junction can be assessed.
On the basis of above-described embodiment, the first end of described transistor can be also source electrode or substrate, to the test that the performance of transistor is correlated with.
Embodiments provide a kind of appraisal procedure of transistor, cycle is the first end that first pulse signal of T is applied to transistor by the method, after at least n cycle, electric performance test is carried out to transistor, to obtain the first parameter, the initial parameter of the first parameter and transistor is compared, according to the comparative result assessment gate oxide of transistor and the reliability of PN junction; The embodiment of the present invention can assess the reliability of transistor fast, shortens the process exploitation cycle, realizes carrying out reliability monitoring to each transistor wafer in volume production process.
Embodiment two
The appraisal procedure of a kind of transistor that Fig. 4 provides for the present embodiment two, on the basis of above-described embodiment, adding the cycle is the step that second pulse signal of T is applied to the second end of described transistor, and accordingly, as shown in Figure 4, described method comprises:
Step 401: be the first end that first pulse signal of T is applied to described transistor by the cycle; It is the second end that second pulse signal of T is applied to described transistor by the cycle.
In the present embodiment, the first end of described transistor is grid or the drain electrode of described transistor, and accordingly, the second end of described transistor is drain electrode or the grid of described transistor.Described first pulse signal is identical with the cycle of the second pulse signal; Described second pulse signal advanced first pulse signal (m+1/2) the individual cycle, wherein m be more than or equal to 1 integer.As shown in Fig. 5 (a), when described second pulse signal 2 advanced first pulse signal 1, the end time of described second pulse duration is overlapping with the initial time of the first pulse duration.
Wherein, the pulse width T 1 of described first pulse signal and space width T2 are all preferably 1ms; The rising edge width T3 of the first pulse signal and described trailing edge width T4 is all preferably 2 μ s; The pulse width T 1 of described second pulse signal and described space width T2 are all preferably 1ms; The rising edge width T3 of described second pulse signal and described trailing edge width T4 is all preferably 2 μ s.Described first pulse signal and the second end pulse signal high level be respectively the first end of described transistor and 1 ~ 1.2 times of the second end normal working voltage.Pulse width T 1 and the space width T2 of described first pulse signal can be set to other width, and accordingly, the pulse width T 1 of described second pulse signal and described space width T2 can be set to other width.The rising edge width T3 of described first pulse signal and described trailing edge width T4 can be set to other width, and accordingly, the rising edge width T3 of described second pulse signal and described trailing edge width T4 can be set to other width.
On the basis of above-described embodiment, the second described pulse signal can also be preferably delayed first pulse signal, as shown in Fig. 5 (b), when described second pulse signal 2 delayed first pulse signal 1, the pulse duration initial time of described second pulse signal is overlapping with the pulse duration end time of described first pulse signal (when that is the first pulse signal is high level, the second pulse signal is low level).
On the basis of above-described embodiment, as shown in Fig. 5 (c), the second described pulse signal 2 can also be preferably overlapping with the first pulse signal 1.
Step 402: at the first pulse signal applied after at least n cycle, electric performance test is carried out to described transistor, to obtain the first parameter, wherein, n be more than or equal to 1 positive integer.
Step 403: compare, to assess the reliability of described transistor according to described transistor initial parameter and described first parameter.
Step 404: at the second pulse signal applied after at least n cycle, electric performance test is carried out to described transistor, to obtain the second parameter, wherein, n be more than or equal to 1 positive integer.
Step 405: compare, to assess the reliability of described transistor according to the initial parameter of described transistor and described second parameter.
In the reliability testing of transistor, hot carrier (HCI) can also be adopted to test and time correlation dielectric breakdown (TDDB) test.Wherein, the test of HCI mainly comprises DC stress method.DC stress method is the life-span being obtained transistor by the method for accelerated life test, concrete method is exactly in the grid of transistor and source electrode, drain electrode and source electrode and the DC voltage stress applying a period of time between source electrode and drain electrode, this stress is generally greater than the voltage under its normal work, make the degradation values that the monitoring parameter of transistor reaches predetermined, to measure under some stress voltages corresponding annealing time, utilize the method for extrapolation to infer the life-span under its normal operation condition.Wherein, apply at grid and source electrode the reliability that DC voltage stress can test gate oxide, drain electrode and source electrode and apply DC voltage stress between source electrode and drain electrode can the performance of PN junction in test transistor.
Time correlation dielectric breakdown (TDDB) test is a kind of main quality of gate oxide evaluating method, and concrete grammar is on grid, apply constant voltage, makes transistor be in accumulated state.Through after a period of time, gate oxide will puncture, and by actual measurement charge to breakdown, breakdown time etc., a large amount of data statistics distribution characterized the quality of gate oxide, and was predicted the life-span of gate oxide by it.
In the present embodiment, when the first end of transistor is grid or drain electrode, when second end of transistor is for drain electrode or grid, apply the first pulse signal and the second pulse signal respectively at the first end of transistor and the second end simultaneously, can realize the gate oxide of transistor and the test of PN junction characteristic and assessment.The present embodiment can assess the reliability of transistor fast, shortens the process exploitation cycle.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.
Claims (8)
1. an appraisal procedure for transistor, is characterized in that, comprising:
It is the first end that first pulse signal of T is applied to described transistor by the cycle;
After at least n cycle, electric performance test is carried out to described transistor, to obtain the first parameter, wherein, n be more than or equal to 1 positive integer;
Compare according to the initial parameter of described transistor and described first parameter, to assess the reliability of described transistor.
2. appraisal procedure according to claim 1, is characterized in that, the first end of described transistor is grid or the drain electrode of described transistor.
3. appraisal procedure according to claim 2, is characterized in that, the appraisal procedure of described transistor also comprises:
It is the second end that second pulse signal of T is applied to described transistor by the cycle;
After at least n cycle, electric performance test is carried out to described transistor, to obtain the second parameter, wherein, n be more than or equal to 1 positive integer;
Compare according to the initial parameter of described transistor and described second parameter, to assess the reliability of described transistor.
4. appraisal procedure according to claim 3, is characterized in that, the second end of described transistor is drain electrode or grid.
5. the appraisal procedure according to claim 1 or 3, is characterized in that, the periodic width of described T is pulse width T 1 and space width T2.
6. appraisal procedure according to claim 5, is characterized in that, the periodic width of described T also comprises rising edge width T3 and trailing edge width T4.
7. appraisal procedure according to claim 6, is characterized in that, described pulse width T 1 is identical with described space width T2; Described rising edge width T3 is identical with described trailing edge width T4.
8. the appraisal procedure according to claim 1 or 3, is characterized in that, described n is specially: the total degree that specified standard transistor carries out out in length of life/breaks.
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Cited By (1)
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| CN107369632A (en) * | 2017-07-12 | 2017-11-21 | 欧阳慧琳 | A kind of method for testing reliability and system of unencapsulated power device chip |
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| CN1306303A (en) * | 2001-02-28 | 2001-08-01 | 山东大学 | Steady-state service life test method by controlling junction temp of transistor |
| US20080186048A1 (en) * | 2005-12-14 | 2008-08-07 | Alpha & Omega Semiconductor, Ltd | Configurations and method for carrying out wafer level unclamped inductive switching (UIS) tests |
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