CN105047530A - 一种制备Si基碲镉汞芯片位错观察样品的衬底腐蚀工艺 - Google Patents

一种制备Si基碲镉汞芯片位错观察样品的衬底腐蚀工艺 Download PDF

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CN105047530A
CN105047530A CN201510295709.3A CN201510295709A CN105047530A CN 105047530 A CN105047530 A CN 105047530A CN 201510295709 A CN201510295709 A CN 201510295709A CN 105047530 A CN105047530 A CN 105047530A
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substrate
chip
hgcdte
dislocation
cadmium telluride
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张姗
林春
廖清君
胡晓宁
叶振华
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Shanghai Institute of Technical Physics of CAS
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Abstract

本发明公开了一种制备Si基碲镉汞芯片位错观察样品的衬底腐蚀工艺。工艺包括探测器芯片的衬底减薄抛光和清洗、芯片保护、衬底氧化层腐蚀、衬底选择性湿法腐蚀四个步骤，本发明的特征在于：将化学机械减薄抛光后的Si基碲镉汞芯片衬底朝上贴于宝石片上并固化，将制好的样品放入氢氟酸中去氧化层，再将其放入高选择比腐蚀液中进行腐蚀。本发明的特点在于：能获得衬底完全去除的碲化镉/碲镉汞外延薄膜材料和光亮的碲化镉界面，为从碲化镉界面入手研究探测器芯片中位错提供了方便。

Description

一种制备Si基碲镉汞芯片位错观察样品的衬底腐蚀工艺
技术领域
本发明涉及半导体芯片衬底选择腐蚀工艺，具体是指一种用于制备Si基碲镉汞芯片位错观察样品的衬底腐蚀工艺。
背景技术
Si基HgCdTe(碲镉汞)探测器是第三代红外焦平面探测器发展的主流之一。依托于成熟的Si晶元制备工艺和分子束外延生长工艺的发展，Si基HgCdTe材料具备更大的使用面积、更高平整度和较高机械强度，从而能够制备出超大像素规模，超高分辨率、更远探测距离的红外探测器，并提高了探测器的成品率降低了成本。除此之外，Si基HgCdTe材料还具有与Si电路相似的热膨胀系数，避免了高低温循环过程中因形变差异造成的铟柱脱开，提高了器件的可靠性。
由于衬底Si和外延层HgCdTe之间具有较大的晶格失配(-19％)和热失配，会使材料在生长和应用的过程中产生大量的失配位错，因此Si基HgCdTe探测器制备最大的挑战在于低位错密度的HgCdTe外延材料的生长和如何抑制位错对器件性能的影响。为了减少Si基HgCdTe材料中的失配位错往往在HgCdTe生长之前生长一层6～10μm的CdTe缓冲层，再通过退火等方法减少CdTe缓冲层中位错，进而减少HgCdTe外延薄膜中位错密度。研究CdTe缓冲层与HgCdTe外延层中位错的产生原因、位置和产生湮灭过程对于降低材料的位错密度非常重要，特别是对于长波Si基HgCdTe材料。通常对HgCdTe材料中位错的分析都是从HgCdTe表面一侧，通过位错腐蚀液进行逐层腐蚀，对位错密度、位置、形状进行逐层分析，但当器件已经加工成型后，研究位错对器件性能的影响或研究器件工艺对HgCdTe芯片中位错的影响时，从HgCdTe界面进行分析就存在困难。本发明针对这一问题，提供了一种衬底腐蚀工艺，通过衬底的去除，能够获得完整的外延薄膜材料和清晰的观察界面，为从缓冲层CdTe界面入手对芯片位错进行观察提供了很好的工艺手段。
发明内容
本发明的目的在于保证HgCdTe芯片特性稳定的基础上，提供一种高选择性、低损伤的Si衬底腐蚀方法，获得衬底完全去除的CdTe/HgCdTe薄膜样品，从而为Si基HgCdTe芯片材料中位错的研究提供有效工艺手段。
本发明的腐蚀工艺步骤如下：
(1)探测器芯片的衬底减薄抛光和清洗：将Si基碲镉汞芯片衬底减薄抛光至50um，依次利用有机溶剂(三氯乙烯、乙醚、丙酮、酒精)将芯片表面、背面清洗干净。
(2)芯片保护：利用环氧树脂将芯片衬底向上贴于宝石片上，充分固化。
(3)衬底氧化层腐蚀：将贴于宝石片的Si基碲镉汞芯片放于HF酸中腐蚀，去掉衬底表面氧化层，取出后置于去离子水中冲洗。
(4)衬底选择性湿法腐蚀：将贴于宝石片的Si基碲镉汞芯片放入高选择性Si晶体腐蚀液中进行腐蚀，衬底完全去除后取出用氮气吹干。
所述的高选择性Si晶体腐蚀液为四甲基氢氧化铵、去离子水和过硫酸铵的混合腐蚀液。
此时再将衬底去除的CdTe/HgCdTe薄膜芯片放入位错腐蚀液中进行腐蚀观察即可得到不同深度和不同位置处的位错信息。
本发明的优点在于：
能获得衬底完全去除的CdTe/HgCdTe外延薄膜材料和光亮的CdTe界面，为从CdTe界面入手研究探测器芯片中位错提供了方便。
附图说明
图1为衬底部分去除后材料的EDAX测试结果。图(1)为衬底去除位置的EDAX测试结果；图(2)为衬底残留位置的EDAX测试结果。
图2为衬底完全去除后材料表面的EDAX测试结果。
图3为位错腐蚀后CdTe界面的位错显微镜照片。
图4本发明使用工艺流程图。
具体实施方式
下面结合附图，对本发明的具体工艺步骤作进一步的详细说明。
(1)将Si基HgCdTe芯片衬底朝上利用石蜡固定在玻璃板上，利用化学机械减薄抛光设备和粒径分别为9μm、3μm的Al2O3抛光液，将Si基HgCdTe芯片衬底初步磨抛至50um后从玻璃盘上取下，室温下利用有机溶剂(三氯乙烯、乙醚、丙酮、酒精)浸泡5min，再将芯片表面、背面清洗干净。
(2)利用环氧树脂将芯片衬底向上贴于宝石片上，衬底背面露出，65℃温度下固化24小时。
(3)利用浓度为25％的TMAH(四甲基氢氧化铵)溶液和去离子水H2O按照2：3的比例配制成浓度为10％的腐蚀液，根据体积加入2g/l的APODS(过硫酸铵)，放在温度90℃的水浴中加热一小时。
(4)将保护好的样品放于HF酸中腐蚀5s，去掉衬底表面氧化层，取出后置于去离子水中冲洗。
(5)将样品迅速放入60℃的腐蚀液中进行腐蚀；此时会有大量气泡从衬底表面产生并脱离衬底表面，表明反应开始。
(6)当用肉眼观察衬底完全去除后将芯片置于去离子水中清洗并取出，用氮气吹干，并利用显微镜观察芯片表面，露出光亮的银灰色碲化镉表面说明衬底已完全去除，利用EDAX测试验证了衬底的完全去除。图1为衬底部分去除后材料的EDAX测试结果。通过对比两个位置处的成分可知，位置(2)处的Si衬底被腐蚀后露出了位置(1)的CdTe缓冲层。图2为衬底完全去除后材料的EDAX测试结果，可以看出衬底腐蚀后CdTe表面光亮，可见此腐蚀液能够完全去除Si衬底且对CdTe具有很好的选择性。此时将衬底去除的CdTe/HgCdTe薄膜样品利用位错腐蚀液进行腐蚀，通过观察即可统计得到不同深度和位置处的位错信息，如图3所示。

Claims (1)

1.一种制备Si基碲镉汞芯片位错观察样品的衬底腐蚀工艺，其特征在于包括以下步骤：
1)探测器芯片的衬底减薄抛光和清洗：将Si基碲镉汞芯片衬底减薄抛光至50um，依次利用三氯乙烯、乙醚、丙酮和酒精将芯片表面、背面清洗干净；
2)芯片保护：利用环氧树脂将芯片衬底向上贴于宝石片上，充分固化；
3)衬底氧化层腐蚀：将贴于宝石片的Si基碲镉汞芯片放于HF酸中腐蚀，去掉衬底表面氧化层，取出后置于去离子水中冲洗；
4)衬底选择性湿法腐蚀：将贴于宝石片的Si基碲镉汞芯片放入高选择性Si晶体腐蚀液中进行腐蚀，衬底完全去除后取出用氮气吹干。
CN201510295709.3A 2015-06-02 2015-06-02 一种制备Si基碲镉汞芯片位错观察样品的衬底腐蚀工艺 Pending CN105047530A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
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CN109142793A (zh) * 2018-09-25 2019-01-04 天津大学 一种焊接接头界面微结构的无损可视化检测方法
CN111180361A (zh) * 2019-12-13 2020-05-19 贵州航天计量测试技术研究所 一种塑封器件湿法开封方法

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CN103413863A (zh) * 2013-07-30 2013-11-27 中国科学院上海技术物理研究所 一种延伸波长的平面型铟镓砷红外探测器芯片制备方法
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US4436580A (en) * 1983-08-12 1984-03-13 The United States Of America As Represented By The Secretary Of The Army Method of preparing a mercury cadium telluride substrate for passivation and processing
CN1563493A (zh) * 2004-03-18 2005-01-12 中国科学院上海技术物理研究所 用于硅腐蚀的四甲基氢氧化铵腐蚀液及制备方法
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109142793A (zh) * 2018-09-25 2019-01-04 天津大学 一种焊接接头界面微结构的无损可视化检测方法
CN111180361A (zh) * 2019-12-13 2020-05-19 贵州航天计量测试技术研究所 一种塑封器件湿法开封方法

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