CN105045647B - Emulator supporting NVM rapid page programming - Google Patents
Emulator supporting NVM rapid page programming Download PDFInfo
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- CN105045647B CN105045647B CN201410751684.9A CN201410751684A CN105045647B CN 105045647 B CN105045647 B CN 105045647B CN 201410751684 A CN201410751684 A CN 201410751684A CN 105045647 B CN105045647 B CN 105045647B
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Abstract
The invention introduces an emulator supporting NVM (non-volatile memory) fast page programming, and relates to the technical field of chip emulation. The simulator comprises a simulator control module and a chip simulation module. When the simulator is in a program downloading state, the NVM control module in the chip simulation module is in a fast page programming mode, so that the fast downloading of the program is realized; when the simulator is in a program debugging state, the page programming time parameter of the NVM control module can be set through the simulator control module for the debugging evaluation program to use; when the simulator is in a program running state, the NVM control module in the chip simulation module is in a chip simulation normal page programming mode, and the page programming function of the NVM control module is consistent with that of the NVM page in a real chip. The simulator of the invention can ensure that the NVM page programming function is correct when a user runs a program, and can also ensure that NVM data can be quickly written when the user downloads the program. The invention has the characteristics of fast downloading the program and improving the debugging efficiency of the program.
Description
Technical Field
The invention relates to a chip emulator, in particular to an emulator supporting NVM fast page programming, and the NVM is specially referred to as a non-volatile memory such as F L ASH or EEPROM.
Background
The medium for storing programs on the simulator comprises RAM and NVM (including EEPROM, F L ASH and the like), and the single byte reading and writing or page programming corresponding to different storage media are greatly different and are different from nanosecond level to millisecond level.
For a processor chip with an NVM storage medium, the NVM characteristics generally adopt a page erase/write method. Depending on the characteristics of the NVM, the page size may be defined as 64/128/256/512 bytes, etc. Depending on the different page sizes, page programming is between a few milliseconds to tens of milliseconds. When a user needs to debug a written program, the compiled MEM file needs to be downloaded to a target memory, and then the debugging and running of the program is started. For program downloading of the NVM, the program downloading of the NVM is completed by executing a page programming program of the NVM in chip emulation and by page loop programming.
Most of the integrated development environments used by users support the F L ASH programming algorithm function, programs compiled by users can be downloaded through the function, after the users debug and modify the programs, the programs need to be recompiled, NVM data downloading is carried out through the F L ASH programming algorithm, and then the programs are debugged.
Based on the current NVM program downloading and debugging mode, the user first finishes downloading the program and then performs program debugging. For NVM programs of several kilobytes (K Bytes) of capacity, the download time is small and not noticeable to the user. If the program capacity is above megabytes (M Bytes), the NVM program download time is long and noticeable to the user. Especially, in the initial stage of user program development, the frequency of modifying program and downloading program is relatively high, if the downloading time of NVM program with large capacity can be reduced, the debugging efficiency of user program can be improved.
Disclosure of Invention
The invention solves the technical problem of designing an emulator supporting NVM fast page programming.
In order to achieve the above technical problem, the simulator of the present invention includes a simulator control module and a chip simulation module. The chip simulation module mainly comprises an NVM control module, a time parameter register and a storage medium; the simulator control module enables the NVM control module in the simulation chip module to be in a fast page programming mode or a normal page programming mode of the chip through a page programming control signal. When the page programming control signal is high, the NVM control module is in a fast page programming mode; when the page programming control signal is low, the NVM control module is in a chip normal page programming mode.
Through the data path, the emulator control module may modify the value of the time parameter register. In a fast page programming mode, the simulator control module transmits a time parameter value to be set to a time parameter register through a data channel, and the NVM control module reads a page programming parameter value from the time parameter register to perform corresponding NVM page programming operation; in the normal page programming mode, the NVM control module uses the default time parameters to complete the corresponding NVM page programming operation.
The NVM control module supports both F L ASH fast page programming and normal page programming operations, and EEPROM fast page programming and normal page programming operations.A user can support multiple types of chip function emulation of F L ASH or EEPROM by setting the page programming time parameter.
When the simulator is in a program downloading state, the simulator control module controls the chip simulation module to realize rapid NVM page programming operation; when the simulator is in a program debugging state, the page programming time parameter of the NVM control module can be set through the simulator control module for the debugging evaluation program to use; when the simulator is in a program running state, the simulator control module controls the chip simulation module to realize the NVM page programming operation of a normal chip, so that the real chip simulation function is realized.
Drawings
FIG. 1 is a schematic structural view of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, an emulator 1 of the present invention includes an emulator control module 2 and a chip emulation module 3. The emulator control module 2 is connected with the chip emulation module 3 through a page programming control signal 8, and the NVM control module 4 in the emulation chip module 3 is in a fast page programming mode or a normal page programming mode through the page programming control signal 8. When the simulator 1 is in a program downloading state, the simulator control module 2 enables the NVM control module 4 to be in a fast page programming mode through a page programming control signal 8, so as to complete fast programming operation; when the simulator 1 is in a program debugging state, the page programming time parameter 5 of the NVM control module 4 can be set through the simulator control module 2 for the debugging evaluation program to use; when the emulator 1 is in the program running state, the emulator control module 2 makes the NVM control module 4 in the normal chip programming mode through the page programming control signal 8, so as to complete the normal programming operation.
When the emulator control module 2 is in the program download state, the emulator control module 2 makes the NVM control module 4 in the fast page programming mode through the page programming control signal 8, and at the same time, the emulator control module 2 writes the page programming parameters into the time parameter register 5 of the NVM control module 4 through the data channel 9. The NVM control module 4 controls the page programming time by reading the value in the time parameter register 5 to write data to the storage medium 7 through the memory interface 10.
When the emulator control module 2 is in the program debug state, the emulator control module 2 makes the NVM control module 4 in the fast page programming mode through the page programming control signal 8, and at the same time, the emulator control module 2 writes the page programming parameters into the time parameter register 5 of the NVM control module 4 through the data channel 9. The NVM control module 4 controls the page programming time by reading the value in the time parameter register 5 to write data to the storage medium 7 through the memory interface 10. When a user debugs a program, the value in the time parameter register 5 can be set according to debugging requirements, so that the time requirement of programming a user program page is met.
When the emulator control module 2 is in the program running state, the emulator control module 2 puts the NVM control module 4 in the chip normal page programming mode through the page programming control signal 8. At this point, the NVM control module 4 writes data into the memory world 7 through the memory interface 10 by obtaining the default time parameter 6 for chip page programming. And the NVM page programming time of the simulation chip is ensured to be consistent with that of the real chip.
The chip simulation module 3 is realized by using an FPGA chip, and the storage medium 7 is realized by using a Block RAM chip on the FPGA or an off-chip SRAM chip.
Claims (4)
1. A simulator supporting NVM fast page programming is characterized by comprising a simulator control module and a chip simulation module, wherein the chip simulation module mainly comprises an NVM control module, a time parameter register and a storage medium; the method comprises the following steps that an NVM control module in a simulation chip module is in a fast page programming mode or a chip normal page programming mode through a page programming control signal by the simulator control module, when the simulator is in a program downloading state and a debugging state, the simulator control module completes the setting of a time parameter register in the NVM control module through a data channel, the NVM control module completes the corresponding page programming operation on a storage medium according to the value in the time parameter register, and the simulator control module controls the chip simulation module to realize the fast NVM page programming operation;
when the simulator is in a program debugging state, the page programming time parameter of the NVM control module can be set through the simulator control module for the debugging evaluation program to use;
when the simulator is in a program running state, the simulator control module controls the chip simulation module to realize the NVM page programming operation of a normal chip by acquiring the default time parameter of the chip page programming.
2. The emulator of claim 1, wherein the emulator control module controls the level change of the page programming control signal to switch between different page programming modes, and when the page programming control signal is high, the NVM control module is in the fast page programming mode; when the page programming control signal is low, the NVM control module is in a chip normal page programming mode.
3. The emulator capable of supporting NVM fast page programming according to claim 1, wherein the NVM control module supports both F L ASH fast page programming and normal page programming operations, and EEPROM fast page programming and normal page programming operations.
4. The emulator capable of supporting NVM fast page programming as claimed in claim 1, wherein when the emulator is in program debug mode, the user can support chip function emulation of multiple versions of F L ASH or EEPROM by setting the page programming time parameter.
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| CN105045647B true CN105045647B (en) | 2020-08-04 |
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