CN105027095B - 降低执行硬件表移动所需资源量的方法、系统和可读介质 - Google Patents

降低执行硬件表移动所需资源量的方法、系统和可读介质 Download PDF

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Publication number
CN105027095B
CN105027095B CN201480011808.8A CN201480011808A CN105027095B CN 105027095 B CN105027095 B CN 105027095B CN 201480011808 A CN201480011808 A CN 201480011808A CN 105027095 B CN105027095 B CN 105027095B
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China
Prior art keywords
ipa
function
tlb
vmid
physical memory
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Expired - Fee Related
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CN201480011808.8A
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English (en)
Chinese (zh)
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CN105027095A (zh
Inventor
T·曾
A·托兹尼
T·R·曾
P·J·博斯特利
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/151—Emulated environment, e.g. virtual machine
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/17—Embedded application
    • G06F2212/171—Portable consumer electronics, e.g. mobile phone
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/654—Look-ahead translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/684—TLB miss handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45545—Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Software Systems (AREA)
CN201480011808.8A 2013-03-05 2014-03-04 降低执行硬件表移动所需资源量的方法、系统和可读介质 Expired - Fee Related CN105027095B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/785,877 2013-03-05
US13/785,877 US9015400B2 (en) 2013-03-05 2013-03-05 Methods and systems for reducing the amount of time and computing resources that are required to perform a hardware table walk (HWTW)
PCT/US2014/020101 WO2014137970A1 (en) 2013-03-05 2014-03-04 Methods and systems for reducing the amount of time and computing resources that are required to perform a hardware table walk

Publications (2)

Publication Number Publication Date
CN105027095A CN105027095A (zh) 2015-11-04
CN105027095B true CN105027095B (zh) 2019-01-22

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CN201480011808.8A Expired - Fee Related CN105027095B (zh) 2013-03-05 2014-03-04 降低执行硬件表移动所需资源量的方法、系统和可读介质

Country Status (7)

Country Link
US (1) US9015400B2 (enExample)
EP (1) EP2965210A1 (enExample)
JP (1) JP6298083B2 (enExample)
KR (1) KR20150128804A (enExample)
CN (1) CN105027095B (enExample)
TW (1) TWI526832B (enExample)
WO (1) WO2014137970A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9330026B2 (en) 2013-03-05 2016-05-03 Qualcomm Incorporated Method and apparatus for preventing unauthorized access to contents of a register under certain conditions when performing a hardware table walk (HWTW)
US9805194B2 (en) * 2015-03-27 2017-10-31 Intel Corporation Memory scanning methods and apparatus
US10474589B1 (en) 2016-03-02 2019-11-12 Janus Technologies, Inc. Method and apparatus for side-band management of security for a server computer
US10261916B2 (en) * 2016-03-25 2019-04-16 Advanced Micro Devices, Inc. Adaptive extension of leases for entries in a translation lookaside buffer
US10386904B2 (en) * 2016-03-31 2019-08-20 Qualcomm Incorporated Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks
US20180069767A1 (en) * 2016-09-06 2018-03-08 Advanced Micro Devices, Inc. Preserving quality of service constraints in heterogeneous processing systems
EP3355188B1 (en) 2017-01-31 2021-08-25 OpenSynergy GmbH Instrument display on a car dashboard by checking frames of a gui by a realtime os
US10754790B2 (en) * 2018-04-26 2020-08-25 Qualcomm Incorporated Translation of virtual addresses to physical addresses using translation lookaside buffer information
US12307902B2 (en) * 2020-04-21 2025-05-20 Qualcomm Incorporated Cluster-based approach to positioning of vehicles in vehicle platooning or autonomous trucking

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101558388A (zh) * 2006-09-29 2009-10-14 Mips技术公司 数据高速缓存虚拟提示路线预测及其应用
CN102722451A (zh) * 2012-06-25 2012-10-10 杭州中天微系统有限公司 采用物理地址预测访问高速缓存的装置

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2933628B2 (ja) * 1988-07-25 1999-08-16 株式会社日立製作所 主記憶装置管理方法および計算機システム
GB2260004B (en) 1991-09-30 1995-02-08 Apple Computer Memory management unit for a computer system
US7124170B1 (en) 1999-08-20 2006-10-17 Intertrust Technologies Corp. Secure processing unit systems and methods
US20030079103A1 (en) 2001-10-24 2003-04-24 Morrow Michael W. Apparatus and method to perform address translation
US8051301B2 (en) 2001-11-13 2011-11-01 Advanced Micro Devices, Inc. Memory management system and method providing linear address based memory access security
GB2409745B (en) 2002-11-18 2006-01-11 Advanced Risc Mach Ltd Virtual to physical memory address mapping within a system having a secure domain and a non-secure domain
US7089397B1 (en) * 2003-07-03 2006-08-08 Transmeta Corporation Method and system for caching attribute data for matching attributes with physical addresses
US7117290B2 (en) * 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US8156343B2 (en) * 2003-11-26 2012-04-10 Intel Corporation Accessing private data about the state of a data processing machine from storage that is publicly accessible
US7162609B2 (en) * 2003-12-03 2007-01-09 Marvell International Ltd. Translation lookaside buffer prediction mechanism
EP1870814B1 (en) 2006-06-19 2014-08-13 Texas Instruments France Method and apparatus for secure demand paging for processor devices
US7340582B2 (en) 2004-09-30 2008-03-04 Intel Corporation Fault processing for direct memory access address translation
US7428626B2 (en) 2005-03-08 2008-09-23 Microsoft Corporation Method and system for a second level address translation in a virtual machine environment
US20060224815A1 (en) 2005-03-30 2006-10-05 Koichi Yamada Virtualizing memory management unit resources
US20070226795A1 (en) 2006-02-09 2007-09-27 Texas Instruments Incorporated Virtual cores and hardware-supported hypervisor integrated circuits, systems, methods and processes of manufacture
US7822941B2 (en) 2006-06-05 2010-10-26 Oracle America, Inc. Function-based virtual-to-physical address translation
US8615643B2 (en) * 2006-12-05 2013-12-24 Microsoft Corporation Operational efficiency of virtual TLBs
EP2075696A3 (en) 2007-05-10 2010-01-27 Texas Instruments Incorporated Interrupt- related circuits, systems and processes
US8661181B2 (en) * 2007-06-28 2014-02-25 Memory Technologies Llc Memory protection unit in a virtual processing environment
US8595465B1 (en) * 2009-09-09 2013-11-26 Marvell Israel (M.I.S.L) Ltd. Virtual address to physical address translation using prediction logic
US9098700B2 (en) 2010-03-01 2015-08-04 The Trustees Of Columbia University In The City Of New York Systems and methods for detecting attacks against a digital circuit
US9405700B2 (en) 2010-11-04 2016-08-02 Sonics, Inc. Methods and apparatus for virtualization in an integrated circuit
US20120246381A1 (en) * 2010-12-14 2012-09-27 Andy Kegel Input Output Memory Management Unit (IOMMU) Two-Layer Addressing
US9092358B2 (en) * 2011-03-03 2015-07-28 Qualcomm Incorporated Memory management unit with pre-filling capability
US9009445B2 (en) * 2011-10-20 2015-04-14 Apple Inc. Memory management unit speculative hardware table walk scheme
US9330026B2 (en) 2013-03-05 2016-05-03 Qualcomm Incorporated Method and apparatus for preventing unauthorized access to contents of a register under certain conditions when performing a hardware table walk (HWTW)

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101558388A (zh) * 2006-09-29 2009-10-14 Mips技术公司 数据高速缓存虚拟提示路线预测及其应用
CN102722451A (zh) * 2012-06-25 2012-10-10 杭州中天微系统有限公司 采用物理地址预测访问高速缓存的装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SpecTLB: a mechanism for speculative address translation;TW Barr, AL Cox, S Rixner;《International Symposium on Computer Architecture》;20110430;参见第307-317页、图1-5 *

Also Published As

Publication number Publication date
WO2014137970A1 (en) 2014-09-12
TW201447583A (zh) 2014-12-16
JP6298083B2 (ja) 2018-03-20
US9015400B2 (en) 2015-04-21
KR20150128804A (ko) 2015-11-18
EP2965210A1 (en) 2016-01-13
US20140258586A1 (en) 2014-09-11
JP2016513835A (ja) 2016-05-16
CN105027095A (zh) 2015-11-04
TWI526832B (zh) 2016-03-21

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