CN105023834A - Vertical anti-blooming CCD manufacturing technology - Google Patents
Vertical anti-blooming CCD manufacturing technology Download PDFInfo
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- CN105023834A CN105023834A CN201510487424.XA CN201510487424A CN105023834A CN 105023834 A CN105023834 A CN 105023834A CN 201510487424 A CN201510487424 A CN 201510487424A CN 105023834 A CN105023834 A CN 105023834A
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- China
- Prior art keywords
- vertical anti
- ion injection
- blooming
- single crystal
- crystal silicon
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 238000002347 injection Methods 0.000 claims abstract description 22
- 239000007924 injection Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000004913 activation Effects 0.000 claims abstract description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- -1 phosphonium ion Chemical class 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 14
- 238000000407 epitaxy Methods 0.000 claims description 9
- 238000001994 activation Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 claims description 3
- 229940085991 phosphate ion Drugs 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14806—Structural or functional details thereof
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- High Energy & Nuclear Physics (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention provides a vertical anti-blooming CCD manufacturing technology which comprises the steps that 1) an N-type mono-crystalline silicon wafer is provided; 2) an oxide layer is formed on the surface of the N-type mono-crystalline silicon wafer; 3) phosphorous ion injection is performed on the N-type mono-crystalline silicon wafer so that a certain thickness of phosphorous ion injection region is formed in the N-type mono-crystalline silicon wafer; 4) activation processing is performed on the phosphorous ion injection region, and an N-type sandwich layer is formed in the activated phosphorous ion injection region; 5) the oxide layer on the surface of the N-type mono-crystalline silicon wafer is removed; 5) an epitaxial layer is grown on the N-type mono-crystalline silicon wafer so that a substrate is formed; and 7) a gate medium, a p-well, channel resistance, channels, a transfer gate, connecting holes and a metal lead wire are manufactured on the substrate in turn. The beneficial technical effects of the vertical anti-blooming CCD manufacturing technology are that resistivity heterogeneity of the N-type sandwich layer is reduced, and homogeneity control of a large-scale vertical anti-blooming CCD is facilitated. Only the primary epitaxial technology is adopted by the vertical anti-blooming CCD manufacturing technology so that integral controllability of the technology is relatively high.
Description
Technical field
The present invention relates to a kind of CCD manufacture craft, particularly relate to a kind of vertical anti-blooming CCD manufacture craft.
Background technology
When ccd image sensor is under strong light environment, because the light induced electron produced exceedes trap capacity, unnecessary electrons is towards closing on pixel diffusion, and this situation is called halation phenomenon; For foregoing problems, in prior art, generally in ccd image sensor, arrange antibloom structure, antibloom structure can take excess electron away, thus plays inhibitory action to halation phenomenon; Common antibloom structure has horizontal antibloom structure and vertical anti-blooming structure, and wherein, vertical anti-blooming structure can not tie up photosensitive area area because of it and reduce device duty ratio, has larger advantage.
Traditional vertical anti-blooming structure is after Grown gate medium, carry out the making of P trap, and then form longitudinal anti-blooming potential barrier, by regulating P trap concentration, different anti-blooming barrier heights can be obtained, in practical application, the vertical anti-blooming voltage of this vertical anti-blooming structure is comparatively large, causes device power consumption larger; In order to reduce anti-blooming voltage, external producer is optimized for silicon substrate, and be optimized for the epitaxial silicon substrate of band N-type sandwich of layers by original N-type substrate, its structure is: epitaxial loayer/N-type sandwich of layers/substrate layer; The epitaxial silicon substrate of this band N-type sandwich of layers, epitaxial loayer on it and N-type sandwich of layers all adopt epitaxy technique to make, because epitaxy technique control difficulty is larger, cause N-type sandwich of layers resistivity heterogeneity≤16% of gained, and affect by N-type sandwich of layers resistivity heterogeneity, its epilayer resistance rate heterogeneity≤15%, in the case, is unfavorable for the uniformity controlling of extensive (4096 yuan × 4096 yuan and more than) vertical anti-blooming CCD.
Summary of the invention
For the problem in background technology, the present invention proposes a kind of vertical anti-blooming CCD manufacture craft, its innovation is: following steps for manufacturing vertical anti-blooming CCD:1) n type single crystal silicon sheet is provided;
2) oxide layer is formed on n type single crystal silicon sheet surface;
3) phosphonium ion injection is carried out to n type single crystal silicon sheet, make to form certain thickness phosphonium ion injection region in n type single crystal silicon sheet;
4) carry out activation process to phosphonium ion injection region, the phosphonium ion injection region after activation forms N-type sandwich of layers;
5) oxide layer on n type single crystal silicon sheet surface is removed;
6) at n type single crystal silicon sheet growing epitaxial layers, substrate is formed;
7) on substrate, produce gate medium, P trap, ditch resistance, raceway groove, TG transfer gate, connecting hole and metal lead wire successively.
The present invention's difference maximum from prior art is that the technique forming N-type sandwich of layers is different, adopt epitaxy technique to form N-type sandwich of layers in prior art, adopt ion implantation technology to form N-type sandwich of layers in the present invention, compared to epitaxy technique, the controllability of ion implantation technology is better, adopt the N-type sandwich of layers that ion implantation technology is formed, its resistivity heterogeneity≤3%, epilayer resistance rate heterogeneity≤10% of follow-up formation, for whole technological process, an epitaxy technique (grown epitaxial layer namely in step 6)) is only have employed in the present invention, the global controllability of technological process is improved, in addition, operate described in step 7) of the present invention all same as the prior art.
Preferably, step 2) in the thickness of oxide layer be 10 ~ 60nm.
Preferably, in step 3), phosphonium ion injection condition is: Implantation Energy 200 ~ 300keV, surface concentration 4 ~ 6E12cm
-2.
Preferably, adopt following technique to activate phosphonium ion injection region in step 4): to be placed in nitrogen atmosphere by n type single crystal silicon sheet, anneal 30 ~ 60 minutes under 900 DEG C of conditions.
Preferably, in step 6), epitaxial loayer phosphate ion concentration is 1 ~ 3E14cm
-3, epitaxy layer thickness is 3 ~ 10 μm.
Advantageous Effects of the present invention is: the resistivity heterogeneity reducing N-type sandwich of layers, is conducive to the uniformity controlling of extensive vertical anti-blooming CCD, and the present invention only have employed an epitaxy technique, and the global controllability of technique is higher.
Accompanying drawing explanation
Fig. 1, the structural representation of device obtained by the inventive method;
In figure each mark corresponding to title be respectively: n type single crystal silicon sheet 1, N-type sandwich of layers 2, P trap 3, ditch resistance 4, gate medium 5, raceway groove 6, TG transfer gate 7.
Embodiment
A kind of vertical anti-blooming CCD manufacture craft, its innovation is: following steps for manufacturing vertical anti-blooming CCD:1) n type single crystal silicon sheet is provided;
2) oxide layer is formed on n type single crystal silicon sheet surface;
3) phosphonium ion injection is carried out to n type single crystal silicon sheet, make to form certain thickness phosphonium ion injection region in n type single crystal silicon sheet;
4) carry out activation process to phosphonium ion injection region, the phosphonium ion injection region after activation forms N-type sandwich of layers;
5) oxide layer on n type single crystal silicon sheet surface is removed;
6) at n type single crystal silicon sheet growing epitaxial layers, substrate is formed;
7) on substrate, produce gate medium, P trap, ditch resistance, raceway groove, TG transfer gate, connecting hole and metal lead wire successively.
Further, step 2) in the thickness of oxide layer be 10 ~ 60nm.
Further, in step 3), phosphonium ion injection condition is: Implantation Energy 200 ~ 300keV, surface concentration 4 ~ 6E12cm
-2.
Further, adopt following technique to activate phosphonium ion injection region in step 4): to be placed in nitrogen atmosphere by n type single crystal silicon sheet, anneal 30 ~ 60 minutes under 900 DEG C of conditions.
Further, in step 6), epitaxial loayer phosphate ion concentration is 1 ~ 3E14cm
-3, epitaxy layer thickness is 3 ~ 10 μm.
Claims (5)
1. a vertical anti-blooming CCD manufacture craft, is characterized in that: following steps for manufacturing vertical anti-blooming CCD:1) n type single crystal silicon sheet is provided;
2) oxide layer is formed on n type single crystal silicon sheet surface;
3) phosphonium ion injection is carried out to n type single crystal silicon sheet, make to form certain thickness phosphonium ion injection region in n type single crystal silicon sheet;
4) carry out activation process to phosphonium ion injection region, the phosphonium ion injection region after activation forms N-type sandwich of layers;
5) oxide layer on n type single crystal silicon sheet surface is removed;
6) at n type single crystal silicon sheet growing epitaxial layers, substrate is formed;
7) on substrate, produce gate medium, P trap, ditch resistance, raceway groove, TG transfer gate, connecting hole and metal lead wire successively.
2. vertical anti-blooming CCD manufacture craft according to claim 1, is characterized in that: step 2) in the thickness of oxide layer be 10 ~ 60nm.
3. vertical anti-blooming CCD manufacture craft according to claim 1, it is characterized in that: in step 3), phosphonium ion injection condition is: Implantation Energy 200 ~ 300keV, surface concentration 4 ~ 6E12cm
-2.
4. vertical anti-blooming CCD manufacture craft according to claim 1, is characterized in that: adopt following technique to activate phosphonium ion injection region in step 4): to be placed in nitrogen atmosphere by n type single crystal silicon sheet, anneals 30 ~ 60 minutes under 900 DEG C of conditions.
5. vertical anti-blooming CCD manufacture craft according to claim 1, is characterized in that: in step 6), and epitaxial loayer phosphate ion concentration is 1 ~ 3E14cm
-3, epitaxy layer thickness is 3 ~ 10 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510487424.XA CN105023834A (en) | 2015-08-11 | 2015-08-11 | Vertical anti-blooming CCD manufacturing technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510487424.XA CN105023834A (en) | 2015-08-11 | 2015-08-11 | Vertical anti-blooming CCD manufacturing technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105023834A true CN105023834A (en) | 2015-11-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510487424.XA Pending CN105023834A (en) | 2015-08-11 | 2015-08-11 | Vertical anti-blooming CCD manufacturing technology |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6140147A (en) * | 1998-07-31 | 2000-10-31 | Nec Corporation | Method for driving solid-state imaging device |
| JP2002237585A (en) * | 2001-02-13 | 2002-08-23 | Sony Corp | Manufacturing method of vertical overflow drain system solid-state imaging element |
| JP2002368204A (en) * | 2001-06-08 | 2002-12-20 | Sony Corp | Solid-state imaging element and manufacturing method therefor |
| EP1748490A1 (en) * | 2005-07-28 | 2007-01-31 | Fuji Photo Film Co., Ltd. | Fabrication method for epitaxially grown solid-state image sensing devices and such devices |
| CN102064181A (en) * | 2010-12-03 | 2011-05-18 | 中国电子科技集团公司第四十四研究所 | SOI (Silicon On Insulator) material based CCD (Charge Coupled Device) capable of suppressing interface dark current of buried oxide layer |
| CN102064182A (en) * | 2010-12-07 | 2011-05-18 | 中国电子科技集团公司第四十四研究所 | Method for manufacturing CCD (Charge Couple Device) for reducing sensor dark current |
| JP2012204674A (en) * | 2011-03-25 | 2012-10-22 | Sharp Corp | Epitaxial substrate and manufacturing method therefor, solid state image sensor and manufacturing method therefor, electronic information apparatus |
| CN103337509A (en) * | 2013-06-13 | 2013-10-02 | 中国兵器工业集团第二一四研究所苏州研发中心 | Anti-dispersion structure and manufacture technology of electron multiplying charge-coupled device(EMCCD) |
| CN104037186A (en) * | 2014-06-25 | 2014-09-10 | 中国兵器工业集团第二一四研究所苏州研发中心 | Halo resisting structure of charge carrier multiplication register |
-
2015
- 2015-08-11 CN CN201510487424.XA patent/CN105023834A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6140147A (en) * | 1998-07-31 | 2000-10-31 | Nec Corporation | Method for driving solid-state imaging device |
| JP2002237585A (en) * | 2001-02-13 | 2002-08-23 | Sony Corp | Manufacturing method of vertical overflow drain system solid-state imaging element |
| JP2002368204A (en) * | 2001-06-08 | 2002-12-20 | Sony Corp | Solid-state imaging element and manufacturing method therefor |
| EP1748490A1 (en) * | 2005-07-28 | 2007-01-31 | Fuji Photo Film Co., Ltd. | Fabrication method for epitaxially grown solid-state image sensing devices and such devices |
| CN102064181A (en) * | 2010-12-03 | 2011-05-18 | 中国电子科技集团公司第四十四研究所 | SOI (Silicon On Insulator) material based CCD (Charge Coupled Device) capable of suppressing interface dark current of buried oxide layer |
| CN102064182A (en) * | 2010-12-07 | 2011-05-18 | 中国电子科技集团公司第四十四研究所 | Method for manufacturing CCD (Charge Couple Device) for reducing sensor dark current |
| JP2012204674A (en) * | 2011-03-25 | 2012-10-22 | Sharp Corp | Epitaxial substrate and manufacturing method therefor, solid state image sensor and manufacturing method therefor, electronic information apparatus |
| CN103337509A (en) * | 2013-06-13 | 2013-10-02 | 中国兵器工业集团第二一四研究所苏州研发中心 | Anti-dispersion structure and manufacture technology of electron multiplying charge-coupled device(EMCCD) |
| CN104037186A (en) * | 2014-06-25 | 2014-09-10 | 中国兵器工业集团第二一四研究所苏州研发中心 | Halo resisting structure of charge carrier multiplication register |
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| RJ01 | Rejection of invention patent application after publication | ||
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Application publication date: 20151104 |