CN105022875B - Consider the cmos circuit total dose effect emulation mode of Radiation bias voltage dynamic change - Google Patents
Consider the cmos circuit total dose effect emulation mode of Radiation bias voltage dynamic change Download PDFInfo
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Abstract
The present invention relates to a kind of cmos circuit total dose effect emulation mode for considering Radiation bias voltage dynamic change, the step of including single tube Establishing an injured model, Transient is performed to cmos circuit to be studied, influence of the different Radiation bias voltages to hole yield in oxide layer is described, and establish Radiation bias voltage and test with the relation between irradiation voltage the step of, ask for intergal dose equal to equivalent intergal dose striked by step 2.4) using linear difference with reference to single tube damage model when circuit in single tube device electric property degeneration the step of.The present invention it is contemplated that in irradiation process bias conditions dynamic, the actual conditions of various change, realize the actual performance degeneration extrapolated using the electric property degraded data that single tube is surveyed under single Radiation bias and form integrated circuit under any Radiation bias in single tube, and irradiation process in any mode of operation, by the different single tube of bias conditions in a large amount of irradiation process.
Description
Technical field
The invention belongs to the simulation of the total dose effect of CMOS integrated circuits and design reinforcement checking field.
Background technology
Semiconductor devices long-term work is in space radiation environment, and excess carriers caused by radiation are in device oxide layer
It is captured, the electric property for causing device is occurred to degenerate even, and entirely chip circuit generating function fails, this cumulative ionization
Damage is referred to as total dose effect.
For integrated circuit, general irradiation test is only capable of obtaining macroscopical lump electrical parameter to be increased with intergal dose
And the change of generation, it is simple to rely on experiment it is difficult to provide Analysis of Failure Mechanism that is clear and definite, going deep into details.And by simulation analysis
Method can be to macroscopic view failure characterize and carry out further discriminant analysis, while provide the explanation in terms of effector mechanism.It is another
Aspect, simulation analysis can be in the radiation resistance of design prediction at initial stage chip, and then provides the criterion of modification design, greatly
Reduce cost needs.
The juche idea of total dose effect circuit simulation is that radiation effect is introduced to the SPICE models of transistor level.First
The single tube model for introducing total dose effect is built according to irradiation test data, circuit simulation is carried out then in conjunction with commercial tool.Should
You Shuojia mechanisms were studied for the part of structure single tube model in flow, referring to number of patent application 200910078910, title
For " a kind of device modeling method related to integral dose radiation "；Number of patent application 201010145101.X, entitled " one kind is right
Semiconductor devices carries out the method that total dose irradiation carries mould of taking part in building ".Because obtained single tube model correspond to single Radiation bias
Situation (be usually irradiation process in grid connect operating voltage), common processing method is set in ensuing circuit simulation
Put all transistors and uniformly add single Radiation bias, referring to number of patent application 201010275725, entitled " one kind estimation
The method of integrated circuit irradiation effect ".The different biasing shapes of circuit internal transistor in real work are not considered in the simplification
Condition and dynamic change, acquired results will over-evaluate the radiation injury degree of circuit, and then underestimate the resistant to total dose ability of circuit.
The content of the invention
Circuit internal transistor in real work is not considered in order to solve existing total dose effect circuit emulation method
Different bias conditions and dynamic change, the inaccurate technical problem of acquired results, the present invention one kind is provided and is directed to cmos circuit
In view of the circuit simulation method of bias conditions dynamic change in irradiation process, for more rationally accurately studying the total of circuit
Dosage effect and predict its Radiation hardness.
The present invention technical solution be：The CMOS electricity of Radiation bias voltage dynamic change in a kind of consideration irradiation process
Road total dose effect emulation mode, it is characterised in that comprise the following steps：
1) single tube Establishing an injured model
1.1) select and cmos circuit characteristic size identical single column run piece to be studied；
1.2) test single column run piece in different intergal doses, most it is bad irradiation voltage bias effect under single tube test film electricity
Learn performance degradation；Extract the single tube damage model under the most bad irradiation voltage bias of concrete numerical value structure that electric property is degenerated；
2) Transient is performed to cmos circuit to be studied, describes different Radiation bias voltages to hole yield in oxide layer
Influence, and establish Radiation bias voltage and test irradiation voltage between relation
2.1) driving source in irradiation process, the duration of driving source, the Transient step in the duration section are set
Long and simulated dose rate,
2.2) Transient is performed, the emulation of each step is monitored and records each single tube device in cmos circuit to be studied
Source electrode, drain electrode, grid and the terminal voltage of substrate four of part；
2.3) oxide layer electric field intensity inside high and the sky gone out using the parameter conversion of step 2.2) record in single step time interval
Cave yield, and draw the relation between oxide layer electric field intensity inside high and hole yield；
2.4) relation between the oxide layer electric field intensity inside high and hole yield that are drawn using step 2.3), and using etc.
The relation of conceptual description any time Radiation bias voltage and test between irradiation voltage of intergal dose is imitated, is specially：
Wherein, VgbRepresent the voltage difference between grid and substrate, Radiation bias voltage, EoxRepresent the electric-field strength in oxide layer
Degree, concrete numerical value is by VgbIt is calculated, Y represents hole yield (the hole ratio for escaping initial composite), Y (EOx, i) represent i-th
Walk the hole yield in the period；DiThe intergal dose in the i-th step period is represented,Represent in step 1)
Hole yield under different intergal doses, most bad irradiation voltage bias, the numerical value do not increase and changed with intergal dose, Vdd
Represent most bad bias voltage；
3) the single tube damage model that step 1) is established is combined, is approximately considered in step 1.2) single tube between different intergal doses
The performance degradation of test film meets continuous, linear feature, and it is required equal to step 2.4) to ask for intergal dose using linear difference
The electric property of single tube device is degenerated in circuit during the equivalent intergal dose taken；
4) parameter using the electric property degeneration concrete numerical value striked by step 3) to each single tube device after irradiation
Enter Mobile state renewal.
Above-mentioned steps 2.3) in influence of the Radiation bias voltage for hole yield in oxide layer is retouched using formula (1)
State：
Eox,cIt is undetermined parameter with m, is determined by emission types, for conventional Co-60 gamma ray projectors, Eox,c=
0.65MV/cm, m=0.9.
Above-mentioned steps 2) in the Transient of cmos circuit to be studied, be divided into three time phases, respectively predose,
In irradiation process and after irradiation, setting for driving source is all used for the service behaviour for detecting circuit after predose and irradiation, selects as far as possible
With parameters such as equal rise or fall times, in irradiation process the setting of driving source will with it is actual carry out irradiation test when shape
Condition is consistent, and the Transient step-length and simulated dose rate in its duration, the period will all be used as adjustable parameter
For embodying the numerical value of intergal dose.
Above-mentioned steps 2) -4) used by emulation tool be SPICE.
Above-mentioned steps 1) single tube Establishing an injured model select be the Verilog-A language mutually compatible with SPICE emulation tools
Speech programming.
The advantage of the invention is that：
1st, the method proposed by the present invention that cmos circuit total dose effect is studied using circuit simulation, it is contemplated that irradiation
During bias conditions dynamic, the actual conditions of various change, realize and utilize the electricity that single tube is surveyed under single Radiation bias
Performance Degradation Data, which is extrapolated, is in any mode of operation, by a large amount of spokes in single tube, and irradiation process under any Radiation bias
The different single tube of bias conditions forms the actual performance degeneration of integrated circuit according to during.
2nd, the present invention is realized using analytic method and turned between single tube electric property is degenerated in the case of different Radiation bias
Change, avoid the need for carrying out single tube irradiation experiment under various Radiation bias, can greatly save experimental cost.
3rd, the present invention can be adjusted very easily after being realized using Verilog-A language by circuit simulating software SPICE
With, its performance degradation is predicted to the cmos circuit that any working condition is in irradiation process so as to realize, can be easily embedding
Enter into universal circuit design cycle.
Brief description of the drawings
Fig. 1：The flow chart of single tube damage model under the most bad biasing of structure；
Fig. 2：The contrast of single tube damage model and measured data under constructed most bad biasing；
Fig. 3：The main process figure of the present invention；
Fig. 4：With reference to the simulation example of por circuit.
Embodiment
Emphasis of the present invention solves existing methods deficiency, when simulation calculating is carried out to cmos circuit total dose effect, will examine
Consider the practical working situation of each single tube in irradiation process, it is allowed to its dynamic change and be not limited to the single irradiation set
Biasing (being usually most bad biasing).By studying intergal dose work is cooperateed with Radiation bias for what device electric property was degenerated
With successfully proposing a kind of method of analog cmos circuit total dose effect.
The preferred embodiment of the present invention is further elaborated below in conjunction with the accompanying drawings.
Fig. 1 show the flow chart for building single tube damage model under most bad biasing, relative with the step 1) in the content of the invention
Should.Research foundation be with cmos circuit characteristic size identical single column run piece to be studied, choose some intergal dose points, test
The electrical parameter of MOS single tubes is degenerated when corresponding to different intergal doses under most bad bias conditions, and extraction obtains threshold voltage, zero grid voltage
The concrete numerical value of the parameter degradations such as drain current, and it is modeled description using Verilog-A language.
By taking certain 0.25 μm of technique as an example, the single tube damage model under most bad biasing is constructed, Fig. 2 show size as 0.8/
The contrast of 0.24 μm of nMOS single tubes damage model and test data, there it can be seen that the damage built using step in Fig. 1
Model can accurately reflect the parameter degradation of MOS single tubes after irradiation.
Fig. 3 gives the main process figure of the present invention, and time zone is already divided into three parts in Transient：Spoke
According in preceding, irradiation process and after irradiation.Need to set beginning and ending time, simulation step length and the irradiation dose of irradiation process before actual execution
Rate, when performing Transient, each step will all monitor and record source electrode, drain electrode, grid and the end of substrate four of each single tube device
Voltage, and then the oxide layer electric field intensity inside high in single step time interval and hole yield are conversed, describe to bias using formula (1)
The different influences for hole yield in oxide layer：And obtain the equivalent intergal dose D at current time using formula (2)eff。
Transient step-length and simulated dose rate in the duration of each step, the period will all be used as adjustable
Parameter is used for the numerical value for embodying intergal dose.Duration such as irradiation process is set as 2ms-4ms, and Transient step-length is 2 μ
S, then the sampling number that Transient is performed in whole irradiation process is 1000, further sets simulated dose rate as 100rad
(SiO2), then after whole irradiation process is finished, intergal dose is up to 100krad (SiO2).Now corresponding equivalent accumulation
Dosage can be expressed as：
Wherein, i represents the calculating step number in Transient, Eox,iAnd DiRepresent respectively corresponding to the i-th step in time interval
Electric field across oxide intensity and intergal dose.
Afterwards, degenerated with reference to the single tube electric property in the case of different intergal doses in step 1), using Verilog-A languages
Say that programming description characterizes the parasitic transistor of single tube radiation injury.On the basis of step 2.4), equivalent accumulation agent is calculated
The numerical value of amount, interpolation ask for single tube electricity under the most bad Radiation bias corresponding when intergal dose is equal to above-mentioned equivalent intergal dose
Performance degradation is learned, while is to consider the numerical value after Radiation bias influences by the single tube parameter dynamical update after irradiation.Now " spoke
According to rear " Simulation results in the period correspond to the degree of injury after whole circuit is influenceed by irradiation.Using
After flow in Fig. 3 is described Verilog-A language, the code for working out to obtain can be called directly by SPICE softwares,
The change of single tube electrical parameter can be directly embedded into the electric current of circuit node with voltage Simultaneous Equations, finally solving
Change of the circuit integrity energy parameter under the influence of total dose effect.
Fig. 4 show a kind of total dose effect simulation result of por circuit." predose " period is 100 μ s-2.1ms,
Output signal in the time is amplitude 1.5V voltage pulse, and the later stage examine circuit whether normal work benchmark it is defeated
Go out." in the irradiation process " period is 2.1ms-4.1ms, and Transient step-length is 2 μ s, and close rate is 60rad (SiO2), the area
The bias conditions of circuit are consistent with actual irradiation situation in domain, and holding input stimulus are high level, and output signal is continuously low
Level.Time later 4.1ms correspond to " after irradiation ", now set input stimulus and " predose " time it is short it is interior possess it is identical
Rise time and amplitude of variation, and it is 60krad (SiO that output signal, which will represent intergal dose,2) when circuit output, this
When output signal be no longer standard triangular pulse, but there occurs obvious deformation, it is 60krad to illustrate intergal dose
(SiO2) when, por circuit cisco unity malfunction.
Claims (5)
1. a kind of cmos circuit total dose effect emulation mode for considering Radiation bias voltage dynamic change in irradiation process, it is special
Sign is, comprises the following steps：
1) single tube Establishing an injured model
1.1) select and cmos circuit characteristic size identical single column run piece to be studied；
1.2) test single column run piece in different intergal doses, most it is bad irradiation voltage bias effect under single tube test film electrical property
It can degenerate；Extract the single tube damage model under the most bad irradiation voltage bias of concrete numerical value structure that electric property is degenerated；
2) Transient is performed to cmos circuit to be studied, describes shadow of the different Radiation bias voltages to hole yield in oxide layer
Ring, and the relation established between Radiation bias voltage and test irradiation voltage
2.1) set irradiation process in driving source, the duration of driving source, the Transient step-length in the duration section and
Simulated dose rate,
2.2) Transient is performed, the emulation of each step is monitored and records each single tube device in cmos circuit to be studied
Source electrode, drain electrode, grid and the terminal voltage of substrate four；
2.3) the oxide layer electric field intensity inside high gone out using the parameter conversion of step 2.2) record in single step time interval and hole production
Volume, and draw the relation between oxide layer electric field intensity inside high and hole yield；
2.4) relation between the oxide layer electric field intensity inside high and hole yield that are drawn using step 2.3), and using equivalent tired
The relation of conceptual description any time Radiation bias voltage and test between irradiation voltage of product dosage, it is specially：
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Wherein, VgbRepresent the voltage difference between grid and substrate, that is, Radiation bias voltage, EoxRepresent the electric-field strength in oxide layer
Degree, concrete numerical value is by VgbIt is calculated, Y represents hole yield, Y (EOx, i) represent the i-th step period in hole yield, DiTable
Show the intergal dose in the i-th step period,Represent the hole under most bad irradiation voltage bias in step 1)
Yield, the numerical value do not increase and changed with intergal dose, VddRepresent most bad Radiation bias voltage；
3) the single tube damage model that step 1) is established is combined, is approximately considered in step 1.2) single column run between different intergal doses
The performance degradation of piece meets continuous, linear feature, and intergal dose is asked for equal to striked by step 2.4) using linear difference
The electric property of single tube device is degenerated in circuit during equivalent intergal dose；
4) parameter of each single tube device after irradiation is carried out using the electric property degeneration concrete numerical value striked by step 3)
Dynamic updates.
2. the cmos circuit accumulated dose effect according to claim 1 for considering Radiation bias voltage dynamic change in irradiation process
Answer emulation mode, it is characterised in that：
Influence of the Radiation bias voltage for hole yield in oxide layer is described using formula (1) in step 2.3)：
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Eox,cIt is undetermined parameter with m, is determined by emission types.
3. the cmos circuit accumulated dose effect according to claim 1 for considering Radiation bias voltage dynamic change in irradiation process
Answer emulation mode, it is characterised in that：
To the Transient of cmos circuit to be studied in step 2), it is divided into three time phases, respectively predose, irradiation process
After neutralizing irradiation, the setting of driving source is all for the service behaviour for detecting circuit after predose and irradiation, from equal rising
Or fall time parameter, in irradiation process the setting of driving source will with it is actual carry out irradiation test when situation it is consistent.
4. the cmos circuit of Radiation bias voltage dynamic change is total in the consideration irradiation process according to claim 1 or 2 or 3
Dosage effect emulation mode, it is characterised in that：Step 2) -4) used by emulation tool be SPICE.
5. the cmos circuit accumulated dose effect according to claim 4 for considering Radiation bias voltage dynamic change in irradiation process
Answer emulation mode, it is characterised in that：
What step 1) single tube Establishing an injured model was selected is the Verilog-A Programming with Pascal Language mutually compatible with SPICE emulation tools.
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| CN107305593B (en) * | 2016-04-21 | 2020-12-01 | 中国科学院上海微系统与信息技术研究所 | Modeling method of SOI MOSFET total dose irradiation model |
| CN106649920A (en) * | 2016-09-14 | 2017-05-10 | 西安电子科技大学 | IBIS-based integrated circuit total dose effect modeling method |
| CN108508351B (en) * | 2018-03-30 | 2020-05-05 | 西北核技术研究所 | Single event fault injection simulation method based on double-exponent current source |
| CN108536959A (en) * | 2018-04-09 | 2018-09-14 | 中国科学院上海微系统与信息技术研究所 | Radiation patterns embedding grammar and emulation mode for the emulation of channel radiation effect |
| CN110783203A (en) * | 2019-10-28 | 2020-02-11 | 深圳尚阳通科技有限公司 | Method for reducing threshold voltage of MOSFET after radiation recovery |
| CN112214953B (en) * | 2020-10-20 | 2022-08-05 | 中国科学院新疆理化技术研究所 | Circuit-level total dose radiation effect simulation method |
| CN114169194A (en) * | 2021-11-25 | 2022-03-11 | 中国科学院新疆理化技术研究所 | Simulation analysis method for total ionization dose effect of multi-gate fin field effect transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6216099B1 (en) * | 1997-09-05 | 2001-04-10 | Advanced Micro Devices, Inc. | Test system and methodology to improve stacked NAND gate based critical path performance and reliability |
| CN101551831A (en) * | 2009-02-27 | 2009-10-07 | 北京时代民芯科技有限公司 | A device modeling method in relation to total dose radiation |
| CN101923596A (en) * | 2010-09-08 | 2010-12-22 | 北京大学 | Method for estimating radiation effect of integrated circuit |
| CN102214251A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Method for extracting parameters and establishing models for total dose irradiation of semiconductor device |
-
2015
- 2015-07-14 CN CN201510412969.4A patent/CN105022875B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6216099B1 (en) * | 1997-09-05 | 2001-04-10 | Advanced Micro Devices, Inc. | Test system and methodology to improve stacked NAND gate based critical path performance and reliability |
| CN101551831A (en) * | 2009-02-27 | 2009-10-07 | 北京时代民芯科技有限公司 | A device modeling method in relation to total dose radiation |
| CN102214251A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Method for extracting parameters and establishing models for total dose irradiation of semiconductor device |
| CN101923596A (en) * | 2010-09-08 | 2010-12-22 | 北京大学 | Method for estimating radiation effect of integrated circuit |
Non-Patent Citations (1)
| Title |
|---|
| 辐照偏置影响深亚微米MOS器件总剂量效应的理论研究;丁李利等;《原子能科学技术》;20130520;第47卷(第5期);第842-847页 * |
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