CN104994034B - A kind of receiving/transmission method of the point-to-point SV messages of combining unit - Google Patents
A kind of receiving/transmission method of the point-to-point SV messages of combining unit Download PDFInfo
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- CN104994034B CN104994034B CN201510386642.4A CN201510386642A CN104994034B CN 104994034 B CN104994034 B CN 104994034B CN 201510386642 A CN201510386642 A CN 201510386642A CN 104994034 B CN104994034 B CN 104994034B
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Abstract
The present invention relates to a kind of receiving/transmission methods of the point-to-point SV messages of combining unit, this method is packaged SV messages using the stronger operational capabilities of CPU, periodically inquiry FPGA sends whether buffering area has message, there is message, parse outgoing packet sending time, and the time needed according to message sending time and one frame message of transmission, it calculates message and sends the stand-by period, stand-by period is shorter, it waits for a period of time, message is sent, otherwise, inquiry DM9000C receives whether buffering area has message, there is message, message, which will be received, by the high-resolution timer of FPGA beats time stamp, realize the point-to-point receive capabilities of SV messages.The method of the present invention substantially increases the uniformity and reliability of SV packet sending and receivings.
Description
Technical field
The invention belongs to power system transformer substation intelligent network technical fields, and in particular to a kind of combining unit is point-to-point
SV packet sending and receiving methods.
Background technology
Combining unit, abbreviation MU are that a kind of electrical quantity transmitted to a mutual inductor merges and synchronization process,
And digital signal is transmitted to the device that bay device uses according to specific format by treated.Combining unit is electronic type electricity
The interface arrangement of stream, voltage transformer.Combining unit realizes the shared and digitlization of process layer data to a certain extent, it
As the digital substation interval layer of IEC61850 standards, the data source of station level equipment is followed, effect is particularly significant.With
The popularization and engineering construction for digital transformer substation automatic technology, it is higher and higher to the function and performance requirement of combining unit.
The main function of combining unit be the data of collector are carried out packing processing, and by way of SV messages on give protection dress
It sets.SV messages are widely used a kind of ether network packets in digital transformer substation, are mainly used to transmit the simulations such as Current Voltage
Measure information.
There is network delay, the various destabilizing factors such as network congestion, in order to improve protection system for traditional Ethernet
Reliability, in the newest specification of national grid, it is proposed that use point-to-point connection between combining unit and protective device
Mode.Using point-to-point connection type, uniformity and reliability to SV packet sending and receivings propose higher requirement, newest
Specification in, it is desirable that the discrete type of SV messages is no more than 1us.
Combining unit is broadly divided into two kinds, and one is busbar combining units, and one is interval combining units.Interval merges single
Member will also receive the SV message informations that the cascade of busbar combining unit comes while sending SV messages.So being badly in need of a kind of
Point-to-point SV packet sending and receivings device and method improves point-to-point SV messages and receives while realizing to point-to-point SV packet sending and receivings
The uniformity and reliability of hair.
Invention content
The present invention proposes a kind of point-to-point SV packet sending and receivings method of combining unit, it is intended to solve to merge in the prior art single
The not high problem of member point-to-point uniformity and reliability of the SV packet sending and receivings method to SV packet sending and receivings.
In order to solve the above technical problems, the point-to-point SV packet sending and receivings method of the present invention includes the following steps：
1) procotol interface chip is initialized；
2) transceiver logic periodically inquires send in FIFO whether have SV messages inside FPGA, there is SV messages, carries out step 3)；
Otherwise, step 8) is carried out；
3) it reads message and packet parsing is obtained into sending time Ts, message is written to the transmission of procotol interface chip
Buffer area carries out step 4)；
4) it calculates SV messages transmission in procotol interface chip transmission buffer area and needs to wait for time TwIf TwLess than network
Protocol interface chip has sent the time T needed for a frame messageF, carry out step 5)；Otherwise, step 6) is carried out
5) it waits for a period of time, until TwAfter=0, the SV messages are sent, carry out step 2)；
6) inquiry procotol interface chip receives whether buffering area has SV messages, there is SV messages, carries out step 7), no
Then, step 4) is carried out
7) FPGA transceiver logics are beaten after timestamp to be written and be received to the SV messages of procotol interface chip reception buffering area
FIFO, and the SV messages sent in FIFO are sent, carry out step 2)；
8) inquiry procotol interface chip receives whether buffering area has SV messages, there is SV messages, carries out step 9)；It is no
Then, step 2) is carried out；
9) FPGA transceiver logics are beaten after timestamp to be written and be received to the SV messages of procotol interface chip reception buffering area
FIFO carries out step 2).
The procotol interface chip is DM9000C.
The SV messages sending time TsIt is the system time information T parsed according to FPGAuWith working as FPGA timer
Preceding time TnIt is calculated.
CPU is by SV message sending times TsAfter write-in FPGA is sent in FIFO after being packaged with message, fifo address pointer adds
Whether the pointer that the transceiver logic inside 1, FPGA periodically inquires transmission FIFO changes, so that it is determined that whether send in FIFO has
SV messages.
The process that FPGA transceiver logics beat the SV messages that procotol interface chip receives timestamp is：Procotol
As soon as interface chip often receives frame data, the INT signal of procotol interface chip will produce a reception interrupt signal, FPGA
Transceiver logic timestamp is stamped to this frame data in the failing edge of INT signal according to the time of timer internal.
The receiving/transmission method of the point-to-point SV messages of the present invention is passed through by the way of CPU+FPGA+ procotol interface chips
What a piece of procotol interface chip realized point-to-point SV messages simultaneously sends and receivees function.Utilize the stronger operation energy of CPU
Power is packaged SV messages, and by accurately controlling the sending time of SV messages the characteristics of FPGA high real-times, control message is sent
Uniformity, and message will be received by the high-resolution timer of FPGA and beat time stamp, and in the gap of transmission, inquired procotol and connect
Mouth chip receives buffering area, realizes the point-to-point receive capabilities of SV messages.
Using the timer synchronization whole system of FPGA internal builds, so that SV messages is sent has high uniformity, receives
Literary time discrete of transmitting messages is no more than 100ns.
Multiframe data are cached by FPGA internal builds FIFO, ensure that CPU in the case where computational load is bigger, does not go out
Existing frame losing phenomenon, improves the stability and reliability of reception.
Description of the drawings：
Fig. 1 is system realization principle figure；
Fig. 2 is that the state machine of SV packet sending and receiving logics redirects figure.
Specific implementation mode
Below in conjunction with the accompanying drawings, technical scheme of the present invention is described in detail：
The realization principle of whole system as shown in Figure 1, be mainly made of CPU, FPGA and DM9000C, CPU by bus and
FPGA carries out data interaction, and FPGA drives DM9000C to carry out the transmitting-receiving of message by the data-interface of DM9000C.FPGA is
The core that system is realized.In one 32 timers of FPGA internal builds, constant-temperature crystal oscillator provides stabilization to timer
Reliable clock, clock are 100Mhz by internal DC M frequencys multiplication, and the minimum resolution of timer can reach 10ns, ensure that
The precision and reliability of system.
System parses external synchronization time information by FPGA, and is resolved to pulse per second (PPS) and UTC time information, each
The pulse per second (PPS) of second all stamps timestamp by the timer of FPGA.The timestamp that we define pulse per second (PPS) is Tp, UTC time Tu,
CPU reads T by buspAnd Tu, and periodically read the current time T of FPGA timer internalsn, whole to realize by this method
The time synchronization function of a system.
FPGA, which is internally provided with, to be received FIFO and sends FIFO, is received FIFO for caching the SV messages received, is sent
FIFO is for caching the SV messages to be sent.
Since DM9000C is current most widely used procotol interface chip, have it is cheap, good reliability
Feature.Preferred DM9000C chips realize the transmitting-receiving of point-to-point message in the present embodiment, but not limited to this chip can also be adopted
With other procotol interface chips, such as DM9000A in the prior art.
After system electrification, FPGA first passes through each initialization of register of the internal logic by DM9000C.CPU reports SV
Text accomplishes fluently packet, and according to system time information TuWith the current time T of FPGA timern, calculate the sending time of SV messages
Ts, and by sending time TsIt is packaged together in the transmission FIFO by bus write-in FPGA with message is sent, often writes a frame FIFO
Address pointer adds 1.
The logic state machine of entire SV transmitting-receivings after the completion of DM9000C initialization as shown in Fig. 2, enter " inquiry sends FIFO "
State, whether the SV transceiver logics inside FPGA are periodically inquired sends the pointer of FIFO and changes, and does not just jump to " inquiry
DM9000C receives buffering " state.There is a message to be sent if inquiring and sending in FIFO, reads message and by packet parsing
Obtain sending time Ts, by message be written DM9000C transmission buffer area, and by send marking signal READY be set to 1, when up to
To sending time Ts, the SV messages are sent, then by READY signal clear 0.
But sending time T in order to preventsIt is long, device can be made to be in the wait state of long period, device is caused to provide
Source wastes, and the transmission of SV messages can also be calculated in the present embodiment and needs to wait for time Tw=Ts-Tn, wherein TFIt is sent for DM9000C
Time needed for complete frame message.If Tw<TF, then enter " send and wait for " state, wait for TwAfter becoming 0, by DM9000C's
It sends enabled register to be set to effectively, the transmission of a frame data is completed, then by READY signal clear 0.If TwLong enough and Tw>
TF, then logic jump to " inquiry DM9000C receive buffering " state.
" inquiry DM9000C receives buffering " state：Whether the reception buffering of inquiry DM9000C has data, if there is data,
Then state machine redirects entrance and " receives SV write-ins and receive FIFO " state.DM9000C often receives a frame data, the INT letters of DM9000C
A reception interrupt signal number is just will produce, the transceiver logic of FPGA will be according to the time of timer internal, under INT signal
Then drop encapsulates timestamp and SV messages together along timestamp is stamped to this frame data, write-in receives FIFO, and waiting for CPU is fixed
When read.After the reception for completing a frame data, by judging READY for 1 or 0, confirm that next state is that " inquiry is sent
FIFO ", still " inquiry DM9000C receives buffering ".
The present embodiment reaches the timer of 10ns by FPGA internal build precision, and the time for realizing CPU and FPGA is same
Function is walked, SV messages are packaged using the stronger operational capabilities of CPU, by accurately controlling SV reports the characteristics of FPGA high real-times
The sending time of text, and message will be received by the high-resolution timer of FPGA and beat time stamp.Theoretically the time error of message is not
Can be more than 20ns, it is contemplated that CPU calculates factors, the packet sending and receiving uniformities of whole system such as error and does not exceed 100ns, to
Realize a kind of receiving/transmission method of the point-to-point SV messages of high uniformity.
Claims (5)
1. a kind of receiving/transmission method of the point-to-point SV messages of combining unit, which is characterized in that include the following steps：
1) procotol interface chip is initialized；
2) transceiver logic periodically inquires send in FIFO whether have SV messages inside FPGA, there is SV messages, carries out step 3)；It is no
Then, step 8) is carried out；
3) it reads message and packet parsing is obtained into sending time Ts, message is written to the transmission caching of procotol interface chip
Area carries out step 4)；
4) it calculates SV messages transmission in procotol interface chip transmission buffer area and needs to wait for time TwIf TwLess than procotol
Interface chip has sent the time T needed for a frame messageF, carry out step 5)；Otherwise, step 6) is carried out
5) it waits for a period of time, until TwAfter=0, the SV messages are sent, carry out step 2)；
6) inquiry procotol interface chip receives whether buffering area has SV messages, there is SV messages, carries out step 7), otherwise, into
Row step 4)
7) write-in receives FIFO after FPGA transceiver logics beat timestamp to the SV messages of procotol interface chip reception buffering area,
And send the SV messages sent in FIFO, carry out step 2)；
8) inquiry procotol interface chip receives whether buffering area has SV messages, there is SV messages, carries out step 9)；Otherwise, into
Row step 2)；
9) write-in receives FIFO after FPGA transceiver logics beat timestamp to the SV messages of procotol interface chip reception buffering area,
Carry out step 2).
2. the receiving/transmission method of the point-to-point SV messages of combining unit according to claim 1, which is characterized in that the procotol
Interface chip is DM9000C.
3. the receiving/transmission method of the point-to-point SV messages of combining unit according to claim 1, which is characterized in that the SV messages hair
Send time TsIt is the system time information T parsed according to FPGAuWith the current time T of FPGA timernIt is calculated.
4. the receiving/transmission method of the point-to-point SV messages of combining unit according to claim 1, which is characterized in that CPU is by SV messages
Sending time TsAfter write-in FPGA is sent in FIFO after being packaged with message, fifo address pointer adds the transceiver logic inside 1, FPGA
Whether the pointer that periodically inquiry sends FIFO changes, so that it is determined that sending in FIFO whether have SV messages.
5. the receiving/transmission method of the point-to-point SV messages of combining unit according to claim 1, which is characterized in that FPGA transceiver logics
The process for beating the SV messages that procotol interface chip receives timestamp is：Procotol interface chip often receives a frame number
According to the INT signal of procotol interface chip just will produce a reception interrupt signal, and the transceiver logic of FPGA will be according to inside
The time of timer stamps timestamp in the failing edge of INT signal to this frame data.
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| CN106201970B (en) * | 2016-06-22 | 2020-09-29 | 广东电网有限责任公司电力科学研究院 | Information acquisition device and method |
| CN106961396B (en) * | 2017-03-21 | 2019-01-22 | 中国南方电网有限责任公司电网技术研究中心 | Based on the method and apparatus that caching realizes SV Message processing in FPGA piece |
| CN108667852B (en) * | 2018-05-22 | 2021-02-12 | 广州穗华能源科技有限公司 | Method for framing and sending SV message by FPGA |
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| CN103209137A (en) * | 2013-03-21 | 2013-07-17 | 国家电网公司 | Configurable high-accuracy control system of time interval frame release Ethernet interface |
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| CN103605023A (en) * | 2013-11-20 | 2014-02-26 | 国家电网公司 | Method and device for measuring merging unit time characteristics |
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