CN104993821A - Low phase noise phase-locked loop circuit - Google Patents
Low phase noise phase-locked loop circuit Download PDFInfo
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- CN104993821A CN104993821A CN201510405707.5A CN201510405707A CN104993821A CN 104993821 A CN104993821 A CN 104993821A CN 201510405707 A CN201510405707 A CN 201510405707A CN 104993821 A CN104993821 A CN 104993821A
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Abstract
The invention discloses a low phase noise phase-locked loop circuit, comprising a phase detector, a loop filter, a voltage controlled oscillator, a coupler, a power amplifier and a mixer. A reference input end of the phase detector is connected with an external reference source. An output end of the phase detector is connected with an input end of the loop filter. An output end of the loop filter is connected with an input end of the voltage controlled oscillator. An output end of the voltage controlled oscillator is connected with an input end of the coupler. The mixer has a local oscillation end, a radio frequency end and a middle frequency end. The middle frequency end of the mixer is connected with a radio frequency input end of the phase detector. An input end of the power amplifier is connected with a coupling end of the coupler. An output end of the power amplifier is connected with the radio frequency end of the mixer. The local oscillation end of the mixer is connected with an external offset source. The radio frequency end of the mixer is connected with the output end of the voltage controlled oscillator. The middle frequency end of the mixer is connected with the radio frequency input end of the phase detector. The low phase noise phase-locked loop circuit has the advantages of lowering the phase noise of the phase-locked loop circuit in a loop bandwidth.
Description
Technical field
The present invention relates to a kind of phase-locked loop circuit, especially relate to a kind of Low phase noise phase-locked loop circuit.
Background technology
Existing phase-locked loop circuit is mainly used in frequency synthesizer, by the frequency multiplication of external reference input signal, makes frequency synthesizer obtain higher rate-adaptive pacemaker.Existing phase-locked loop circuit comprises phase discriminator (Phase Detector), loop filter (Loop Filter), voltage controlled oscillator (Voltage Controlled Oscillator), frequency divider (FrequencyDivider) and coupler, the reference input of phase discriminator is connected with external reference input signal, the output of phase discriminator is connected with the input of loop filter, the output of loop filter is connected with the input of voltage controlled oscillator, the output of voltage controlled oscillator is connected with the input of coupler, the coupled end of coupler is connected with the input of frequency divider, the output of frequency divider is connected with the rf inputs of phase discriminator.
Existing phase-locked loop circuit operation principle as shown in Figure 1.
If external reference input signal is u
it (), phase place is θ
i(t), frequency f
i(t); If phase discriminator output error signal is u
ε(t); If the output signal of voltage controlled oscillator is u
ot (), phase place is θ
ot (), frequency is f
o(t); If output signal of frequency divider is u
rt (), phase place is θ
rt (), frequency is f
r(t).Then the phase-locked loop circuit course of work is as follows: phase discriminator is by comparing external reference input signal u
isignal u after (t) and frequency divider process
rthe phase theta of (t)
i(t) and θ
rafter (t), the phase difference of the two is converted to linearity error electric current or error voltage signal u
ε(t), then through loop filter filtering u
εpurer tuning voltage u is obtained after the ripple interference of (t)
dt (), voltage controlled oscillator generates the signal u of required frequency under the effect of tuning voltage
ot (), as external reference frequency input signal f
i(t) and output signal of frequency divider frequency f
rwhen () is equal t, maintenance is also fixed by their phase difference, and the voltage-controlled whole signal maintenance lock-out state swinging device and export, now has f
o(t)=f
i(t) × N.
When analyzing the noise of existing phase-locked loop circuit, phase-locked loop can be equivalent to a linear system, obtain existing phase-locked loop phase noise Mathematical Modeling as shown in Figure 2.Wherein Δ θ
is () is the phase jitter of external reference input signal, V
npDfor the noise voltage of phase discriminator, Δ θ
vCOs () is voltage controlled oscillator phase jitter, Δ θ
ns phase jitter that () is frequency divider, K
dfor phase detector gain, the transmission coefficient that F (s) is loop filter, K
0for the voltage-controlled sensitivity of voltage controlled oscillator, K
0/ s is the transmission coefficient of voltage controlled oscillator, and N/s is frequency divider transmission coefficient.
When the reference-input signal phase noise of existing phase-locked loop is uncorrelated with the phase noise of phase discriminator, voltage controlled oscillator and frequency divider, the phase noise of existing phase-locked loop can linear principle of stacking obtain:
Wherein
and there is conventional estimation equation to be
Therefore in loop bandwidth,
be expressed as with logarithm
Namely the proper phase noise of existing phase-locked loop and the phase noise of external reference input signal will worsen 20lg (N) dB.
Outside loop bandwidth,
the phase noise of phase-locked loop determines primarily of the phase noise of voltage controlled oscillator.
There is following problem in existing phase-locked loop circuit: in loop bandwidth, the phase noise that phase-locked loop circuit is intrinsic and external reference input signal phase noise deterioration degree depend on the frequency division multiple of frequency divider, and frequency divider frequency division multiple is higher, the phase noise of phase-locked loop circuit worsens more serious, due to the frequency of output signal frequency divided by external reference input signal that frequency divider frequency dividing ratio is phase-locked loop circuit, external reference input signal is generally produced by crystal oscillator, the frequency of the signal that the price of crystal oscillator is produced by it determines, frequency is lower, crystal oscillator cost is lower, therefore the crystal oscillator that the usual frequency of utilization of external reference input signal is lower, be generally 1MHz ~ 500MHz, and the frequency of the output signal of phase-locked loop circuit is higher, general at more than 1GHz, even can reach millimere-wave band (30GHz ~ 300GHz), in existing phase-locked loop circuit, frequency divider frequency dividing ratio is higher, the proper phase noise of phase-locked loop circuit and the phase noise of external reference input signal is caused to worsen thus also comparatively serious.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of Low phase noise phase-locked loop circuit.Offset source signal is introduced to reduce frequency dividing ratio by frequency mixer (Mixer) in this Low phase noise phase-locked loop circuit road, phase-locked loop circuit proper phase noise and external reference input signal phase noise deterioration degree are reduced, thus reduces the phase noise of phase-locked loop circuit in loop bandwidth.
The present invention solves the technical scheme that above technical problem adopts: a kind of Low phase noise phase-locked loop circuit, comprises phase discriminator, loop filter circuit, voltage controlled oscillator, coupling circuit, power amplification circuit, mixting circuit.Described phase discriminator comprises reference input, rf inputs and charge pump outputs (Charge Pump Output), described loop filter circuit comprises input and output, described voltage controlled oscillator comprises tuning voltage input and radio-frequency (RF) output end, described coupling circuit comprises input, coupled end, straight-through end, described power amplification circuit comprises input and output, and described mixting circuit comprises local oscillator end, radio-frequency head and intermediate frequency end.Described phase discriminator reference input is connected with external reference source, described phase discriminator rf inputs is connected with described mixting circuit intermediate frequency end, the charge pump outputs of described phase discriminator is connected with described loop filter circuit input, the output of described loop filter circuit is connected with the tuning voltage input of voltage controlled oscillator, the radio-frequency (RF) output end of described voltage controlled oscillator is connected with the input of described coupling circuit, the straight-through end of described coupling circuit is phase-locked loop output, the coupled end of described coupling circuit is connected with the input of described power amplification circuit, the output of described power amplification circuit is connected with the radio-frequency head of described mixting circuit, the local oscillator end of described frequency mixer is connected with external deviation source.
Described phase discriminator comprises the first resistance, first electric capacity and model are the phase discriminator chip of ADF4002, one end ground connection of the first described resistance, the other end of the first described resistance is connected with the 19th pin of described phase discriminator chip, one end ground connection of the first described electric capacity, the other end of the first described electric capacity is connected with the 4th pin of described phase discriminator chip, 6th pin of described phase discriminator chip, 7th pin, 11st pin, 16th pin, 17th pin and the 18th pin all access 3V voltage, 1st pin of described phase discriminator chip, 2nd pin, 3rd pin, 9th pin and the equal ground connection of the 10th pin, 5th pin of described phase discriminator chip is the rf inputs of described phase discriminator, 8th pin of described phase discriminator chip is the reference input of described phase discriminator, 20th pin of described phase discriminator chip is the output of described phase discriminator.In this circuit, the phase noise of phase discriminator chip ADF4002 is very low, can ensure that phase-locked loop proper phase noise is in reduced levels.
Described loop filter comprises the second electric capacity, 3rd electric capacity, 4th electric capacity, second resistance and the 3rd resistance, one end of the second described electric capacity, one end of the second described resistance is connected with one end of the 3rd described resistance and its link is the input of described loop filter, the other end ground connection of the second described electric capacity, the second described resistance other end is connected with one end of the 3rd described electric capacity, the other end ground connection of the 3rd described electric capacity, the other end of the 3rd described resistance is connected with one end of the 4th described electric capacity and its link is the output of described loop filter, the other end ground connection of the 4th described electric capacity.In this circuit, loop filter adopts passive loop filter structure simple, has further inhibitory action to phase noise.
Described voltage controlled oscillator comprises the voltage controlled oscillator chip that the 5th electric capacity and model are HMC917LP3, one end of the 5th described electric capacity is connected with the 16th pin of described voltage controlled oscillator chip, the other end of the 5th described electric capacity is the output of described voltage controlled oscillator, 20th pin access 3V voltage of described voltage controlled oscillator chip, 15th pin ground connection of described voltage controlled oscillator chip, the 22nd pin of described voltage controlled oscillator chip is the input of described voltage controlled oscillator.In this circuit, voltage controlled oscillator output signal power and frequency stabilization, have less phase noise.
Described coupler comprises the first microstrip line and second microstrip line of parallel interval setting, the length of the first described microstrip line is 4.8mm, the width of the first described microstrip line is 1.1mm, the length of the second described microstrip line is 4.8mm, the width of the second described microstrip line is 1.1mm, between the first described microstrip line and the second described microstrip line, gap width is 0.2mm, one end of the first described microstrip line is the input of described coupler, the other end of the first described microstrip line is the straight-through end of described coupler, one end of the input of the close described coupler of the second described microstrip line is the coupled end of described coupler, the other end ground connection of the second described microstrip line.This circuit loss is less, and structure is simple, and size is less, is easy to integrated.
Power amplifier comprises the 4th resistance, 5th resistance, 6th electric capacity, 7th electric capacity, 8th electric capacity, 9th electric capacity, first inductance and model are the power amplifier chip of MGA30689, one end of the 4th described resistance, one end of the 5th described resistance is connected with one end of the 6th described electric capacity and its link is the input of described power amplification circuit, the other end of the 4th described resistance and the equal ground connection of the other end of the 5th described resistance, the 6th described electric capacity other end is connected with the 1st pin of described power amplifier chip, 2nd pin ground connection of described power amplifier chip, one end of the first described inductance is connected with the 3rd pin of described power amplifier chip and its link is the output of described power amplification circuit, 5V voltage is all accessed in the other end of the first described inductance and one end of the 7th described electric capacity, the other end ground connection of the 7th described electric capacity, one end access 5V voltage of the 8th described electric capacity, the other end ground connection of the 8th described electric capacity, one end access 5V voltage of the 9th described electric capacity, the other end ground connection of the 9th described electric capacity.This circuit dynamic range is wider, and gain is comparatively large, and noise is low, and can ensure that the signal power after amplifying is in the scope of the input power of the radio-frequency head of frequency mixer, simultaneously cheap, structure is simple.
Described frequency mixer comprises the mixing chip that the tenth electric capacity and model are HMC213, the tenth described electric capacity one end is the radio-frequency head of described frequency mixer, the other end of the tenth described electric capacity is connected with the 7th pin of described mixing chip, 1st pin of described mixing chip, the 3rd pin, the 6th pin and the equal ground connection of the 8th pin, 2nd pin of described mixing chip is the local oscillator end of described frequency mixer, and the 5th pin of described mixing chip is the intermediate frequency end of described frequency mixer.This current phase noise is low, and conversion loss is low, and structure is simple simultaneously, cheap.
Compared with prior art, the invention has the advantages that and introduce external deviation source signal by arranging frequency mixer, the output signal of external deviation source signal and voltage controlled oscillator carries out mixing in frequency mixer, the frequency of the intermediate-freuqncy signal produced after mixing is equal with the reference-input signal frequency of phase discriminator, being equivalent to frequency dividing ratio is 1, thus, in loop bandwidth, the proper phase noise of phase-locked loop and the phase noise of external reference input signal can not change, the phase noise of the output signal of whole phase-locked loop circuit is only the intrinsic phase noise of loop, the linear superposition of the phase noise of reference-input signal and the phase noise of external deviation source signal, thus reduce the phase noise of the output signal of phase-locked loop circuit.
Accompanying drawing explanation
Fig. 1 is the theory diagram of existing phase-locked loop circuit;
Fig. 2 is the phase noise Mathematical Modeling of existing phase-locked loop circuit;
Fig. 3 is the theory diagram of low-noise phase-locked loop circuit of the present invention;
Fig. 4 is the circuit diagram of phase discriminator of the present invention;
Fig. 5 is the circuit diagram of loop filter of the present invention;
Fig. 6 is the circuit diagram of voltage controlled oscillator of the present invention;
Fig. 7 is the circuit diagram of coupler of the present invention;
Fig. 8 is the circuit diagram of amplifier of the present invention;
Fig. 9 is the circuit diagram of frequency mixer of the present invention;
Figure 10 is phase noise Mathematical Modeling of the present invention.
Embodiment
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
Embodiment one: as shown in Figure 3, a kind of Low phase noise phase-locked loop circuit, comprise phase discriminator, loop filter, voltage controlled oscillator and coupler, phase discriminator has reference input, rf inputs and output, coupler has input, coupled end and straight-through end, the reference input of phase discriminator is connected with external reference source, the output of phase discriminator is connected with the input of loop filter, the output of loop filter is connected with the input of voltage controlled oscillator, the output of voltage controlled oscillator is connected with the input of coupler, the straight-through end of coupler is the output of this Low phase noise phase-locked loop circuit, a kind of Low phase noise phase-locked loop circuit also comprises power amplifier and frequency mixer, frequency mixer has local oscillator end, radio-frequency head and intermediate frequency end, the intermediate frequency end of frequency mixer is connected with the rf inputs of phase discriminator, the input of power amplifier is connected with the coupled end of coupler, the output of power amplifier is connected with the radio-frequency head of frequency mixer, the local oscillator end of frequency mixer is connected with external deviation source, the radio-frequency head of frequency mixer is connected with the output of voltage controlled oscillator, the intermediate frequency end of frequency mixer is connected with the rf inputs of phase discriminator.
Embodiment two: as shown in Figure 3, a kind of Low phase noise phase-locked loop circuit, comprise phase discriminator, loop filter, voltage controlled oscillator and coupler, phase discriminator has reference input, rf inputs and output, coupler has input, coupled end and straight-through end, the reference input of phase discriminator is connected with external reference source, the output of phase discriminator is connected with the input of loop filter, the output of loop filter is connected with the input of voltage controlled oscillator, the output of voltage controlled oscillator is connected with the input of coupler, the straight-through end of coupler is the output of this Low phase noise phase-locked loop circuit, a kind of Low phase noise phase-locked loop circuit also comprises power amplifier and frequency mixer, frequency mixer has local oscillator end, radio-frequency head and intermediate frequency end, the intermediate frequency end of frequency mixer is connected with the rf inputs of phase discriminator, the input of power amplifier is connected with the coupled end of coupler, the output of power amplifier is connected with the radio-frequency head of frequency mixer, the local oscillator end of frequency mixer is connected with external deviation source, the radio-frequency head of frequency mixer is connected with the output of voltage controlled oscillator, the intermediate frequency end of frequency mixer is connected with the rf inputs of phase discriminator.
In the present embodiment, as shown in Figure 4, phase discriminator comprises the first resistance R1, first electric capacity C1 and model are the phase discriminator chip U1 of ADF4002, one end ground connection of the first resistance R1, the other end of the first resistance R1 is connected with the 19th pin of phase discriminator chip U1, one end ground connection of the first electric capacity C1, the other end of the first electric capacity C1 is connected with the 4th pin of phase discriminator chip U1, 6th pin of phase discriminator chip U1, 7th pin, 11st pin, 16th pin, 17th pin and the 18th pin all access 3V voltage, 1st pin of phase discriminator chip U1, 2nd pin, 3rd pin, 9th pin and the equal ground connection of the 10th pin, 5th pin of phase discriminator chip U1 is the rf inputs of phase discriminator, 8th pin of phase discriminator chip U1 is the reference input of phase discriminator, 20th pin of phase discriminator chip U1 is the output of phase discriminator.
Embodiment three: as shown in Figure 3, a kind of Low phase noise phase-locked loop circuit, comprise phase discriminator, loop filter, voltage controlled oscillator and coupler, phase discriminator has reference input, rf inputs and output, coupler has input, coupled end and straight-through end, the reference input of phase discriminator is connected with external reference source, the output of phase discriminator is connected with the input of loop filter, the output of loop filter is connected with the input of voltage controlled oscillator, the output of voltage controlled oscillator is connected with the input of coupler, the straight-through end of coupler is the output of this Low phase noise phase-locked loop circuit, a kind of Low phase noise phase-locked loop circuit also comprises power amplifier and frequency mixer, frequency mixer has local oscillator end, radio-frequency head and intermediate frequency end, the intermediate frequency end of frequency mixer is connected with the rf inputs of phase discriminator, the input of power amplifier is connected with the coupled end of coupler, the output of power amplifier is connected with the radio-frequency head of frequency mixer, the local oscillator end of frequency mixer is connected with external deviation source, the radio-frequency head of frequency mixer is connected with the output of voltage controlled oscillator, the intermediate frequency end of frequency mixer is connected with the rf inputs of phase discriminator.
In the present embodiment, as shown in Figure 4, phase discriminator comprises the first resistance R1, first electric capacity C1 and model are the phase discriminator chip U1 of ADF4002, one end ground connection of the first resistance R1, the other end of the first resistance R1 is connected with the 19th pin of phase discriminator chip U1, one end ground connection of the first electric capacity C1, the other end of the first electric capacity C1 is connected with the 4th pin of phase discriminator chip U1, 6th pin of phase discriminator chip U1, 7th pin, 11st pin, 16th pin, 17th pin and the 18th pin all access 3V voltage, 1st pin of phase discriminator chip U1, 2nd pin, 3rd pin, 9th pin and the equal ground connection of the 10th pin, 5th pin of phase discriminator chip U1 is the rf inputs of phase discriminator, 8th pin of phase discriminator chip U1 is the reference input of phase discriminator, 20th pin of phase discriminator chip U1 is the output of phase discriminator.
In the present embodiment, as shown in Figure 5, loop filter comprises the second electric capacity C2, 3rd electric capacity C3, 4th electric capacity C4, second resistance R2 and the 3rd resistance R3, one end of second electric capacity C2, one end of second resistance R2 is connected with one end of the 3rd resistance R3 and its link is the input of loop filter, the other end ground connection of the second electric capacity C2, the second resistance R2 other end is connected with one end of the 3rd electric capacity C3, the other end ground connection of the 3rd electric capacity C3, the other end of the 3rd resistance R3 is connected with one end of the 4th electric capacity C4 and its link is the output of loop filter, the other end ground connection of the 4th electric capacity C4.
Embodiment four: as shown in Figure 3, a kind of Low phase noise phase-locked loop circuit, comprise phase discriminator, loop filter, voltage controlled oscillator and coupler, phase discriminator has reference input, rf inputs and output, coupler has input, coupled end and straight-through end, the reference input of phase discriminator is connected with external reference source, the output of phase discriminator is connected with the input of loop filter, the output of loop filter is connected with the input of voltage controlled oscillator, the output of voltage controlled oscillator is connected with the input of coupler, the straight-through end of coupler is the output of this Low phase noise phase-locked loop circuit, a kind of Low phase noise phase-locked loop circuit also comprises power amplifier and frequency mixer, frequency mixer has local oscillator end, radio-frequency head and intermediate frequency end, the intermediate frequency end of frequency mixer is connected with the rf inputs of phase discriminator, the input of power amplifier is connected with the coupled end of coupler, the output of power amplifier is connected with the radio-frequency head of frequency mixer, the local oscillator end of frequency mixer is connected with external deviation source, the radio-frequency head of frequency mixer is connected with the output of voltage controlled oscillator, the intermediate frequency end of frequency mixer is connected with the rf inputs of phase discriminator.
In the present embodiment, as shown in Figure 4, phase discriminator comprises the first resistance R1, first electric capacity C1 and model are the phase discriminator chip U1 of ADF4002, one end ground connection of the first resistance R1, the other end of the first resistance R1 is connected with the 19th pin of phase discriminator chip U1, one end ground connection of the first electric capacity C1, the other end of the first electric capacity C1 is connected with the 4th pin of phase discriminator chip U1, 6th pin of phase discriminator chip U1, 7th pin, 11st pin, 16th pin, 17th pin and the 18th pin all access 3V voltage, 1st pin of phase discriminator chip U1, 2nd pin, 3rd pin, 9th pin and the equal ground connection of the 10th pin, 5th pin of phase discriminator chip U1 is the rf inputs of phase discriminator, 8th pin of phase discriminator chip U1 is the reference input of phase discriminator, 20th pin of phase discriminator chip U1 is the output of phase discriminator.
In the present embodiment, as shown in Figure 5, loop filter comprises the second electric capacity C2, 3rd electric capacity C3, 4th electric capacity C4, second resistance R2 and the 3rd resistance R3, one end of second electric capacity C2, one end of second resistance R2 is connected with one end of the 3rd resistance R3 and its link is the input of loop filter, the other end ground connection of the second electric capacity C2, the second resistance R2 other end is connected with one end of the 3rd electric capacity C3, the other end ground connection of the 3rd electric capacity C3, the other end of the 3rd resistance R3 is connected with one end of the 4th electric capacity C4 and its link is the output of loop filter, the other end ground connection of the 4th electric capacity C4.
In the present embodiment, as shown in Figure 6, voltage controlled oscillator comprises the voltage controlled oscillator chip U2 that the 5th electric capacity C5 and model are HMC917LP3, one end of 5th electric capacity C5 is connected with the 16th pin of voltage controlled oscillator chip U2, the other end of the 5th electric capacity C5 is the output of voltage controlled oscillator, the 20th pin access 3V voltage of voltage controlled oscillator chip U2, the 15th pin ground connection of voltage controlled oscillator chip U2, the 22nd pin of voltage controlled oscillator chip U2 is the input of voltage controlled oscillator.
Embodiment five: as shown in Figure 3, a kind of Low phase noise phase-locked loop circuit, comprise phase discriminator, loop filter, voltage controlled oscillator and coupler, phase discriminator has reference input, rf inputs and output, coupler has input, coupled end and straight-through end, the reference input of phase discriminator is connected with external reference source, the output of phase discriminator is connected with the input of loop filter, the output of loop filter is connected with the input of voltage controlled oscillator, the output of voltage controlled oscillator is connected with the input of coupler, the straight-through end of coupler is the output of this Low phase noise phase-locked loop circuit, a kind of Low phase noise phase-locked loop circuit also comprises power amplifier and frequency mixer, frequency mixer has local oscillator end, radio-frequency head and intermediate frequency end, the intermediate frequency end of frequency mixer is connected with the rf inputs of phase discriminator, the input of power amplifier is connected with the coupled end of coupler, the output of power amplifier is connected with the radio-frequency head of frequency mixer, the local oscillator end of frequency mixer is connected with external deviation source, the radio-frequency head of frequency mixer is connected with the output of voltage controlled oscillator, the intermediate frequency end of frequency mixer is connected with the rf inputs of phase discriminator.
In the present embodiment, as shown in Figure 4, phase discriminator comprises the first resistance R1, first electric capacity C1 and model are the phase discriminator chip U1 of ADF4002, one end ground connection of the first resistance R1, the other end of the first resistance R1 is connected with the 19th pin of phase discriminator chip U1, one end ground connection of the first electric capacity C1, the other end of the first electric capacity C1 is connected with the 4th pin of phase discriminator chip U1, 6th pin of phase discriminator chip U1, 7th pin, 11st pin, 16th pin, 17th pin and the 18th pin all access 3V voltage, 1st pin of phase discriminator chip U1, 2nd pin, 3rd pin, 9th pin and the equal ground connection of the 10th pin, 5th pin of phase discriminator chip U1 is the rf inputs of phase discriminator, 8th pin of phase discriminator chip U1 is the reference input of phase discriminator, 20th pin of phase discriminator chip U1 is the output of phase discriminator.
In the present embodiment, as shown in Figure 5, loop filter comprises the second electric capacity C2, 3rd electric capacity C3, 4th electric capacity C4, second resistance R2 and the 3rd resistance R3, one end of second electric capacity C2, one end of second resistance R2 is connected with one end of the 3rd resistance R3 and its link is the input of loop filter, the other end ground connection of the second electric capacity C2, the second resistance R2 other end is connected with one end of the 3rd electric capacity C3, the other end ground connection of the 3rd electric capacity C3, the other end of the 3rd resistance R3 is connected with one end of the 4th electric capacity C4 and its link is the output of loop filter, the other end ground connection of the 4th electric capacity C4.
In the present embodiment, as shown in Figure 6, voltage controlled oscillator comprises the voltage controlled oscillator chip U2 that the 5th electric capacity C5 and model are HMC917LP3, one end of 5th electric capacity C5 is connected with the 16th pin of voltage controlled oscillator chip U2, the other end of the 5th electric capacity C5 is the output of voltage controlled oscillator, the 20th pin access 3V voltage of voltage controlled oscillator chip U2, the 15th pin ground connection of voltage controlled oscillator chip U2, the 22nd pin of voltage controlled oscillator chip U2 is the input of voltage controlled oscillator.
In the present embodiment, as shown in Figure 7, coupler comprises the first microstrip line and second microstrip line of parallel interval setting, the length L of the first microstrip line is 4.8mm, the width W of the first microstrip line is 1.1mm, the length L of the second microstrip line is 4.8mm, the width W of the second microstrip line is 1.1mm, between the first microstrip line and the second microstrip line, gap width S is 0.2mm, one end of first microstrip line is the input of coupler, the other end of the first microstrip line is the straight-through end of coupler, one end of the input of the close coupler of the second microstrip line is the coupled end of coupler, the other end ground connection of the second microstrip line.
In the present embodiment, as shown in Figure 8, power amplifier comprises the 4th resistance R4, 5th resistance R5, 6th electric capacity C6, 7th electric capacity C7, 8th electric capacity C8, 9th electric capacity C9, first inductance L 1 and model are the power amplifier chip U3 of MGA30689, one end of 4th resistance R4, one end of 5th resistance R5 is connected with one end of the 6th electric capacity C6 and its link is the input of power amplification circuit, the other end of the 4th resistance R4 and the equal ground connection of the other end of the 5th resistance R5, the 6th electric capacity C6 other end is connected with the 1st pin of power amplifier chip U3, the 2nd pin ground connection of power amplifier chip U3, one end of first inductance L 1 is connected with the 3rd pin of power amplifier chip U3 and its link is the output of power amplification circuit, 5V voltage is all accessed in the other end of the first inductance L 1 and one end of the 7th electric capacity C7, the other end ground connection of the 7th electric capacity C7, one end access 5V voltage of the 8th electric capacity C8, the other end ground connection of the 8th electric capacity C8, one end access 5V voltage of the 9th electric capacity C9, the other end ground connection of the 9th electric capacity C9.
In the present embodiment, as shown in Figure 9, frequency mixer comprises the mixing chip U4 that the tenth electric capacity C10 and model are HMC213, tenth electric capacity C10 one end is the radio-frequency head of frequency mixer, the other end of the tenth electric capacity C10 is connected with the 7th pin of mixing chip U4,1st pin of mixing chip U4, the 3rd pin, the 6th pin and the equal ground connection of the 8th pin, the 2nd pin of mixing chip U4 is the local oscillator end of frequency mixer, and the 5th pin of mixing chip U4 is the intermediate frequency end of frequency mixer.
As shown in Figure 10, the operation principle of the Low phase noise phase-locked loop circuit of the present embodiment is: phase discriminator is by after the phase place of intermediate-freuqncy signal that compares external reference input signal and frequency mixer and export, convert the phase difference of the two to linearity error voltage signal, purer tuning voltage signal is obtained again after the ripple interference of this linearity error voltage signal of loop filter filtering, voltage controlled oscillator exports the signal of required frequency under the effect of tuning voltage signal, this signal carries out mixing as the radio-frequency input signals of frequency mixer and external deviation source signal and obtains mixer intermediate-frequency and output signal, when external reference frequency input signal and frequency mixer export IF signal frequency equal time, maintenance is also fixed by their phase difference, the signal that voltage controlled oscillator exports keeps lock-out state, thus make phase-locked loop circuit obtain stable output signal.In Figure 10, Δ θ
is () is the phase jitter of external reference input signal, V
npDfor the noise voltage of phase discriminator, Δ θ
vCOs () is voltage controlled oscillator phase jitter, Δ θ
ns phase jitter that () is frequency divider, K
dfor phase detector gain, the transmission coefficient that F (s) is loop filter, K
0for the voltage-controlled sensitivity of voltage controlled oscillator, K
0/ s is the transmission coefficient of voltage controlled oscillator, Δ θ
los phase jitter that () introduces for offset source, therefore, the phase noise of the Low phase noise phase-locked loop circuit of the present embodiment can be expressed as:
Wherein
its conventional estimation equation is:
Therefore have in loop bandwidth
The phase noise of the Low phase noise phase-locked loop circuit of the present embodiment is only made an uproar mutually with external reference input signal, the intrinsic of Low phase noise phase-locked loop is made an uproar and offset source is made an uproar relevant mutually mutually.And outside loop bandwidth,
the phase noise of Low phase noise phase-locked loop circuit determines primarily of voltage controlled oscillator.Formula (4) has been taken the logarithm
When the phase noise of offset source is far smaller than the proper phase noise of Low phase noise phase-locked loop, namely
Formula (5) can be reduced to
therefore, the phase noise of Low phase noise phase-locked loop circuit in loop bandwidth of the present embodiment reduces 20lg (N).
Claims (7)
1. a Low phase noise phase-locked loop circuit, comprise phase discriminator, loop filter, voltage controlled oscillator and coupler, described phase discriminator has reference input, rf inputs and output, described coupler has input, coupled end and straight-through end, the reference input of described phase discriminator is connected with external reference source, the output of described phase discriminator is connected with the input of described loop filter, the output of described loop filter is connected with the input of described voltage controlled oscillator, the output of described voltage controlled oscillator is connected with the input of described coupler, the straight-through end of described coupler is the output of described Low phase noise phase-locked loop circuit, it is characterized in that described Low phase noise phase-locked loop circuit also comprises power amplifier and frequency mixer, described frequency mixer has local oscillator end, radio-frequency head and intermediate frequency end, the intermediate frequency end of described frequency mixer is connected with the rf inputs of described phase discriminator, the input of described power amplifier is connected with the coupled end of described coupler, the output of described power amplifier is connected with the radio-frequency head of described frequency mixer, the local oscillator end of described frequency mixer is connected with external deviation source, the radio-frequency head of described frequency mixer is connected with the output of described voltage controlled oscillator, the intermediate frequency end of described frequency mixer is connected with the rf inputs of described phase discriminator.
2. a kind of Low phase noise phase-locked loop circuit according to claim 1, it is characterized in that described phase discriminator comprises the first resistance, first electric capacity and model are the phase discriminator chip of ADF4002, one end ground connection of the first described resistance, the other end of the first described resistance is connected with the 19th pin of described phase discriminator chip, one end ground connection of the first described electric capacity, the other end of the first described electric capacity is connected with the 4th pin of described phase discriminator chip, 6th pin of described phase discriminator chip, 7th pin, 11st pin, 16th pin, 17th pin and the 18th pin all access 3V voltage, 1st pin of described phase discriminator chip, 2nd pin, 3rd pin, 9th pin and the equal ground connection of the 10th pin, 5th pin of described phase discriminator chip is the rf inputs of described phase discriminator, 8th pin of described phase discriminator chip is the reference input of described phase discriminator, 20th pin of described phase discriminator chip is the output of described phase discriminator.
3. a kind of Low phase noise phase-locked loop circuit according to claim 1, it is characterized in that described loop filter comprises the second electric capacity, 3rd electric capacity, 4th electric capacity, second resistance and the 3rd resistance, one end of the second described electric capacity, one end of the second described resistance is connected with one end of the 3rd described resistance and its link is the input of described loop filter, the other end ground connection of the second described electric capacity, the second described resistance other end is connected with one end of the 3rd described electric capacity, the other end ground connection of the 3rd described electric capacity, the other end of the 3rd described resistance is connected with one end of the 4th described electric capacity and its link is the output of described loop filter, the other end ground connection of the 4th described electric capacity.
4. a kind of Low phase noise phase-locked loop circuit according to claim 1, it is characterized in that described voltage controlled oscillator comprises the voltage controlled oscillator chip that the 5th electric capacity and model are HMC917LP3, one end of the 5th described electric capacity is connected with the 16th pin of described voltage controlled oscillator chip, the other end of the 5th described electric capacity is the output of described voltage controlled oscillator, 20th pin access 3V voltage of described voltage controlled oscillator chip, 15th pin ground connection of described voltage controlled oscillator chip, 22nd pin of described voltage controlled oscillator chip is the input of described voltage controlled oscillator.
5. a kind of Low phase noise phase-locked loop circuit according to claim 1, it is characterized in that described coupler comprises the first microstrip line and second microstrip line of parallel interval setting, the length of the first described microstrip line is 4.8mm, the width of the first described microstrip line is 1.1mm, the length of the second described microstrip line is 4.8mm, the width of the second described microstrip line is 1.1mm, between the first described microstrip line and the second described microstrip line, gap width is 0.2mm, one end of the first described microstrip line is the input of described coupler, the other end of the first described microstrip line is the straight-through end of described coupler, one end of the input of the close described coupler of the second described microstrip line is the coupled end of described coupler, the other end ground connection of the second described microstrip line.
6. a kind of Low phase noise phase-locked loop circuit according to claim 1, it is characterized in that power amplifier comprises the 4th resistance, 5th resistance, 6th electric capacity, 7th electric capacity, 8th electric capacity, 9th electric capacity, first inductance and model are the power amplifier chip of MGA30689, one end of the 4th described resistance, one end of the 5th described resistance is connected with one end of the 6th described electric capacity and its link is the input of described power amplification circuit, the other end of the 4th described resistance and the equal ground connection of the other end of the 5th described resistance, the 6th described electric capacity other end is connected with the 1st pin of described power amplifier chip, 2nd pin ground connection of described power amplifier chip, one end of the first described inductance is connected with the 3rd pin of described power amplifier chip and its link is the output of described power amplification circuit, 5V voltage is all accessed in the other end of the first described inductance and one end of the 7th described electric capacity, the other end ground connection of the 7th described electric capacity, one end access 5V voltage of the 8th described electric capacity, the other end ground connection of the 8th described electric capacity, one end access 5V voltage of the 9th described electric capacity, the other end ground connection of the 9th described electric capacity.
7. a kind of Low phase noise phase-locked loop circuit according to claim 1, it is characterized in that described frequency mixer comprises the mixing chip that the tenth electric capacity and model are HMC213, the tenth described electric capacity one end is the radio-frequency head of described frequency mixer, the other end of the tenth described electric capacity is connected with the 7th pin of described mixing chip, 1st pin of described mixing chip, the 3rd pin, the 6th pin and the equal ground connection of the 8th pin, 2nd pin of described mixing chip is the local oscillator end of described frequency mixer, and the 5th pin of described mixing chip is the intermediate frequency end of described frequency mixer.
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| CN107453753A (en) * | 2017-08-31 | 2017-12-08 | 安徽四创电子股份有限公司 | A kind of C-band VCO frequency stabilization circuits |
| CN107689775A (en) * | 2017-09-07 | 2018-02-13 | 成都九洲迪飞科技有限责任公司 | A kind of Low phase noise frequency multiplier and its frequency-doubling method |
| CN109104156A (en) * | 2018-10-12 | 2018-12-28 | 南京屹信航天科技有限公司 | It is a kind of for minimizing the local oscillation circuit of ODU transmission channel |
| CN111446961A (en) * | 2020-04-16 | 2020-07-24 | 上海晶曦微电子科技有限公司 | Frequency synthesizer and driving method of frequency synthesizer |
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| CN107689775A (en) * | 2017-09-07 | 2018-02-13 | 成都九洲迪飞科技有限责任公司 | A kind of Low phase noise frequency multiplier and its frequency-doubling method |
| CN109104156A (en) * | 2018-10-12 | 2018-12-28 | 南京屹信航天科技有限公司 | It is a kind of for minimizing the local oscillation circuit of ODU transmission channel |
| CN111446961A (en) * | 2020-04-16 | 2020-07-24 | 上海晶曦微电子科技有限公司 | Frequency synthesizer and driving method of frequency synthesizer |
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