CN104992953B - Integrated optoelectronic device based on GaAs and preparation method thereof - Google Patents

Integrated optoelectronic device based on GaAs and preparation method thereof Download PDF

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CN104992953B
CN104992953B CN201510410048.4A CN201510410048A CN104992953B CN 104992953 B CN104992953 B CN 104992953B CN 201510410048 A CN201510410048 A CN 201510410048A CN 104992953 B CN104992953 B CN 104992953B
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inp
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CN104992953A (en
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陈�峰
陈一峰
陈勇波
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Chengdu Hiwafer Technology Co Ltd
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Abstract

The invention provides a kind of integrated optoelectronic device based on GaAs and preparation method thereof.Integrated optoelectronic device includes GaAs substrates, N GaAs collector layers, the first isolated area and the second isolated area of formation on gaas substrates, N GaAs collector layers are divided into first area, second area and the 3rd region by the first isolated area and the second isolated area, and the first P GaAs base layers, the first N InGaP emitter layers, the first N are sequentially formed with from the bottom to top on the N GaAs collector layers of first area+InGaAs cap layers, device isolation layer, crystalline transition layer, N layer of InP, i light absorbing layers and P layer of InP；The 2nd P GaAs base layers, the 2nd N InGaP emitter layers and the 2nd N are sequentially formed with from the bottom to top on the N GaAs collector layers of second area+InGaAs cap layers；Formed with the 3rd P GaAs base layers and the 3rd N-type electrode on the N GaAs collector layers in the 3rd region.The present invention can realize that PIN photoelectric detector, trans-impedance amplifier and limiter are highly integrated.

Description

Integrated optoelectronic device based on GaAs and preparation method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of integrated optoelectronic device based on GaAs and its Preparation method.
Background technology
Since 21st century is entered, information industry welcomes super-speed development, and global metadata business is presented explosion type and increased Long, the demand of network bandwidth is skyrocketed through, and this is that developing rapidly for conventional telecommunications business provides new challenge and opportunity, because This, greatly developing optical fiber telecommunications system turns into the emphasis of current development, and the development of optical fiber telecommunications system focuses on developing Photoreceiver.
At present, the receiving terminal framework of the photoreceiver of main flow is：PIN photoelectric detector+trans-impedance amplifier (TIA, trans- Impedance amplifier)+limiter, each layer architecture uses independent chip, three kinds of independent chips form one it is complete Whole receiving terminal, but problems be present in this framework：1. needing to debug during system assembles, it is unfavorable for large-scale production and people Uncertain factor can be introduced for the intervention of factor, is unfavorable for being lifted the quality of receiving terminal；2. three kinds of chips are separate, Wu Faji Into unfavorable Miniaturization Design；3. chip usage quantity is more, it is unfavorable for reducing cost.
The content of the invention
The present invention solves the technical problem of providing a kind of integrated optoelectronic device based on GaAs and preparation method thereof, It can realize that PIN photoelectric detector, trans-impedance amplifier and limiter are highly integrated.
In order to solve the above technical problems, one aspect of the present invention is：A kind of photoelectricity based on GaAs is provided Integrated device, including：GaAs substrates；N-GaAs collector layers, the N-GaAs collector layers are formed on the GaAs substrates； First isolated area and the second isolated area, first isolated area and second isolated area are from the upper of the N-GaAs collector layers Surface insertion is extended to inside the N-GaAs collector layers, and the N-GaAs collector layers are divided into first area, second Region and the 3rd region, the second area is between first isolated area and second isolated area；Wherein, described The first P-GaAs base layers, the first N-InGaP transmittings are sequentially formed with the N-GaAs collector layers of first area from the bottom to top Region layer, the first N+- InGaAs cap layers, device isolation layer, crystalline transition layer, N-InP layers, i- light absorbing layers and P-InP layers, it is described Formed with the first P-type electrode on P-InP layers, formed with the first N-type electrode on the N-InP layers；In the N- of the second area The 2nd P-GaAs base layers, the 2nd N-InGaP emitter layers and the 2nd N are sequentially formed with GaAs collector layers from the bottom to top+- InGaAs cap layers, the 2nd N+The N-GaAs collecting zones of in-InGaAs cap layers and the 2nd P-GaAs base layers side Formed with the second N-type electrode on layer, formed with the second P-type electrode on the 2nd P-GaAs base layers；In the 3rd region N-GaAs collector layers on formed with the 3rd P-GaAs base layers and the 3rd N-type electrode, on the 3rd P-GaAs base layers Formed with the 3rd P-type electrode.
Preferably, between first N-type electrode and the N-InP layers, first P-type electrode and the P-InP layers Between, second N-type electrode and the 2nd N+Between-InGaAs cap layers and N-GaAs collector layers, second P-type electrode with Between the 2nd P-GaAs base layers, between the 3rd N-type electrode and the N-GaAs collector layers and the 3rd P Ohmic contact is respectively formed between type electrode and the 3rd P-GaAs base layers.
Preferably, the thickness of the N-GaAs collector layers be 0.5~3 micron, doping concentration be less than or equal to 5 × 1017cm-3。
Preferably, the first P-GaAs base layers, the 2nd P-GaAs base layers and the 3rd P-GaAs bases The thickness of layer is 20~500 nanometers, and doping concentration is more than or equal to 5 × 1017cm-3。
Preferably, the thickness of the first N-InGaP emitter layers and the 2nd N-InGaP emitter layers be 10~ 500 nanometers, doping concentration is more than or equal to 1 × 1017cm-3, and the first N-InGaP emitter layers and the 2nd N- InGaP chemical formula is In in InGaP emitter layersXGa1-XP, wherein, X is 0.49~0.51.
Preferably, the first N+- InGaAs cap layers and the 2nd N+The thickness of-InGaAs cap layers is received for 10~200 Rice, doping concentration are more than or equal to 1 × 1018cm-3, and the first N+- InGaAs cap layers and the 2nd N+- InGaAs cap layers Middle InGaAs chemical formula is InYGa1-YAs, wherein, Y is 0~1.
Preferably, 10~200 nanometers of the thickness of the device isolation layer, and the material that uses of the device isolation layer for AlN and/or SiN；The thickness of the crystalline transition layer is 0~100 nanometer, and the material that uses of the crystalline transition layer for One or more in InGaAsP, InGaAs, GaAs and InP.
Preferably, the thickness of the N-InP layers is 50~500 nanometers, and doping concentration is more than or equal to 1 × 1018cm-3；Institute The thickness for stating P-InP layers is 20~500 nanometers, and doping concentration is more than or equal to 1 × 1018cm-3。
Preferably, the thickness of the i- light absorbing layers is 50~500 nanometers, and doping concentration is less than or equal to 5 × 1017cm-3, and the material that the i- light absorbing layers use is InGaAs, InGaAs chemical formula is InZGa1-ZAs, wherein, Z be 0.52 or 0.53。
In order to solve the above technical problems, another technical solution used in the present invention is：One kind is provided according to any of the above-described The preparation method of the integrated optoelectronic device based on GaAs of kind, comprises the following steps：From bottom to top shape successively on gaas substrates Into N-GaAs collector layers, P-GaAs base layers, N-InGaP emitter layers, N+- InGaAs cap layers, device isolation layer, crystal mistake Cross layer, N-InP layers, i- light absorbing layers and P-InP layers；The first isolated area and the second isolated area, institute are formed on the P-InP layers Stating the first isolated area and second isolated area, from the upper surface of the P-InP layers, insertion extends to the N-GaAs collecting zones Layer is internal, wherein, first isolated area and second isolated area by the N-GaAs collector layers be divided into first area, Second area and the 3rd region, the second area is between first isolated area and second isolated area；Remove institute The P-InP layers of second area and the 3rd region and the part P-InP layers of the first area are stated, with firstth area Expose i- light absorbing layers in the P-InP layers both sides in domain；Remove the second area and the 3rd region i- light absorbing layers and The part i- light absorbing layers of the first area, expose N-InP layers with the i- light absorbing layers both sides in the first area；Remove The second area and N-InP layers, crystalline transition layer and the device isolation layer in the 3rd region；Remove the second area Part P-GaAs base layers, part N-InGaP emitter layers and N+- InGaAs cap layers, with exposed portion N-GaAs collector layers And expose P-GaAs base layers in the N-InGaP emitter layers both sides of the second area, and remove the 3rd region N-InGaP emitter layers, N+- InGaAs cap layers and part P-GaAs base layers, with exposed portion N-GaAs collector layers；Institute State on the P-InP layers of first area formed with the first P-type electrode and the N-InP layers formed with the first N-type electrode, in institute State the 2nd N of second area+Formed with the second N-type electrode and the 2nd P- in-InGaAs cap layers and N-GaAs collector layers Formed with the second P-type electrode on GaAs base layers, the 3rd N-type electrode is formed on the N-GaAs collector layers in the 3rd region And the 3rd form the 3rd P-type electrode on P-GaAs base layers.
The situation of prior art is different from, the beneficial effects of the invention are as follows：By integrating InP-base PIN on the same substrate Photodetector, InGaP HBT (the different knot bipolar transistor of InGaP) trans-impedance amplifiers and GaAs base PN limiters, and pass through First isolated area and the isolation of the second isolated area so that InP-base PIN photoelectric detector converts optical signals to current signal and delivered to HBT, meanwhile, PN junction forms PN limiters in HBT, so as to realize that PIN photoelectric detector, trans-impedance amplifier and limiter are high Degree is integrated, can increase chip functions, improves integrated level, simplied system structure, reduces size and cost.
Brief description of the drawings
Fig. 1 is the structural representation of integrated optoelectronic device of the embodiment of the present invention based on GaAs.
Fig. 2~Fig. 7 is the preparation flow figure of integrated optoelectronic device of the embodiment of the present invention based on GaAs.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only the part of the embodiment of the present invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made Embodiment, belong to the scope of protection of the invention.
Fig. 1 is referred to, is the structural representation of integrated optoelectronic device of the embodiment of the present invention based on GaAs.The present invention is implemented The integrated optoelectronic device based on GaAs of example includes GaAs substrates 1, N-GaAs collector layers 2, the first isolated area 3 and the second isolation Area 4.
N-GaAs collector layers 2 are formed on GaAs substrates 1.First isolated area 3 and the second isolated area 4 are from N-GaAs current collections Region layer 2 upper surface insertion extend to inside N-GaAs collector layers 2, by N-GaAs collector layers 2 be divided into first area A, Second area B and the 3rd region C, second area B are between the first isolated area 3 and the second isolated area 4.The He of first isolated area 3 The effect of second isolated area 4 is to make first area A, second area B and the 3rd region C mutually insulateds.First isolated area 3 and second Isolated area 4 can use injection ionic means or be formed using etching technics.
Wherein, the first P-GaAs base layers are sequentially formed with from the bottom to top on first area A N-GaAs collector layers 2 11st, the first N-InGaP emitter layers 12, the first N+- InGaAs cap layers 13, device isolation layer 14, crystalline transition layer 15, N-InP Layer 16, i- light absorbing layers 17 and P-InP layers 18.On P-InP layers 18 formed with the first P-type electrode P1, N-InP layer 16 formed with First N-type electrode N1；The 2nd P-GaAs bases are sequentially formed with from the bottom to top on second area B N-GaAs collector layers 2 The 21, the 2nd N-InGaP emitter layers 22 of layer and the 2nd N+- InGaAs cap layers 23, the 2nd N+In-InGaAs cap layers 23 and second Formed with the second N-type electrode N2 on the N-GaAs collector layers 2 of the side of P-GaAs base layers 21, on the 2nd P-GaAs base layers 21 Formed with the second P-type electrode P2；Formed with the He of the 3rd P-GaAs base layers 31 on the 3rd region C N-GaAs collector layers 2 3rd N-type electrode N3, formed with the 3rd P-type electrode P3 on the 3rd P-GaAs base layers 31.In the present embodiment, the first p-type electricity Pole P1, the first N-type electrode N1 and the second P-type electrode P2 quantity are two.Two the first P-type electrode P1 are located at P- respectively The left and right sides on layer of InP 18, two the first N-type electrode N1 are located on the N-InP layers 16 of the both sides of i- light absorbing layers 17 respectively, and two Individual second P-type electrode P2 is respectively on the 2nd P-GaAs base layers 21 of the both sides of the 2nd N-InGaP emitter layers 22.
In the present embodiment, between the first N-type electrode N1 and N-InP layer 16, the first P-type electrode P1 and P-InP layer 18 it Between, the second N-type electrode N2 and the 2nd N+Between-InGaAs cap layers 23 and N-GaAs collector layers 2, the second P-type electrode P2 and Between two P-GaAs base layers 21, between the 3rd N-type electrode N3 and N-GaAs collector layer 2 and the 3rd P-type electrode P3 and Ohmic contact is respectively formed between three P-GaAs base layers 31.
The material of GaAs substrates 1 is the one or more in Si, SiC, GaN, Diamond and sapphire, and main function is Base support.
The thickness of N-GaAs collector layers 2 is 0.5~3 micron, and doping concentration is less than or equal to 5 × 1017cm-3, it is main to make By the use of be as HBT devices colelctor electrode and PN diode clippers N knot.
The thickness of first P-GaAs base layers 11, the 2nd P-GaAs base layers 21 and the 3rd P-GaAs base layers 31 be 20~ 500 nanometers, doping concentration is more than or equal to 5 × 1017cm-3, the main function of the 2nd P-GaAs base layers 21 is as HBT devices Base stage and PN diode clippers P knot.
The thickness of first N-InGaP emitter layers 12 and the 2nd N-InGaP emitter layers 22 is 10~500 nanometers, doping Concentration is more than or equal to 1 × 1017cm-3, and in the first N-InGaP emitter layers 12 and the 2nd N-InGaP emitter layers 22 InGaP chemical formula is InXGa1-XP, wherein, X is 0.49~0.51, the first N-InGaP emitter layers 12 and the 2nd N-InGaP The main function of the N-InGaP emitter layers 22 of emitter layer 22 the 2nd is the base stage as HBT devices, it is contemplated that Lattice Matching, X Selection 0.49~0.51 typically is only capable of, and due to being heterojunction structure during HBT, therefore the 2nd N-InGaP emitter layers 22 Doping concentration need not be higher than the 2nd P-GaAs base layers 21.
First N+The N of-InGaAs cap layers 13 and the 2nd+The thickness of-InGaAs cap layers 23 is 10~200 nanometers, and doping concentration is big In or equal to 1 × 1018cm-3, and the first N+The N of-InGaAs cap layers 13 and the 2nd+InGaAs chemical formula in-InGaAs cap layers 23 For InYGa1-YAs, wherein, Y is 0~1.2nd N+The main function of-InGaAs cap layers 23 is to be beneficial to make Europe on HBT devices Nurse contacts electrode.
10~200 nanometers of the thickness of device isolation layer 14, and the material that device isolation layer 14 uses is AlN and/or SiN. The main function of device isolation layer 14 is to separate PIN photoelectric detector, trans-impedance amplifier and limiter.
The thickness of crystalline transition layer 15 is 0~100 nanometer, and the material that uses of crystalline transition layer 15 for InGaAsP, One or more in InGaAs, GaAs and InP.The main function of crystalline transition layer 15 is to be beneficial to InP to grow.
The thickness of N-InP layers 16 is 50~500 nanometers, and doping concentration is more than or equal to 1 × 1018cm-3.N-InP layers 16 Main function is the N areas as PIN photoelectric detector.
The thickness of i- light absorbing layers 17 is 50~500 nanometers, and doping concentration is less than or equal to 5 × 1017cm-3, and i- light is inhaled For the material that receipts layer 17 uses for InGaAs, InGaAs chemical formula is InZGa1-ZAs, wherein, Z is 0.52 or 0.53.I- light is inhaled The main function for receiving floor 17 is i areas as PIN photoelectric detector, observable spectral response be about 1.1~1.8 microns or 0.7~0.9 micron.
The thickness of P-InP layers 18 is 20~500 nanometers, and doping concentration is more than or equal to 1 × 1018cm-3.P-InP layers 18 Main function is the P areas as PIN photoelectric detector.
The embodiment of the present invention also provides a kind of preparation method of the integrated optoelectronic device based on GaAs, refers to Fig. 2 to figure 7, the preparation method comprises the following steps：
Step 1：N-GaAs collector layers 2, P-GaAs base layers 10, N- are from bottom to top sequentially formed on GaAs substrates 1 InGaP emitter layers 20, N+- InGaAs cap layers 30, device isolation layer 40, crystalline transition layer 50, N-InP layers 60, i- light absorbs 70 and P-InP of layer layers 80.
Wherein, as shown in Fig. 2 GaAs substrates 1, N-GaAs collector layers 2, P-GaAs base layers 10, N-InGaP launch sites Layer 20, N+- InGaAs cap layers 30, device isolation layer 40, crystalline transition layer 50, N-InP layers 60, i- light absorbing layers 70 and P-InP Layer 80 is the structure stacked gradually.
The material of GaAs substrates 1 is the one or more in Si, SiC, GaN, Diamond and sapphire, and main function is Base support.
The thickness of N-GaAs collector layers 2 is 0.5~3 micron, and doping concentration is less than or equal to 5 × 1017cm-3, it is main to make By the use of be as HBT devices colelctor electrode and PN diode clippers N knot.
Step 2：Form the first isolated area 3 and the second isolated area 4 on P-InP layers 80, the first isolated area 3 and second every From area 4, from the upper surface of P-InP floor 80, insertion is extended to inside N-GaAs collector layers 2, wherein, the first isolated area 3 and the N-GaAs collector layers 2 are divided into first area A, second area B and the 3rd region C by two isolated areas 4, and second area B is located at Between first isolated area 3 and the second isolated area 4.
Wherein, the effect of the first isolated area 3 and the second isolated area 4 is to make first area A, second area B and the 3rd region C Mutually insulated.As shown in figure 3, after the first isolated area 3 and the second isolated area 4 separate, P-GaAs base layers 10 divide for three Point, first area A P-GaAs base layers are the first P-GaAs base layers 11, and second area B P-GaAs base layers are 2nd P-GaAs base layers 21, second area B P-GaAs base layers are the 3rd P-GaAs base layers 31.N-InGaP launches Region layer 20 is also classified into three parts, and first area A N-InGaP emitter layers are the first N-InGaP emitter layers 12, the secondth area Domain B N-InGaP emitter layers are the 2nd N-InGaP emitter layers 22.N+- InGaAs cap layers 30 are also classified into three parts, the One region A N+- InGaAs cap layers are the first N+- InGaAs cap layers 13, second area B N+- InGaAs cap layers are second N+- InGaAs cap layers 23.Correspondingly, first area A device isolation layer is device isolation layer 14, first area A crystal Transition zone is crystalline transition layer 15, and first area A N-InP layers are N-InP layers 16, first area A i- light absorbing layers As i- light absorbing layers 17, first area A P-InP layers are P-InP layers 18.In the present embodiment, the first isolated area 3 and Two isolated areas 4 can use injection ionic means or be formed using etching technics.
The thickness of first P-GaAs base layers 11, the 2nd P-GaAs base layers 21 and the 3rd P-GaAs base layers 31 be 20~ 500 nanometers, doping concentration is more than or equal to 5 × 1017cm-3, the main function of the 2nd P-GaAs base layers 21 is as HBT devices Base stage and PN diode clippers P knot.
The thickness of first N-InGaP emitter layers 12 and the 2nd N-InGaP emitter layers 22 is 10~500 nanometers, doping Concentration is more than or equal to 1 × 1017cm-3, and in the first N-InGaP emitter layers 12 and the 2nd N-InGaP emitter layers 22 InGaP chemical formula is InXGa1-XP, wherein, X is 0.49~0.51, the first N-InGaP emitter layers 12 and the 2nd N-InGaP The main function of the N-InGaP emitter layers 22 of emitter layer 22 the 2nd is the base stage as HBT devices, it is contemplated that Lattice Matching, X Selection 0.49~0.51 typically is only capable of, and due to being heterojunction structure during HBT, therefore the 2nd N-InGaP emitter layers 22 Doping concentration need not be higher than the 2nd P-GaAs base layers 21.
First N+The N of-InGaAs cap layers 13 and the 2nd+The thickness of-InGaAs cap layers 23 is 10~200 nanometers, and doping concentration is big In or equal to 1 × 1018cm-3, and the first N+The N of-InGaAs cap layers 13 and the 2nd+InGaAs chemical formula in-InGaAs cap layers 23 For InYGa1-YAs, wherein, Y is 0~1.2nd N+The main function of-InGaAs cap layers 23 is to be beneficial to make Europe on HBT devices Nurse contacts electrode.
10~200 nanometers of the thickness of device isolation layer 14, and the material that device isolation layer 14 uses is AlN and/or SiN. The main function of device isolation layer 14 is to separate PIN photoelectric detector, trans-impedance amplifier and limiter.
The thickness of crystalline transition layer 15 is 0~100 nanometer, and the material that uses of crystalline transition layer 15 for InGaAsP, One or more in InGaAs, GaAs and InP.The main function of crystalline transition layer 15 is to be beneficial to InP to grow.
The thickness of N-InP layers 16 is 50~500 nanometers, and doping concentration is more than or equal to 1 × 1018cm-3.N-InP layers 16 Main function is the N areas as PIN photoelectric detector.
The thickness of i- light absorbing layers 17 is 50~500 nanometers, and doping concentration is less than or equal to 5 × 1017cm-3, and i- light is inhaled For the material that receipts layer 17 uses for InGaAs, InGaAs chemical formula is InZGa1-ZAs, wherein, Z is 0.52 or 0.53.I- light is inhaled The main function for receiving floor 17 is i areas as PIN photoelectric detector, observable spectral response be about 1.1~1.8 microns or 0.7~0.9 micron.
The thickness of P-InP layers 18 is 20~500 nanometers, and doping concentration is more than or equal to 1 × 1018cm-3.P-InP layers 18 Main function is the P areas as PIN photoelectric detector.
Step 3：Second area B and the 3rd region C P-InP layers and first area A part P-InP layers are removed, with In first area, i- light absorbing layers are exposed in A P-InP layers both sides.
Wherein, referring to Fig. 4, after step 3, second area B and the 3rd region C P-InP layers are removed, and the One region A P-InP layers remain a part, as P-InP layers 18.In the present embodiment, photoetching, etching, gold can be used Category deposition or stripping technology form the p-type table top of PIN photoelectric detector on P-InP layers 80, so as to obtain P-InP layers 18.
Step 4：The part i- light of the i- light absorbing layers and first area A that remove second area B and the 3rd region C is inhaled Layer is received, exposes N-InP layers with the i- light absorbing layers both sides in first area A.
Wherein, referring to Fig. 5, after step 4, second area B and the 3rd region C i- light absorbing layers are removed, and First area A i- light absorbing layers remain a part, as i- light absorbing layers 17.In the present embodiment, can use photoetching, Metal deposit or stripping technology form the N-type table top of PIN photoelectric detector on N-InP layers, so as to obtain i- light absorbing layers 17.
Step 5：Remove second area and N-InP layers, crystalline transition layer and the device isolation layer in the 3rd region.
Wherein, referring to Fig. 6, after step 5, second area B and the 3rd region C N-InP layers, crystalline transition layer It is removed with device isolation layer.In the present embodiment, photoetching or etching technics can be used to form HBT devices and the pole of PN junction two The table top of pipe.
Step 6：Remove second area B part P-GaAs base layers, part N-InGaP emitter layers and N+-InGaAs Cap layers, expose P-GaAs bases with exposed portion N-GaAs collector layers and in second area B N-InGaP emitter layers both sides Region layer, and remove the 3rd region C N-InGaP emitter layers, N+- InGaAs cap layers and part P-GaAs base layers, to expose Part N-GaAs collector layers.
Wherein, referring to Fig. 7, after step 6, PIN photoelectric detector, trans-impedance amplifier and PN limiters are formd Basic structure.In the present embodiment, photoetching or etching process can be used to corrode the 2nd P-GaAs base layers 21, the 2nd N- The N of InGaP emitter layers 22 and the 2nd+- InGaAs cap layers 23 form electrode table top, and the corrosion shape of the 3rd P-GaAs base layers 31 Into electrode table top.
Step 7：On first area A P-InP layers formed with the first P-type electrode P1 and N-InP layer formed with One N-type electrode N1, in second area B the 2nd N+Formed with the second N-type electrode in-InGaAs cap layers and N-GaAs collector layers Formed with the second P-type electrode P2 on N2 and the 2nd P-GaAs base layers, formed on the 3rd region C N-GaAs collector layers The 3rd P-type electrode P3 is formed on 3rd N-type electrode N3 and the 3rd P-GaAs base layers.
Wherein, referring to Fig. 1, after step 7, that is, the integrated optoelectronic device based on GaAs of previous embodiment is obtained. In the present embodiment, the first P-type electrode P1, the first N-type electrode N1 and the second P-type electrode P2 quantity are two.Two The left and right sides on P-InP layers 18, two the first N-type electrode N1 are located at i- light absorbing layers to one P-type electrode P1 respectively respectively On the N-InP layers 16 of 17 both sides, two the second P-type electrode P2 are located at the second of the both sides of the 2nd N-InGaP emitter layers 22 respectively On P-GaAs base layers 21.
By the above-mentioned means, the present invention has increase chip functions, integrated level is improved, simplied system structure, reduces size And the advantages that cost, fully adapt to main flow fiber optic communication demand.
Embodiments of the invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize this hair The equivalent structure or equivalent flow conversion that bright specification and accompanying drawing content are made, or directly or indirectly it is used in other related skills Art field, is included within the scope of the present invention.

Claims (10)

  1. A kind of 1. integrated optoelectronic device based on GaAs, it is characterised in that including：
    GaAs substrates；
    N-GaAs collector layers, the N-GaAs collector layers are formed on the GaAs substrates；
    First isolated area and the second isolated area, first isolated area and second isolated area are from the N-GaAs collector layers Upper surface insertion extend to inside the N-GaAs collector layers, by the N-GaAs collector layers be divided into first area, Second area and the 3rd region, the second area is between first isolated area and second isolated area；
    Wherein, be sequentially formed with from the bottom to top on the N-GaAs collector layers of the first area the first P-GaAs base layers, First N-InGaP emitter layers, the first N+- InGaAs cap layers, device isolation layer, crystalline transition layer, N-InP layers, i- light absorbs Layer and P-InP layers, formed with the first P-type electrode on the P-InP layers, formed with the first N-type electrode on the N-InP layers； The 2nd P-GaAs base layers, the 2nd N-InGaP are sequentially formed with from the bottom to top on the N-GaAs collector layers of the second area Emitter layer and the 2nd N+- InGaAs cap layers, the 2nd N+In-InGaAs cap layers and the 2nd P-GaAs base layers one Formed with the second N-type electrode on the N-GaAs collector layers of side, formed with the second p-type electricity on the 2nd P-GaAs base layers Pole；Formed with the 3rd P-GaAs base layers and the 3rd N-type electrode on the N-GaAs collector layers in the 3rd region, described Formed with the 3rd P-type electrode on three P-GaAs base layers；
    The quantity of first P-type electrode, the first N-type electrode and the second P-type electrode is two；Two the first P-type electrodes distinguish position The left and right sides on P-InP layers, two the first N-type electrodes are respectively on the N-InP layers of i- light absorbing layers both sides, two the Two P-type electrodes are respectively on the 2nd P-GaAs base layers of the 2nd N-InGaP emitter layers both sides.
  2. 2. the integrated optoelectronic device according to claim 1 based on GaAs, it is characterised in that first N-type electrode with Between the N-InP layers, between first P-type electrode and the P-InP layers, second N-type electrode and the 2nd N+- Between InGaAs cap layers and N-GaAs collector layers, between second P-type electrode and the 2nd P-GaAs base layers, it is described Between 3rd N-type electrode and the N-GaAs collector layers and the 3rd P-type electrode and the 3rd P-GaAs base layers Between be respectively formed Ohmic contact.
  3. 3. the integrated optoelectronic device according to claim 1 based on GaAs, it is characterised in that the N-GaAs collector layers Thickness be 0.5~3 micron, doping concentration be less than or equal to 5 × 1017cm-3。
  4. 4. the integrated optoelectronic device according to claim 1 based on GaAs, it is characterised in that the first P-GaAs bases The thickness of layer, the 2nd P-GaAs base layers and the 3rd P-GaAs base layers is 20~500 nanometers, and doping concentration is more than Or equal to 5 × 1017cm-3。
  5. 5. the integrated optoelectronic device according to claim 1 based on GaAs, it is characterised in that the first N-InGaP hairs The thickness for penetrating region layer and the 2nd N-InGaP emitter layers is 10~500 nanometers, doping concentration is more than or equal to 1 × 1017cm-3, and InGaP chemical formula is in the first N-InGaP emitter layers and the 2nd N-InGaP emitter layers InXGa1-XP, wherein, X is 0.49~0.51.
  6. 6. the integrated optoelectronic device according to claim 1 based on GaAs, it is characterised in that the first N+- InGaAs caps Layer and the thickness of the 2nd N+-InGaAs cap layers are 10~200 nanometers, and doping concentration is more than or equal to 1 × 1018cm-3, and First N+- InGaAs cap layers and the 2nd N+InGaAs chemical formula is In in-InGaAs cap layersYGa1-YAs, wherein, Y For 0~1.
  7. 7. the integrated optoelectronic device according to claim 1 based on GaAs, it is characterised in that the thickness of the device isolation layer 10~200 nanometers of degree, and the material that the device isolation layer uses is AlN and/or SiN；The thickness of the crystalline transition layer is 0 ~100 nanometers, and the material that the crystalline transition layer uses is the one or more in InGaAsP, InGaAs, GaAs and InP.
  8. 8. the integrated optoelectronic device according to claim 1 based on GaAs, it is characterised in that the thickness of the N-InP layers For 50~500 nanometers, doping concentration is more than or equal to 1 × 1018cm-3；The thickness of the P-InP layers is 20~500 nanometers, is mixed Miscellaneous concentration is more than or equal to 1 × 1018cm-3。
  9. 9. the integrated optoelectronic device according to claim 1 based on GaAs, it is characterised in that the thickness of the i- light absorbing layers Spend for 50~500 nanometers, doping concentration is less than or equal to 5 × 1017cm-3, and the material that uses of the i- light absorbing layers for InGaAs, InGaAs chemical formula are InZGa1-ZAs, wherein, Z is 0.52 or 0.53.
  10. 10. a kind of preparation method of integrated optoelectronic device based on GaAs according to claim any one of 1-9, its feature It is, comprises the following steps：
    N-GaAs collector layers, P-GaAs base layers, N-InGaP emitter layers, N are from bottom to top sequentially formed on gaas substrates +-InGaAs cap layers, device isolation layer, crystalline transition layer, N-InP layers, i- light absorbing layers and P-InP layers；
    The first isolated area and the second isolated area, first isolated area and second isolated area are formed on the P-InP layers From the upper surfaces of the P-InP layers, insertion is extended to inside the N-GaAs collector layers, wherein, first isolated area and The N-GaAs collector layers are divided into first area, second area and the 3rd region by second isolated area, and described second Region is between first isolated area and second isolated area；
    Remove the P-InP layers of the second area and the 3rd region and the part P-InP layers of the first area, with Expose i- light absorbing layers in the P-InP layers both sides of the first area；
    Remove the i- light absorbing layers of the second area and the 3rd region and the part i- light absorbs of the first area Layer, exposes N-InP layers with the i- light absorbing layers both sides in the first area；
    Remove the second area and N-InP layers, crystalline transition layer and the device isolation layer in the 3rd region；
    Remove the part P-GaAs base layers, part N-InGaP emitter layers and N of the second area+- InGaAs cap layers, with dew Go out part N-GaAs collector layers and expose P-GaAs base layers in the N-InGaP emitter layers both sides of the second area, And N-InGaP emitter layers, N+-InGaAs cap layers and the part P-GaAs base layers in the 3rd region are removed, with exposed division Divide N-GaAs collector layers；
    On the P-InP layers of the first area formed with the first P-type electrode and the N-InP layers formed with the first N-type Electrode, in the 2nd N of the second area+In-InGaAs cap layers and N-GaAs collector layers formed with the second N-type electrode and Formed with the second P-type electrode on 2nd P-GaAs base layers, the 3rd N is formed on the N-GaAs collector layers in the 3rd region The 3rd P-type electrode is formed on type electrode and the 3rd P-GaAs base layers.
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