CN104981092A - Surface coating and semiconductor packaging part including same - Google Patents
Surface coating and semiconductor packaging part including same Download PDFInfo
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- CN104981092A CN104981092A CN201510337419.0A CN201510337419A CN104981092A CN 104981092 A CN104981092 A CN 104981092A CN 201510337419 A CN201510337419 A CN 201510337419A CN 104981092 A CN104981092 A CN 104981092A
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- plating layer
- metal
- overlay coating
- wiring pattern
- layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/035—Paste overlayer, i.e. conductive paste or solder paste over conductive layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
The embodiment of the present inventive provides a surface coating and a semiconductor packaging part including the same. The surface coating comprises a first metal plating layer that covers a protected material, a second metal plating layer that is formed on the first metal plating layer, and an organic solderability preservative layer that is formed on the second metal plating layer, wherein the second metal plating layer comprises copper. The surface coating has the advantages of low cost and high thermal cycling reliability.
Description
Technical field
The exemplary embodiment of inventive concept relates to field of semiconductor package, specifically, relate to a kind of overlay coating, a kind of comprise this overlay coating semiconductor package part and a kind of manufacture comprise the method for the semiconductor package part of this overlay coating.
Background technology
Usually, the joining technique of integrated circuit (IC) chip and printed circuit board (PCB) (PCB) can be divided into Through-Hole Technology (THT) and surface mounting technology (SMT).Along with electronic installation is to miniaturized and lightening development, electronic device becomes highly integrated, and the SMT that can save PCB space develops into main encapsulation technology gradually.
Fig. 1 illustrates the encapsulating structure utilizing SMT that ball grid array (BGA) packaging part is joined to PCB and formed according to prior art.With reference to Fig. 1, encapsulating structure comprises BGA package part 1 and PCB 2.BGA package part 1 comprises: substrate 10; Nude film puts dish 20, arranges on the substrate 10; Nude film 30, invests nude film by adhesive 31 and puts dish 20; Lead-in wire 40, is electrically connected to substrate 10 by nude film 30; And sealant 50, cover above nude film 30 to seal whole BGA package part.BGA package part 1 is attached to PCB 2 by the multiple solder joints 3 be arranged on substrate 10 lower surface.
On the surface be connected with solder of PCB 2, be coated with some overlay coatings.These overlay coatings can prevent the wiring pattern of printed circuit board (PCB) to be oxidized, to improve fastness and the reliability of solder bond between solder and printed circuit board (PCB).
Fig. 2 illustrates the overlay coating for printed circuit board (PCB) according to prior art.As shown in Figure 2, the plated surface of copper (Cu) wiring pattern of PCB3 is covered with nickel (Ni) and gold (Au), and wherein, Ni layer 31 and Au layer 32 sequentially cover above Cu wiring 30.In this case, the soldering reliability of Ni/Au overlay coating under thermal cycle (Thermal cycle) environment is better, but causes cost higher owing to employing expensive Au.
Fig. 3 illustrates the overlay coating for another printed circuit board (PCB) according to prior art.As shown in Figure 3, the surface-coated organic solderability preservative (OSP) of the Cu wiring pattern of PCB 4, OSP layer 41 directly overlays above Cu wiring 40.In this case, although it is lower than using the cost of Ni/Au overlay coating to use the cost of OSP overlay coating, cycle reliability is poor.
Disclosed in this background technology part, above information is only for strengthening the understanding of the background to the present invention's design, and therefore, above information may comprise the information not forming the prior art known in this country to those skilled in the art.
Summary of the invention
The exemplary embodiment of inventive concept provide a kind of can realize the cycle reliability of low cost and improvement simultaneously the overlay coating comprising copper and organic solderability preservative, a kind of comprise this overlay coating semiconductor package part and a kind of manufacture comprise the method for the semiconductor package part of this overlay coating.
The one side of inventive concept, provides a kind of overlay coating.Described overlay coating comprises: the first metal. plating layer, covers on protected material; Second metal. plating layer, is formed on described first metal. plating layer; And organic solderability preservative layer, be formed on described second metal. plating layer, wherein, described second metal. plating layer comprises copper.
According to exemplary embodiment, the copper in described second metal. plating layer can fuse in solder completely when welding.
According to exemplary embodiment, described protected material can for being arranged on printed circuit board (PCB) and the wiring pattern will be connected with solder.
According to exemplary embodiment, the thickness of described second metal. plating layer can in the scope of 0.05 μm to 2 μm.
According to exemplary embodiment, the thickness of described second metal. plating layer can in the scope of 0.15 μm to 0.95 μm.
According to exemplary embodiment, described first metal. plating layer can comprise nickel.
According to exemplary embodiment, be included in nickel in described first metal. plating layer after welding terminates with solder bonds.
According to exemplary embodiment, the thickness of described first metal. plating layer can in the scope of 1 μm to 20 μm.
According to exemplary embodiment, the thickness of described organic solderability preservative layer can in the scope of 0.05 μm to 2 μm.
According to exemplary embodiment, the thickness of described organic solderability preservative layer can in the scope of 0.1 μm to 0.5 μm.
The another aspect of inventive concept, provides a kind of semiconductor package part.Described semiconductor package part comprises substrate, setting wiring pattern on the substrate, is formed in the overlay coating on described wiring pattern and is welded to the semiconductor device on described wiring pattern by described overlay coating, wherein, described overlay coating comprises: the first metal. plating layer, covers on described wiring pattern; Second metal. plating layer, is formed on described first metal. plating layer; And organic solderability preservative layer, be formed on described second metal. plating layer, wherein, described second metal. plating layer comprises copper, and the copper in described second metal. plating layer fuses in solder completely when welding.
The another aspect of inventive concept, provides a kind of method manufacturing semiconductor package part.The method of described manufacture semiconductor package part comprises: prepare substrate, and described substrate comprises wiring pattern; Described wiring pattern forms overlay coating; Semiconductor device is placed on the substrate, thus described semiconductor device is contacted with described wiring pattern by the solder be arranged between described semiconductor device and described wiring pattern; And make described semiconductor device be connected to described substrate by welding, wherein, the step that described wiring pattern is formed overlay coating is included on described wiring pattern and sequentially forms the first metal. plating layer, the second metal. plating layer and organic solderability preservative layer, described second metal. plating layer comprises copper, and the copper in described second metal. plating layer fuses in solder completely when welding.
Accompanying drawing explanation
By describing the exemplary embodiment of inventive concept in detail below in conjunction with accompanying drawing, the feature of the above and other aspect of inventive concept and advantage will become clear.In the accompanying drawings, same Reference numeral will indicate same element all the time.
Fig. 1 illustrates and utilizes SMT to join BGA package part to printed circuit board (PCB) according to prior art and the encapsulating structure formed.
Fig. 2 illustrates the overlay coating for printed circuit board (PCB) according to prior art.
Fig. 3 illustrates the overlay coating for another printed circuit board (PCB) according to prior art.
Fig. 4 illustrates the overlay coating comprising copper and organic solderability preservative of the exemplary embodiment according to the present invention's design.
Embodiment
Hereinafter, the various embodiments of the present invention's design are described more fully with reference to the accompanying drawing of some embodiments shown in it.But the present invention's design can be implemented in many different forms, and should not be construed as limited to embodiment set forth herein.On the contrary, provide these embodiments to make this description to be thoroughly with complete, and the scope that the present invention is conceived is conveyed to those skilled in the art by these embodiments.In the accompanying drawings, for the sake of clarity, the size in layer and region may be exaggerated.
For ease of describing, can here use such as " ... under ", " in ... below ", " below ", " in ... top ", " above " etc. space relative terms the relation of an element as shown in accompanying drawing and other elements is described.Will be appreciated that except the orientation drawn in accompanying drawing, space relative terms is also intended to comprise device different azimuth in use or operation.Such as, if the device in accompanying drawing is reversed, be then described to " " other elements " below " or " under " element will be oriented subsequently " " described other elements " top ".Therefore, term " in ... below " can comprise " in ... top " and " in ... below " two kinds of orientation.By device in addition directed (90-degree rotation or in other orientation), and can correspondingly explain that the space used describes language relatively here.
Fig. 4 illustrates the overlay coating comprising copper and organic solderability preservative of the exemplary embodiment according to the present invention's design.As shown in Figure 4, the overlay coating 100 according to exemplary embodiment comprises: the first metal. plating layer 110, covers on protected material 140; Second metal. plating layer 120, is formed on described first metal. plating layer 110; And organic solderability preservative layer 130, be formed on described second metal. plating layer 120, wherein, described second metal. plating layer 120 comprises copper.
In one exemplary embodiment, the protected material 140 it being coated with overlay coating 100 can be arranged on printed circuit board (PCB) (PCB) and the wiring pattern will be connected with solder.Such as, PCB described here can comprise the substrate formed by insulating material such as epoxy resin film, polyimide film or polyetherimde films.PCB can have various shape according to practical application, such as, PCB can be the substrate of the thin sheet form with rigidity, also can be flexible base, board or transparency carrier.Although the overlay coating 100 shown in Fig. 4 is formed on the upper surface of protected material 140; but the present invention's design is not limited thereto; overlay coating can be formed on the lower surface of protected material, on the upper surface that also can simultaneously be formed in protected material and lower surface.Such as, overlay coating 100 can be formed on the lower surface of PCB, to cover the wiring pattern be formed on the lower surface of PCB.
Particularly, wiring pattern can be formed by the electric conducting material of such as copper (Cu).In the preparation technology of PCB, layers of copper can be formed by deposition or electroplating technology on the whole surface of PCB, re-use mask, by the etch process of such as dry ecthing or wet etching, patterning is carried out to copper lamina, thus form wiring pattern.But inventive concept is not limited thereto, wiring pattern can be any conductive metallic material comprising such as silver (Ag), aluminium (Al) or tin (Sn).Except PCB, overlay coating can also cover will experiencing on the surface of welding procedure of various electronic devices and components or semiconductor package part.
In the present example embodiment, plated surface coating 100 comprises the first metal. plating layer 110 covered on protected material 140.Particularly, the first metal. plating layer 110 can cover on the wiring pattern of PCB.More specifically, the wiring pattern of PCB can be formed by Cu, and the first metal. plating layer 110 can to directly overlay on Cu wiring pattern and to contact with Cu.In addition, the thickness of the first metal. plating layer 110 can in the scope of 1 μm to 20 μm.
As the bottom material of overlay coating 100, the first metal. plating layer 110 can comprise various conductive metal material.Such as, the first metal. plating layer 110 can comprise nickel (Ni).Ni can form intermetallic compound with solder during welding procedure, and after welding terminates with solder bonds, thus produce firmly solder joint.In addition, Ni fuses in solder hardly, can not affect the performance of solder.
When the first metal. plating layer is made up of Ni, because the chemical property of Ni is active, therefore Ni be exposed to air can be oxidized, cause solder to reduce in the wetability of contact surface.In this case, make on the first metal. plating layer if covered by organic solderability preservative (OSP) by Ni, then will there is chemical reaction with Ni in OSP, and the chemical property of OSP is changed.
In order to solve the problem, according to the exemplary embodiment of inventive concept, the first metal. plating layer is formed with the second metal. plating layer and the second metal. plating layer comprises Cu.
Particularly, as shown in Figure 4, the second metal level 120 be made up of Cu can be formed on the first metal. plating layer 110 of being made up of Ni.Cu can fuse in solder when welding.In the process of Reflow Soldering or wave-soldering, if the content fusing into the Cu in solder is greater than the 0.5wt% of solder, then may produce granular solder joint (Gritty Joints), cause welding effect deterioration.Therefore, form the thickness being the second metal. plating layer controlling to comprise Cu according to the committed step of the overlay coating of the present invention's design, to guarantee that Cu can fuse in solder completely during Reflow Soldering or wave-soldering, and the content fusing into the Cu in solder can not cause negative effect to the reliability of solder.
In one exemplary embodiment, the thickness of the second metal. plating layer can in the scope of 0.05 μm to 2 μm.In another exemplary embodiment, the thickness of the second metal. plating layer can in the scope of 0.15 μm to 0.95 μm.But inventive concept is not limited thereto, the thickness of the second metal. plating layer can also be fall into any special value in above-mentioned scope or particular range.
In addition, can by utilize such as plating, chemical plating, physical vapour deposition (PVD) (PVD) or chemical vapour deposition (CVD) (CVD) any known method on protected material, form the first metal. plating layer and the second metal. plating layer.
Organic solderability preservative (OSP) layer is formed on the second metal. plating layer.Particularly, as shown in Figure 4, OSP layer 130 can be formed in and comprise on second metal. plating layer 120 of Cu, and the second metal. plating layer 120 is formed on the first metal. plating layer 110, and the first metal. plating layer 110 covers on protected material 140.More specifically, the first metal. plating layer 110 can be made up of Ni, and protected material 140 can be the wiring pattern formed by Cu be arranged on PCB.
As the superiors' material of plated surface coating 100, OSP layer 130 can be removed by scaling powder when welding.OSP forms on exposed Cu surface the hydrophobicity organic protective film that one deck is about 0.2mm ~ 0.5mm by chemical method.The surface of this layer of organic film protection Cu, makes it avoid oxidation.OSP can melt mutually with multiple scaling powder, and can bear the thermal shock of repeatedly more than 260 DEG C, is conducive to the substrate evenness of solder joint and the angularity in plate face before packaging guaranteeing such as printed circuit board (PCB).
According to exemplary embodiment, OSP layer can be formed by organic materials such as rosin based, reactive resin class (Active Resin) and azoles (Azole).Such as; OSP solution can be immersed with the protected material 140 of the second metal. plating layer 120 comprising Cu by it being formed the first metal. plating layer 110; until submergence after 2 to 3 seconds; protected material 140 is taken out; OSP naturally will cover and comprise on second metal. plating layer 120 of Cu, thus forms OSP layer 130.According to exemplary embodiment, the thickness of OSP layer can in the scope of 0.05 μm to 2 μm.According to another exemplary embodiment, the thickness of OSP layer can in the scope of 0.1 μm to 0.5 μm.
The exemplary embodiment of inventive concept also provides a kind of semiconductor package part.Described semiconductor package part comprises substrate, the wiring pattern be arranged on substrate, the semiconductor device that is formed in the overlay coating on wiring pattern and is welded to by overlay coating on wiring pattern, wherein, overlay coating comprises: the first metal. plating layer, covers on described wiring pattern; Second metal. plating layer, is formed on described first metal. plating layer; And organic solderability preservative layer, be formed on described second metal. plating layer, wherein, described second metal. plating layer comprises copper, and the copper in described second metal. plating layer fuses in solder completely when welding.
In one exemplary embodiment, substrate can be printed circuit board (PCB), and the wiring pattern be arranged on substrate can be formed by copper.The semiconductor device be welded on wiring pattern by overlay coating can be any semiconductor device of such as ball grid array (BGA) packaging part.In the present example embodiment, because the overlay coating be formed on wiring pattern can be identical with the overlay coating of each embodiment in foregoing multiple embodiment, the repeated description to it is therefore omitted.
Below, with reference to Fig. 4, the method according to the manufacture semiconductor package part of the exemplary embodiment of inventive concept is described.
With reference to Fig. 4, the method manufacturing semiconductor package part comprises: prepare substrate, substrate comprises the wiring pattern 140 formed by Cu.Next, wiring pattern 140 is sequentially formed the first metal. plating layer 110, comprises second metal. plating layer 120 of Cu and OSP layer 130, to form the overlay coating 100 covered on wiring pattern 140.
Then, being placed on substrate by soldered semiconductor device, thus semiconductor device is contacted with wiring pattern by the solder be arranged between semiconductor device and wiring pattern 140.
Then, semiconductor device is made to be connected to substrate by welding.Such as, when welding beginning, first OSP layer 130 is removed by scaling powder, to expose the surface of the fresh cleaning of the second metal. plating layer 120 comprising Cu.In this case, can be soaked well on the surface at Cu with the Cu surface contact of the fresh cleaning of the second metal. plating layer 120 by the solder of high temperature melting.After welding terminates, the Cu in the second metal. plating layer 120 can fuse in solder completely, and can not make the welding property-deterioration of solder, thus solder and the first metal. plating layer 110 finally form firmly interface cohesion.
Overlay coating according to the present invention's design has the high temperature circulation reliability identical with the Cu-Ni-Au coating of prior art, but production cost is no more than 10% of Cu-Ni-Au coating, can be applied to the surface of the electronic devices and components of such as PCB or other needs welding.
Although illustrate and describe the embodiment of inventive concept at this, it will be apparent to one skilled in the art that when not departing from the spirit and scope of the inventive concept be defined by the claims, various modifications and variations can be made.
Claims (10)
1. an overlay coating, described overlay coating comprises:
First metal. plating layer, covers on protected material;
Second metal. plating layer, is formed on described first metal. plating layer; And
Organic solderability preservative layer, is formed on described second metal. plating layer,
Wherein, described second metal. plating layer comprises copper.
2. overlay coating according to claim 1, wherein, the copper in described second metal. plating layer fuses in solder completely when welding.
3. overlay coating according to claim 1, wherein, described protected material is arrange on a printed circuit and the wiring pattern will be connected with solder.
4. overlay coating according to claim 1, wherein, the thickness of described second metal. plating layer is in the scope of 0.05 μm to 2 μm.
5. overlay coating according to claim 4, wherein, the thickness of described second metal. plating layer is in the scope of 0.15 μm to 0.95 μm.
6. overlay coating according to claim 2, wherein, described first metal. plating layer comprises nickel.
7. overlay coating according to claim 6, wherein, be included in nickel in described first metal. plating layer after welding terminates with solder bonds.
8. overlay coating according to claim 1, wherein, the thickness of described first metal. plating layer is in the scope of 1 μm to 20 μm.
9. overlay coating according to claim 1, wherein, the thickness of described organic solderability preservative layer is in the scope of 0.05 μm to 2 μm.
10. a semiconductor package part, described semiconductor package part comprises:
Substrate;
Wiring pattern, is arranged on the substrate;
Overlay coating, is formed on described wiring pattern; And
Semiconductor device, is welded on described wiring pattern by described overlay coating,
Wherein, described overlay coating comprises:
First metal. plating layer, covers on described wiring pattern;
Second metal. plating layer, is formed on described first metal. plating layer; And
Organic solderability preservative layer, is formed on described second metal. plating layer,
Wherein, described second metal. plating layer comprises copper, and the copper in described second metal. plating layer fuses in solder completely when welding.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510337419.0A CN104981092A (en) | 2015-06-17 | 2015-06-17 | Surface coating and semiconductor packaging part including same |
| CN201710192302.7A CN106954335B (en) | 2015-06-17 | 2015-06-17 | Overlay coating and semiconductor package part including the overlay coating |
| KR1020150161042A KR102410017B1 (en) | 2015-06-17 | 2015-11-17 | Methods for manufacturing printed circuit board and semiconductor package |
| US15/183,868 US10049970B2 (en) | 2015-06-17 | 2016-06-16 | Methods of manufacturing printed circuit board and semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510337419.0A CN104981092A (en) | 2015-06-17 | 2015-06-17 | Surface coating and semiconductor packaging part including same |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710192302.7A Division CN106954335B (en) | 2015-06-17 | 2015-06-17 | Overlay coating and semiconductor package part including the overlay coating |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104981092A true CN104981092A (en) | 2015-10-14 |
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| CN201710192302.7A Active CN106954335B (en) | 2015-06-17 | 2015-06-17 | Overlay coating and semiconductor package part including the overlay coating |
| CN201510337419.0A Pending CN104981092A (en) | 2015-06-17 | 2015-06-17 | Surface coating and semiconductor packaging part including same |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710192302.7A Active CN106954335B (en) | 2015-06-17 | 2015-06-17 | Overlay coating and semiconductor package part including the overlay coating |
Country Status (2)
| Country | Link |
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| KR (1) | KR102410017B1 (en) |
| CN (2) | CN106954335B (en) |
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| KR20220109642A (en) * | 2021-01-29 | 2022-08-05 | 엘지이노텍 주식회사 | Circuit board and package substrate including the same |
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| KR100547352B1 (en) * | 2004-07-06 | 2006-01-26 | 삼성전기주식회사 | Method for manufacturing BGA package using Organic Solderability Preservatives |
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2015
- 2015-06-17 CN CN201710192302.7A patent/CN106954335B/en active Active
- 2015-06-17 CN CN201510337419.0A patent/CN104981092A/en active Pending
- 2015-11-17 KR KR1020150161042A patent/KR102410017B1/en active IP Right Grant
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Also Published As
| Publication number | Publication date |
|---|---|
| KR102410017B1 (en) | 2022-06-16 |
| KR20160149130A (en) | 2016-12-27 |
| CN106954335B (en) | 2019-09-17 |
| CN106954335A (en) | 2017-07-14 |
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