CN104980129B - A kind of scan flip-flop circuit and its design method based on Hewlett-Packard's memristor - Google Patents
A kind of scan flip-flop circuit and its design method based on Hewlett-Packard's memristor Download PDFInfo
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- CN104980129B CN104980129B CN201510410407.6A CN201510410407A CN104980129B CN 104980129 B CN104980129 B CN 104980129B CN 201510410407 A CN201510410407 A CN 201510410407A CN 104980129 B CN104980129 B CN 104980129B
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Abstract
The present invention relates to a kind of scan flip-flop circuit and its design method based on Hewlett-Packard's memristor.The scan flip-flop circuit, including master-slave flip-flop, alternative data selector, storage control module, passback control module and memristor；The master-slave flip-flop is connected with the alternative data selector, storage control module, passback control module respectively, and the storage control module and passback control module are additionally coupled to the memristor；The storage control module is used to control the data transfer of the master-slave flip-flop to memristor；The passback control module is for controlling the data back in the memristor to the master-slave flip-flop.The present invention is realized before whole trigger is powered down, and by storage control module, the data kept in master-slave flip-flop are stored into memristor；When trigger is re-powered, memristor says that the data preserved can be back in master-slave flip-flop by returning control circuit.
Description
Technical field
The present invention relates to semiconductor integrated circuit design field, is a kind of special trigger standard cell circuit, is applicable in
Low power dissipation design in IC scanning chain technology, be specially a kind of scan flip-flop circuit based on Hewlett-Packard's memristor and
Its design method.
Background technology
Resistance, capacitance and inductance are three big basic devices of circuit, and 1971, Prof. Leon Chua were theoretically pre-
The 4th kind of basic device has been surveyed, and has been named as memristor.Two layers of nano level titanium deoxid film is clipped in two by Hewlett-Packard
In a platinized platinum, wherein one layer doped with Lacking oxygen, equivalent to semiconductor, in addition one layer doped with Lacking oxygen, equivalent to exhausted
Edge body, announced successfully to produce nano level memristor in 2008, and was experimentally confirmed the device and has memory function.Root
According to memristor characteristic, existing memory technology may can be substituted in the future, the research on memristor is largely promoted.Separately
Outside, CMOS technology of the memristor also than current mainstream in terms of complexity is prepared is simple, and corresponding manufacture cost is also lower.
For convenience of Computer Simulation, for the memristor of Hewlett-Packard, much research and propose a kind of imitative based on SPICE
True mode；It is proposed that a kind of flip-flop design of embedded memristor, when the trigger does not support sweep test operating mode.
In digital integrated electronic circuit design for Measurability, sweep trigger is to form scan chain essential elements, and all test vectors all pass through
Cross displacement and be input to these triggers, as observer nodes.Under some working environments, segment chip is in test job pattern
Under power consumption may be than the high several times of chip power-consumption under normal mode of operation, it is possible to can damage chip or test setting
It is standby.Scan flip-flop circuit proposed by the present invention based on memristor, before whole trigger is powered down, is controlled by storing
Module, the data kept in master-slave flip-flop is stored into memristor.When trigger is re-powered, memristor says what is preserved
Data can be fed back in master-slave flip-flop by feedback control circuit.So as to during sweep test, pass through herein
Some down circuitries are reached the target of Low-power test by carried memristor sweep trigger.
The content of the invention
It is an object of the invention to provide a kind of scan flip-flop circuit based on Hewlett-Packard's memristor and its design side
Method, the circuit are supported power-off work, that is, are realized before whole trigger is powered down, by storage control module, principal and subordinate
The data kept in trigger are stored into memristor；When trigger is re-powered, memristor says that the data preserved can lead to
Passback control circuit is crossed to be back in master-slave flip-flop.
To achieve the above object, the technical scheme is that：A kind of scan flip-flop circuit based on Hewlett-Packard's memristor,
Including master-slave flip-flop, alternative data selector, storage control module, passback control module and memristor；The principal and subordinate touches
Hair device is connected with the alternative data selector, storage control module, passback control module respectively, the storage control module
The memristor is additionally coupled to passback control module；The storage control module is used for the data for controlling the master-slave flip-flop
It is transmitted to memristor；The passback control module is for controlling the data back in the memristor to the master-slave flip-flop.
In an embodiment of the present invention, the master-slave flip-flop includes first to fourth transmission gate, first to fourth NOT gate；
Input terminal of the input terminal of first transmission gate as the master-slave flip-flop, is connected to the alternative data selector
Output terminal, the output terminal of first transmission gate is connected through the first NOT gate, the second NOT gate with the input terminal of the 3rd transmission gate, described
The output terminal of first transmission gate is also connected through the second transmission gate with the input terminal of the 3rd transmission gate, the output of the 3rd transmission gate
End is connected with the input terminal of the 3rd NOT gate, the input terminal of the 4th transmission gate is connected to the passback control module, the 3rd NOT gate
Output terminal be connected with the input terminal of the 4th NOT gate and be connected to the storage control module, and as the positive of the master-slave flip-flop
Output terminal, the output terminal of the 4th transmission gate is connected with the output terminal of the 4th NOT gate is connected to the storage control module, and makees
For the reversed-phase output of the master-slave flip-flop.
In an embodiment of the present invention, the control terminal of first to fourth transmission gate is controlled by clock signal, and the
First, the 3rd transmission gate is opposite with the on off operating mode of the second, the 4th transmission gate.
In an embodiment of the present invention, the storage control module include first to fourth metal-oxide-semiconductor, the first to the second with
Door；One end of first metal-oxide-semiconductor is connected with second with the first input end of door is connected to the positive output of the master-slave flip-flop
End, the other end of first metal-oxide-semiconductor is connected with one end of the 3rd metal-oxide-semiconductor is connected to one end of the memristor, the first MOS
The control terminal of pipe is connected with the control terminal of the second metal-oxide-semiconductor is connected to described first and the first input end of door, second and the second of door
Input terminal；One end of second metal-oxide-semiconductor is connected with first with the second input terminal of door is connected to the anti-phase of the master-slave flip-flop
Output terminal, the other end of second metal-oxide-semiconductor is connected with one end of the 4th metal-oxide-semiconductor is connected to the other end of the memristor；It is described
The other end ground connection of 3rd metal-oxide-semiconductor, the control terminal of the 3rd metal-oxide-semiconductor are connected with described first with the output terminal of door；Described
The other end ground connection of four metal-oxide-semiconductors, the control terminal of the 4th metal-oxide-semiconductor are connected with described second with the output terminal of door.
In an embodiment of the present invention, the passback control module includes the 5th to the 6th metal-oxide-semiconductor, current source, the 5th biography
Defeated door and the 5th NOT gate；5th metal-oxide-semiconductor is connected with the 6th metal-oxide-semiconductor, and as it is described passback control module control terminal,
One end of 5th metal-oxide-semiconductor is connected to the ground through current source, and one end of the 5th metal-oxide-semiconductor is also non-through the 5th transmission gate and the 5th
The input terminal connection of door, the output terminal of the 5th NOT gate are connected to the master-slave flip-flop, the other end of the 5th metal-oxide-semiconductor
It is connected with the other end of the memristor, and is connected to the storage control module；Recall with described one end of 6th metal-oxide-semiconductor
One end of resistance device is connected, and is connected to the storage control module, and the other end of the 6th metal-oxide-semiconductor is connected to the ground.
Present invention also offers a kind of design method of the scan flip-flop circuit based on Hewlett-Packard's memristor, including following step
Suddenly,
Step S01：Since memristor has power failure memory function, with reference to memristor and master-slave flip-flop and alternative data
Selector circuit；
Step S02：A storage control module is designed, in order to before the power-off of whole scan flip-flop circuit, control institute
State the data transfer preserved in master-slave flip-flop and preserve into memristor；
Step S03：The passback control module of design one, in order to when whole scan flip-flop circuit re-powers, control
Data back in the memristor is into the master-slave flip-flop.
In an embodiment of the present invention, the memristor is Hewlett-Packard's memristor, its mathematical model is as follows：
Wherein, RMEM is memristor all-in resistance, V（t）To be added in the voltage at memristor both ends, w (t) represents doped region field width
Degree changes with time, and D represents doped region and the total length in undoped region, and ROFF represents doped region recalling for 0 moment
Device resistance value is hindered, RON represents the memristor resistance value that undoped region was 0 moment, and w (t) values exist automatically with applied voltage or electric current
Change between 0 and D.
In an embodiment of the present invention, the master-slave flip-flop includes first to fourth transmission gate, first to fourth NOT gate；
Input terminal of the input terminal of first transmission gate as the master-slave flip-flop, is connected to the alternative data selector
Output terminal, the output terminal of first transmission gate is connected through the first NOT gate, the second NOT gate with the input terminal of the 3rd transmission gate, described
The output terminal of first transmission gate is also connected through the second transmission gate with the input terminal of the 3rd transmission gate, the output of the 3rd transmission gate
End is connected with the input terminal of the 3rd NOT gate, the input terminal of the 4th transmission gate is connected to the passback control module, the 3rd NOT gate
Output terminal be connected with the input terminal of the 4th NOT gate and be connected to the storage control module, and as the positive of the master-slave flip-flop
Output terminal, the output terminal of the 4th transmission gate is connected with the output terminal of the 4th NOT gate is connected to the storage control module, and makees
For the reversed-phase output of the master-slave flip-flop.
In an embodiment of the present invention, the storage control module include first to fourth metal-oxide-semiconductor, the first to the second with
Door；One end of first metal-oxide-semiconductor is connected with second with the first input end of door is connected to the positive output of the master-slave flip-flop
End, the other end of first metal-oxide-semiconductor is connected with one end of the 3rd metal-oxide-semiconductor is connected to one end of the memristor, the first MOS
The control terminal of pipe is connected with the control terminal of the second metal-oxide-semiconductor is connected to described first and the first input end of door, second and the second of door
Input terminal；One end of second metal-oxide-semiconductor is connected with first with the second input terminal of door is connected to the anti-phase of the master-slave flip-flop
Output terminal, the other end of second metal-oxide-semiconductor is connected with one end of the 4th metal-oxide-semiconductor is connected to the other end of the memristor；It is described
The other end ground connection of 3rd metal-oxide-semiconductor, the control terminal of the 3rd metal-oxide-semiconductor are connected with described first with the output terminal of door；Described
The other end ground connection of four metal-oxide-semiconductors, the control terminal of the 4th metal-oxide-semiconductor are connected with described second with the output terminal of door.
In an embodiment of the present invention, the passback control module includes the 5th to the 6th metal-oxide-semiconductor, current source, the 5th biography
Defeated door and the 5th NOT gate；5th metal-oxide-semiconductor is connected with the 6th metal-oxide-semiconductor, and as it is described passback control module control terminal,
One end of 5th metal-oxide-semiconductor is connected to the ground through current source, and one end of the 5th metal-oxide-semiconductor is also non-through the 5th transmission gate and the 5th
The input terminal connection of door, the output terminal of the 5th NOT gate are connected to the master-slave flip-flop, the other end of the 5th metal-oxide-semiconductor
It is connected with the other end of the memristor, and is connected to the storage control module；Recall with described one end of 6th metal-oxide-semiconductor
One end of resistance device is connected, and is connected to the storage control module, and the other end of the 6th metal-oxide-semiconductor is connected to the ground.
Compared to the prior art, the invention has the advantages that：
1st, the present invention combines memristor with into traditional master-slave flip-flop, and traditional master-slave flip-flop is not supported
Operating mode is powered off, and power-off Working mould can be supported by the memory action of memristor, the memristor sweep trigger of Combination nova
Formula；
2nd, in testing scanning chain circuit, memristor sweep trigger proposed by the invention can significantly reduce survey
Try power consumption.
Brief description of the drawings
Fig. 1 is Hewlett-Packard's memory resistor structure.
Fig. 2 is memristor simulation waveform.
Fig. 3 is the scan flip-flop circuit functional block diagram of the invention based on Hewlett-Packard's memristor.
Fig. 4 is the scan flip-flop circuit schematic diagram of the invention based on Hewlett-Packard's memristor.
Embodiment
Below in conjunction with the accompanying drawings, technical scheme is specifically described.
The design process of the scan flip-flop circuit based on Hewlett-Packard's memristor of the present invention is as follows,
Step S01：Using existing CMOS master-slave flip-flops circuit engineering；Using Hewlett-Packard's nanometer announced in 2008
Level memory resistor, has power failure memory function, its mathematical model is as follows：
Wherein, RMEM be memristor resistance value, V（t）For memristor both end voltage, w (t) represents doped region width at any time
Between change, D represents the total length in doped region and undoped region, and ROFF represents that doped region hinders for the memristor at 0 moment
Value, RON represent the memristor resistance value that undoped region was 0 moment, w (t) values with applied voltage or electric current automatically 0 and D it
Between change；
Step S02：Step S01 is carried two units to combine, control electricity is stored by design data therebetween
Road and the linking of data back control circuit, which is core of the present invention.
Step S03：Before the power-off of whole memristor sweep trigger, by data control block circuit function, principal and subordinate
The data preserved in trigger, by controlling transmission into memristor；
Step S04：Whole memristor sweep trigger can be powered down, and be stored in the data in master-slave flip-flop originally disconnected
During electricity, it is saved in always in memristor；
Step S05：Whole memristor sweep trigger re-powers the moment, by the effect of data back control module,
Data back in memristor is into master-slave flip-flop.
As shown in figure 3, a kind of scan flip-flop circuit based on Hewlett-Packard's memristor of the present invention, using existing CMOS master
Slave flipflop circuit engineering, using Hewlett-Packard's nanoscale memory resistor announced in 2008（It is as shown in Figure 1 Hewlett-Packard's memristor
Part structure）, Fig. 2 RON=1 K Ω, ROFF=100 K Ω, RINITThe memristor SPICE model emulations of=80 K Ω：（a）
Application frequency is 1Hz, and amplitude is the sine wave of 1.5V；（b）Apply the corresponding current waveform of sinusoidal voltage source；（c）Memristor allusion quotation
Type V-I characteristic curves；（d）Memristor change in resistance waveform.
The scan flip-flop circuit of the present invention, its composition include master-slave flip-flop and two choosings being connected with the master-slave flip-flop
One data selector, storage control module, passback control module, further include a memristor, which controls with the storage
Module is connected with passback control module；The storage control module is used to control the data transfer of the master-slave flip-flop to memristor
Device；The passback control module is for controlling the data back in the memristor to the master-slave flip-flop.
As shown in figure 4, master-slave flip-flop is made of tetra- NOT gates of tetra- transmission gates of TG1-TG4 and U1-U4；TG1-TG4's
Control terminal is controlled by clock signal（CLK1, CLK2 in figure）, and first and the 3rd transmission gate and second and the 4th transmission gate
On off operating mode it is opposite.
As shown in figure 4, storage control module is made of tetra- metal-oxide-semiconductors of M1-M4 and U6, U7 two with door；MIN is control
Signal.When MIN is high level, data that master-slave flip-flop is kept, which are transferred in memristor X1, to be preserved.If control
0 value retained in master-slave flip-flop is stored into memristor, then Q=0, QB=1 and MIN=1, M1 and M2 conductings, U7
Output terminal be low level, M4 is not turned on, and the output terminal of U6 is high level, M3 conductings.The starting point of store path since QB,
By M2, X1 (memristor) and M3, and finally it is grounded.
As shown in figure 4, passback control module is made of two metal-oxide-semiconductors of M5, M6, current source I, transmission gate TG5 and NOT gate U5；
MOUT and MOUT2 is passback control signal.When MOUT is high level, passback control module handle is saved in memristor X1
In signal value pass back in master-slave flip-flop, when MOUT is low level, passback control module be not turned on.When MOUT is height
During level, M6, M5 and TG5 conducting, low current are flowed out from I, by M5, memristor X1, M6, finally reach ground terminal, memristor
In high level passed back to by M5 and TG5 in master-slave flip-flop.When the value kept in memristor is that 0, MOUT is high level
When, M6, M5 and TG5 are switched on, and the low level in memristor is passed back in master-slave flip-flop by M6 and TG5.
Allow those skilled in the art to become more apparent upon the present invention preferably to say to address, illustrate the specific implementation of the present invention below
Example.
As shown in figure 4, X1 represents memristor, its parameter is the K Ω of RON=1 K Ω, ROFF=100, RINIT=80
KΩ.CLK and CLK2 represents clock signal, and Q and QB represent output signal.Whole circuit is by alternative data selector, master
Slave flipflop, storage control module and passback control module composition.SE, SI and DIN form the input/output terminal of selector, SE
Signal is used for switched scan test data and normal logic data, i.e., when SE=1 (scan_enable=1), DIN leads to
Cross the master-slave flip-flop that selector is input to inside；As SE=0, SI signals will be input into the master-slave flip-flop of inside
In.Four transmission gate TG1-TG4, complete master-slave flip-flop is formed with U1, U2, U3 and U4 is closed
If the data 1 in master-slave flip-flop are controlled to be stored in memristor, then Q=1, QB=0 and MIN
=1, M1 and M2 are switched on, and the output terminal of U7 is high level, and M4 conductings, the output terminal of U6 is low level, and M3 is not turned on, and signal passes
Defeated path is since Q, by M1, X1 and M4, and is finally grounded.
After data in master-slave flip-flop are saved in memristor, whole memristor sweep trigger can be powered down,
During power-off can preserve the data always according to memristor characteristic, memristor.
At the time of whole memristor sweep trigger is re-powered, passback control module is first at once being stored in memristor
In data, be saved in by returning control module, then data in master-slave flip-flop.Return control module by M6, M5, TG5,
X1, I and U5 are formed, and MOUT and MOUT2 are passback control signals.When MOUT is high level, feedback circuit handle is saved in
Signal value in memristor is passed back in master-slave flip-flop, and when MOUT is low level, feedback circuit module is not turned on.Memristor
The logic state of storage value embodied by the resistance value of memristor, it is assumed that remain high level 1 in memristor, work as MOUT
For high level when, M6, M5 and TG5 conducting, low current flows out from I, by M6, memristor X1, M5, finally reaches ground terminal, recall
High level in resistance device is passed back in master-slave flip-flop by M6 and TG5.When the value kept in memristor is that 0, MOUT is high electricity
Usually, M6, M5 and TG5 are switched on, and the low level in memristor is passed back in master-slave flip-flop by M6 and TG5.
In above procedure, whole memristor sweep trigger can be in power-down mode for some time, so as to fulfill low work(
Consumption, can be very good to be cited in testing scanning chain circuit design.
Above example, has carried out the purpose of the present invention, technical solution and beneficial effect certain elaboration, should be understood that
, the application case of the simply present invention described above, is formed for different using memristor combination traditional flip-flop
The circuit design method of new trigger, the present invention can apply, all in protection scope of the present invention.
Above is presently preferred embodiments of the present invention, all changes made according to technical solution of the present invention, caused function are made
During with scope without departing from technical solution of the present invention, protection scope of the present invention is belonged to.
Claims (4)
- A kind of 1. scan flip-flop circuit based on Hewlett-Packard's memristor, it is characterised in that：Including master-slave flip-flop, alternative data Selector, storage control module, passback control module and memristor；The master-slave flip-flop is selected with the alternative data respectively Device, storage control module, passback control module connection are selected, the storage control module and passback control module are additionally coupled to described Memristor；The storage control module is used to control the data transfer of the master-slave flip-flop to memristor；The passback control Module is for controlling the data back in the memristor to the master-slave flip-flop；The master-slave flip-flop includes first to fourth transmission gate, first to fourth NOT gate；The input terminal of first transmission gate As the input terminal of the master-slave flip-flop, the output terminal of the alternative data selector, first transmission gate are connected to Output terminal be connected through the first NOT gate, the second NOT gate with the input terminal of the 3rd transmission gate, the output terminal of first transmission gate is also It is connected through the second transmission gate with the input terminal of the 3rd transmission gate, the input of the output terminal and the 3rd NOT gate of the 3rd transmission gate End, the input terminal of the 4th transmission gate are connected and are connected to the passback control module, the output terminal and the 4th NOT gate of the 3rd NOT gate Input terminal be connected and be connected to the storage control module, and passed as the positive output end of the master-slave flip-flop, the described 4th The output terminal of defeated door is connected with the output terminal of the 4th NOT gate is connected to the storage control module, and as the master-slave flip-flop Reversed-phase output；The storage control module includes first to fourth metal-oxide-semiconductor, the first to the second and door；One end of first metal-oxide-semiconductor with Second is connected with the first input end of door is connected to the positive output end of the master-slave flip-flop, the other end of first metal-oxide-semiconductor It is connected with one end of the 3rd metal-oxide-semiconductor and is connected to one end of the memristor, control terminal and the second metal-oxide-semiconductor of first metal-oxide-semiconductor Control terminal be connected be connected to described first with the first input end of door, second with the second input terminal of door；The one of second metal-oxide-semiconductor End is connected with the second input terminal of door with first and is connected to the reversed-phase output of the master-slave flip-flop, second metal-oxide-semiconductor it is another One end is connected with one end of the 4th metal-oxide-semiconductor is connected to the other end of the memristor；The other end ground connection of 3rd metal-oxide-semiconductor, institute The control terminal for stating the 3rd metal-oxide-semiconductor is connected with described first with the output terminal of door；The other end ground connection of 4th metal-oxide-semiconductor is described The control terminal of 4th metal-oxide-semiconductor is connected with described second with the output terminal of door；The passback control module includes the 5th to the 6th metal-oxide-semiconductor, current source, the 5th transmission gate and the 5th NOT gate；Described 5th The grid of metal-oxide-semiconductor is connected with the grid of the 6th metal-oxide-semiconductor, and as the control terminal of the passback control module, the 5th MOS One end of pipe is connected to the ground through current source, the input terminal of one end of the 5th metal-oxide-semiconductor also through the 5th transmission gate and the 5th NOT gate Connection, the output terminal of the 5th NOT gate are connected to the master-slave flip-flop, the other end and the memristor of the 5th metal-oxide-semiconductor The other end connection of device, and it is connected to the storage control module；One end of 6th metal-oxide-semiconductor and one end of the memristor It is connected, and is connected to the storage control module, the other end of the 6th metal-oxide-semiconductor is connected to the ground.
- A kind of 2. scan flip-flop circuit based on Hewlett-Packard's memristor according to claim 1, it is characterised in that：Described The control terminal of one transmission gate to the 4th transmission gate is controlled by clock signal, and the first, the 3rd transmission gate and the second, the 4th transmission The on off operating mode of door is opposite.
- A kind of 3. design method of the scan flip-flop circuit based on Hewlett-Packard's memristor, it is characterised in that：Include the following steps,Step S01：Since memristor has power failure memory function, selected with reference to memristor and master-slave flip-flop and alternative data Device circuit；Step S02：A storage control module is designed, in order to before the power-off of whole scan flip-flop circuit, control the master The data transfer preserved and preservation in slave flipflop is into memristor；Step S03：The passback control module of design one, in order to when whole scan flip-flop circuit re-powers, described in control Data back in memristor is into the master-slave flip-flop；The master-slave flip-flop includes first to fourth transmission gate, first to fourth NOT gate；The input terminal of first transmission gate As the input terminal of the master-slave flip-flop, the output terminal of the alternative data selector, first transmission gate are connected to Output terminal be connected through the first NOT gate, the second NOT gate with the input terminal of the 3rd transmission gate, the output terminal of first transmission gate is also It is connected through the second transmission gate with the input terminal of the 3rd transmission gate, the input of the output terminal and the 3rd NOT gate of the 3rd transmission gate End, the input terminal of the 4th transmission gate are connected and are connected to the passback control module, the output terminal and the 4th NOT gate of the 3rd NOT gate Input terminal be connected and be connected to the storage control module, and passed as the positive output end of the master-slave flip-flop, the described 4th The output terminal of defeated door is connected with the output terminal of the 4th NOT gate is connected to the storage control module, and as the master-slave flip-flop Reversed-phase output；The storage control module includes first to fourth metal-oxide-semiconductor, the first to the second and door；One end of first metal-oxide-semiconductor with Second is connected with the first input end of door is connected to the positive output end of the master-slave flip-flop, the other end of first metal-oxide-semiconductor It is connected with one end of the 3rd metal-oxide-semiconductor and is connected to one end of the memristor, control terminal and the second metal-oxide-semiconductor of first metal-oxide-semiconductor Control terminal be connected be connected to described first with the first input end of door, second with the second input terminal of door；The one of second metal-oxide-semiconductor End is connected with the second input terminal of door with first and is connected to the reversed-phase output of the master-slave flip-flop, second metal-oxide-semiconductor it is another One end is connected with one end of the 4th metal-oxide-semiconductor is connected to the other end of the memristor；The other end ground connection of 3rd metal-oxide-semiconductor, institute The control terminal for stating the 3rd metal-oxide-semiconductor is connected with described first with the output terminal of door；The other end ground connection of 4th metal-oxide-semiconductor is described The control terminal of 4th metal-oxide-semiconductor is connected with described second with the output terminal of door；The passback control module includes the 5th to the 6th metal-oxide-semiconductor, current source, the 5th transmission gate and the 5th NOT gate；Described 5th The grid of metal-oxide-semiconductor is connected with the grid of the 6th metal-oxide-semiconductor, and as the control terminal of the passback control module, the 5th MOS One end of pipe is connected to the ground through current source, the input terminal of one end of the 5th metal-oxide-semiconductor also through the 5th transmission gate and the 5th NOT gate Connection, the output terminal of the 5th NOT gate are connected to the master-slave flip-flop, the other end and the memristor of the 5th metal-oxide-semiconductor The other end connection of device, and it is connected to the storage control module；One end of 6th metal-oxide-semiconductor and one end of the memristor It is connected, and is connected to the storage control module, the other end of the 6th metal-oxide-semiconductor is connected to the ground.
- 4. a kind of design method of scan flip-flop circuit based on Hewlett-Packard's memristor according to claim 3, its feature It is：The memristor is Hewlett-Packard's memristor, its mathematical model is as follows：Wherein, RMEMFor memristor all-in resistance, V（t）To be added in the voltage at memristor both ends, w (t) represent doped region width with The change of time, D represent doped region and the total length in undoped region, ROFFRepresent that doped region hinders for the memristor at 0 moment Value, RONRepresent the memristor resistance value that undoped region was 0 moment, w (t) values with applied voltage or electric current automatically 0 and D it Between change.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510410407.6A CN104980129B (en) | 2015-07-14 | 2015-07-14 | A kind of scan flip-flop circuit and its design method based on Hewlett-Packard's memristor |
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| CN105634446B (en) * | 2016-01-27 | 2018-03-09 | 华中科技大学 | A kind of non-volatile set-reset flip-floop circuit based on memristor |
| CN112910457B (en) * | 2021-01-21 | 2023-04-14 | 西南大学 | Memristor-based data selector and IC topological structure thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579249A (en) * | 2013-10-21 | 2015-04-29 | 创意电子股份有限公司 | Scan flip-flop and related method |
| CN204707104U (en) * | 2015-07-14 | 2015-10-14 | 福州大学 | A kind of scan flip-flop circuit based on Hewlett-Packard's memristor |
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| JP2008219491A (en) * | 2007-03-05 | 2008-09-18 | Nec Electronics Corp | Master slave type flip-flop circuit and latch circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579249A (en) * | 2013-10-21 | 2015-04-29 | 创意电子股份有限公司 | Scan flip-flop and related method |
| CN204707104U (en) * | 2015-07-14 | 2015-10-14 | 福州大学 | A kind of scan flip-flop circuit based on Hewlett-Packard's memristor |
Non-Patent Citations (2)
| Title |
|---|
| Low Power Scan by Partitioning and Scan Hold;Efi Arvaniti等;《IEEE International Symposium on Design&Diagnostics of Electronic Circuits &Systems》;20120331;第262-265页 * |
| Zero-Sleep-Leakage Flip-Flop Circuit With Conditional-Storing Memristor Retention Latch;Chul-Moon Jung等;《IEEE TRANSACTIONS ON NANOTECHNOLOGY》;20120331;第360-365页 * |
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