CN204707104U - A kind of scan flip-flop circuit based on Hewlett-Packard's memristor - Google Patents

A kind of scan flip-flop circuit based on Hewlett-Packard's memristor Download PDF

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Publication number
CN204707104U
CN204707104U CN201520505946.3U CN201520505946U CN204707104U CN 204707104 U CN204707104 U CN 204707104U CN 201520505946 U CN201520505946 U CN 201520505946U CN 204707104 U CN204707104 U CN 204707104U
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memristor
flop
semiconductor
oxide
metal
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陈传东
陈群超
江浩
王仁平
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Fuzhou University
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Fuzhou University
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Abstract

The utility model relates to a kind of scan flip-flop circuit based on Hewlett-Packard's memristor.The alternative data selector, storage control module, the passback control module that comprise master-slave flip-flop and be connected with this master-slave flip-flop, also comprise a memristor, this memristor and described storage control module and return control module and be connected; Described storage control module is for controlling the transfer of data of described master-slave flip-flop to memristor; Described passback control module is for controlling the data back extremely described master-slave flip-flop in described memristor.The utility model, in conjunction with memristor and master-slave flip-flop, achieves the sweep trigger can supporting power-off work.

Description

A kind of scan flip-flop circuit based on Hewlett-Packard's memristor
Technical field
The utility model relates to semiconductor integrated circuit design field, is a kind of special trigger criteria element circuit, is applicable to the low power dissipation design in IC scanning chain technology, be specially a kind of scan flip-flop circuit based on Hewlett-Packard's memristor.
Background technology
Resistance, electric capacity and inductance are three large basic devices of circuit, and 1971, Prof. Leon Chua predicted the 4th kind of basic device theoretically, and is named as memristor.Two-layer nano level titanium deoxid film is clipped in two platinized platinums by Hewlett-Packard, wherein one deck is doped with Lacking oxygen, be equivalent to semiconductor, one deck is not doped with Lacking oxygen in addition, be equivalent to insulator, announced successfully to produce nano level memristor in 2008, and prove that this device has memory function by experiment.According to memristor characteristic, may can substitute existing memory technology in the future, the research about memristor is advanced in a large number.In addition, memristor is also simple than the CMOS technology of current main flow in preparation complexity, and corresponding manufacturing cost is also lower.
For convenience of Computer Simulation, for the memristor of Hewlett-Packard, much research and propose a kind of simulation model based on SPICE; Someone proposes a kind of flip flop design of embedded memristor, when sweep test mode of operation do not supported by this trigger.In digital integrated circuit design for Measurability, sweep trigger forms scan chain essential elements, and all test vectors are all input to these triggers, as observer nodes through displacement.Under some operational environment, segment chip is in power consumption under test job pattern may than the chip power-consumption high several times be under normal mode of operation, likely can defective chip or testing equipment.The scan flip-flop circuit based on memristor that the present invention proposes, before whole trigger is de-energized, by storage control module, is stored into the data kept in master-slave flip-flop in memristor.When trigger is re-powered, memristor says that the data of preserving can be fed back in master-slave flip-flop by feedback control circuit.Thus in sweep test process, by this paper institute memristor sweep trigger of carrying some down circuitry, the target of Low-power test can be reached.
Summary of the invention
The purpose of this utility model is to provide a kind of scan flip-flop circuit based on Hewlett-Packard's memristor, and this circuit supports power-off work, and low in energy consumption.
For achieving the above object, the technical solution of the utility model is: a kind of scan flip-flop circuit based on Hewlett-Packard's memristor, the alternative data selector, storage control module, the passback control module that comprise master-slave flip-flop and be connected with this master-slave flip-flop, also comprise a memristor, this memristor and described storage control module and return control module and be connected; Described storage control module is for controlling the transfer of data of described master-slave flip-flop to memristor; Described passback control module is for controlling the data back extremely described master-slave flip-flop in described memristor.
In the utility model embodiment, described master-slave flip-flop comprises first to fourth transmission gate, first to fourth not gate, the input of described first transmission gate is as the input of described master-slave flip-flop, be connected to the output of described alternative data selector, the output of described first transmission gate is through the first not gate, second not gate is connected with the input of the 3rd transmission gate, the output of described first transmission gate is also connected through the input of the second transmission gate with the 3rd transmission gate, the output of described 3rd transmission gate and the input of the 3rd not gate, the input of the 4th transmission gate is connected to described passback control module, the output of described 3rd not gate is connected to described storage control module with the input of the 4th not gate, and as the positive output end of described master-slave flip-flop, the output of described 4th transmission gate is connected to described storage control module with the output of the 4th not gate, and as the reversed-phase output of described master-slave flip-flop.
In the utility model embodiment, described first transmission gate controls to the control end of the 4th transmission gate by clock signal, and the first, the 3rd transmission gate is contrary with the on off operating mode of the second, the 4th transmission gate.
In the utility model embodiment, described storage control module comprises first to fourth metal-oxide-semiconductor, the first to the second and door; One end of described first metal-oxide-semiconductor is connected to the positive output end of described master-slave flip-flop with second with the first input end of door, the other end of described first metal-oxide-semiconductor is connected to one end of described memristor with one end of the 3rd metal-oxide-semiconductor, the control end of described first metal-oxide-semiconductor be connected with the control end of the second metal-oxide-semiconductor to described first with the first input end of door, second and the second input of door; One end of described second metal-oxide-semiconductor is connected to the reversed-phase output of described master-slave flip-flop with first with the second input of door, and the other end of described second metal-oxide-semiconductor is connected to the other end of described memristor with one end of the 4th metal-oxide-semiconductor; The other end ground connection of described 3rd metal-oxide-semiconductor, the control end of described 3rd metal-oxide-semiconductor is connected with the output of door with described first; The other end ground connection of described 4th metal-oxide-semiconductor, the control end of described 4th metal-oxide-semiconductor is connected with the output of door with described second.
In the utility model embodiment, described passback control module comprises the 5th to the 6th metal-oxide-semiconductor, current source, the 5th transmission gate and the 5th not gate; Described 5th metal-oxide-semiconductor is connected with the 6th metal-oxide-semiconductor, and as the control end of described passback control module, one end of described 5th metal-oxide-semiconductor is connected to ground through current source, one end of described 5th metal-oxide-semiconductor is also connected through the input of the 5th transmission gate with the 5th not gate, the output of described 5th not gate is connected to described master-slave flip-flop, the other end of described 5th metal-oxide-semiconductor is connected with the other end of described memristor, and is connected to described storage control module; One end of described 6th metal-oxide-semiconductor is connected with one end of described memristor, and is connected to described storage control module, and the other end of described 6th metal-oxide-semiconductor is connected to ground.
Compared to prior art, the utility model has following beneficial effect:
1, the utility model combines memristor with in traditional master-slave flip-flop, and power-off mode of operation do not supported by traditional master-slave flip-flop, and by the memory action of memristor, the recalling resistance sweep trigger and can support power-off mode of operation of Combination nova;
2, in testing scanning chain circuit, what the utility model proposed recall, and resistance sweep trigger can reduce testing power consumption significantly.
Accompanying drawing explanation
Tu1Shi Hewlett-Packard memory resistor structure.
Fig. 2 is memristor simulation waveform figure.
Fig. 3 is the scan flip-flop circuit theory diagram of the utility model based on Hewlett-Packard's memristor.
Fig. 4 is the scan flip-flop circuit schematic diagram of the utility model based on Hewlett-Packard's memristor.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is specifically described.
As shown in Figure 3, a kind of scan flip-flop circuit based on Hewlett-Packard's memristor of the present utility model, adopt existing CMOS master-slave flip-flop circuit engineering, adopt the nanoscale memory resistor (being illustrated in figure 1 Hewlett-Packard's memory resistor structure) that Hewlett-Packard announces for 2008, Fig. 2 is R oN=1 K Ω, R oFF=100 K Ω, R iNITthe memristor SPICE model emulation of=80 K Ω: (a) applies frequency is 1Hz, amplitude is the sine wave of 1.5V; B () applies current waveform corresponding to sinusoidal voltage source; (c) memristor typical case V-I characteristic curve; (d) memristor change in resistance waveform.
Scan flip-flop circuit of the present utility model, it forms the alternative data selector, storage control module, the passback control module that comprise master-slave flip-flop and be connected with this master-slave flip-flop, also comprise a memristor, this memristor and described storage control module and return control module and be connected; Described storage control module is for controlling the transfer of data of described master-slave flip-flop to memristor; Described passback control module is for controlling the data back extremely described master-slave flip-flop in described memristor.
As shown in Figure 4, master-slave flip-flop is made up of TG1-TG4 tetra-transmission gates and U1-U4 tetra-not gates; The control end of TG1-TG4 controls (CLK1, CLK2 in figure) by clock signal, and first and the 3rd transmission gate with second and the 4th the on off operating mode of transmission gate contrary.
As shown in Figure 4, storage control module is made up of with door M1-M4 tetra-metal-oxide-semiconductors and U6, U7 two; MIN is control signal.When MIN is high level, the data that master-slave flip-flop keeps are transferred in memristor X1 and preserve.If 0 value controlling to keep in master-slave flip-flop is stored in memristor, then Q=0, QB=1 and MIN=1, M1 and M2 conducting, the output of U7 is low level, M4 not conducting, and the output of U6 is high level, M3 conducting.The starting point of store path from QB, through M2, X1 (memristor) and M3, and last ground connection.
As shown in Figure 4, return control module to be made up of M5, M6 two metal-oxide-semiconductors, current source I, transmission gate TG5 and not gate U5; MOUT and MOUT2 is passback control signal.When MOUT is high level, passback control module passes back to the signal value be stored in memristor X1 in master-slave flip-flop, when MOUT is low level, and the not conducting of passback control module.When MOUT is high level, M6, M5 and TG5 conducting, small area analysis flows out from I, and through M5, memristor X1, M6, last arrival point end, the high level in memristor is passed back in master-slave flip-flop by M5 and TG5.When the value kept in memristor be 0, MOUT is high level, M6, M5 and TG5 are switched on, and the low level in memristor is passed back in master-slave flip-flop by M6 and TG5.
Allowing those skilled in the art more understand the utility model for better saying to address, below specific embodiment of the utility model being described.
Embodiment:
As shown in Figure 4, X1 represents memristor, and its parameter is RON=1 K Ω, ROFF=100 K Ω, RINIT=80 K Ω.CLK and CLK2 represents clock signal, Q and QB represents output signal.Whole circuit is made up of alternative data selector, master-slave flip-flop, storage control module and passback control module.SE, SI and DIN form the input/output terminal of selector, and SE signal is used for switched scan test data and normal logic data, and namely when SE=1 (scan_enable=1), DIN is input to inner master-slave flip-flop by selector; When SE=0, SI signal will be imported in inner master-slave flip-flop.Four transmission gate TG1-TG4, in cooperation, U1, U2, U3 and U4 form complete master-slave flip-flop.
If the data 1 controlled in master-slave flip-flop are stored in memristor, so Q=1, QB=0 and MIN=1, M1 and M2 is switched on, the output of U7 is high level, M4 conducting, and the output of U6 is low level, M3 not conducting, signal transmission path from Q, through M1, X1 and M4, and last ground connection.
Data in master-slave flip-flop are saved to after in memristor, whole recall resistance sweep trigger can be de-energized, according to memristor characteristic between turnoff time, memristor can preserve this data always.
Recall resistance sweep trigger by the moment re-powered when whole, passback control module, first at once the data be stored in memristor, by passback control module, then is saved in data in master-slave flip-flop.Passback control module is made up of M6, M5, TG5, X1, I and U5, MOUT and MOUT2 is passback control signal.When MOUT is high level, feedback circuit passes back to the signal value be stored in memristor in master-slave flip-flop, when MOUT is low level, and the not conducting of feedback circuit module.The logic state of the storing value of memristor is embodied by the resistance value of memristor, suppose in memristor, to remain high level 1, when MOUT is high level, M6, M5 and TG5 conducting, small area analysis flows out from I, through M6, memristor X1, M5, last arrival point end, the high level in memristor is passed back in master-slave flip-flop by M6 and TG5.When the value kept in memristor be 0, MOUT is high level, M6, M5 and TG5 are switched on, and the low level in memristor is passed back in master-slave flip-flop by M6 and TG5.
In above process, wholely recall resistance sweep trigger and can be in power-down mode for some time, thus realize low-power consumption, can well be cited in testing scanning chain circuit design.
Above embodiment; certain elaboration has been carried out to the purpose of this utility model, technical scheme and beneficial effect; be understood that; more than set forth a just application case of the present utility model; form the circuit design method of new trigger in conjunction with traditional flip-flop for different employing memristors; the utility model can be applied, all at protection range of the present utility model.
Be more than preferred embodiment of the present utility model, all changes done according to technical solutions of the utility model, when the function produced does not exceed the scope of technical solutions of the utility model, all belong to protection range of the present utility model.

Claims (5)

1. the scan flip-flop circuit based on Hewlett-Packard's memristor, it is characterized in that: the alternative data selector, storage control module, the passback control module that comprise master-slave flip-flop and be connected with this master-slave flip-flop, also comprise a memristor, this memristor and described storage control module and return control module and be connected; Described storage control module is for controlling the transfer of data of described master-slave flip-flop to memristor; Described passback control module is for controlling the data back extremely described master-slave flip-flop in described memristor.
2. a kind of scan flip-flop circuit based on Hewlett-Packard's memristor according to claim 1, is characterized in that: described master-slave flip-flop comprises first to fourth transmission gate, first to fourth not gate, the input of described first transmission gate is as the input of described master-slave flip-flop, be connected to the output of described alternative data selector, the output of described first transmission gate is through the first not gate, second not gate is connected with the input of the 3rd transmission gate, the output of described first transmission gate is also connected through the input of the second transmission gate with the 3rd transmission gate, the output of described 3rd transmission gate and the input of the 3rd not gate, the input of the 4th transmission gate is connected to described passback control module, the output of described 3rd not gate is connected to described storage control module with the input of the 4th not gate, and as the positive output end of described master-slave flip-flop, the output of described 4th transmission gate is connected to described storage control module with the output of the 4th not gate, and as the reversed-phase output of described master-slave flip-flop.
3. a kind of scan flip-flop circuit based on Hewlett-Packard's memristor according to claim 2, it is characterized in that: described first transmission gate controls to the control end of the 4th transmission gate by clock signal, and the first, the 3rd transmission gate is contrary with the on off operating mode of the second, the 4th transmission gate.
4. a kind of scan flip-flop circuit based on Hewlett-Packard's memristor according to claim 1, is characterized in that: described storage control module comprises first to fourth metal-oxide-semiconductor, the first to the second and door; One end of described first metal-oxide-semiconductor is connected to the positive output end of described master-slave flip-flop with second with the first input end of door, the other end of described first metal-oxide-semiconductor is connected to one end of described memristor with one end of the 3rd metal-oxide-semiconductor, the control end of described first metal-oxide-semiconductor be connected with the control end of the second metal-oxide-semiconductor to described first with the first input end of door, second and the second input of door; One end of described second metal-oxide-semiconductor is connected to the reversed-phase output of described master-slave flip-flop with first with the second input of door, and the other end of described second metal-oxide-semiconductor is connected to the other end of described memristor with one end of the 4th metal-oxide-semiconductor; The other end ground connection of described 3rd metal-oxide-semiconductor, the control end of described 3rd metal-oxide-semiconductor is connected with the output of door with described first; The other end ground connection of described 4th metal-oxide-semiconductor, the control end of described 4th metal-oxide-semiconductor is connected with the output of door with described second.
5. a kind of scan flip-flop circuit based on Hewlett-Packard's memristor according to claim 1, is characterized in that: described passback control module comprises the 5th to the 6th metal-oxide-semiconductor, current source, the 5th transmission gate and the 5th not gate; Described 5th metal-oxide-semiconductor is connected with the 6th metal-oxide-semiconductor, and as the control end of described passback control module, one end of described 5th metal-oxide-semiconductor is connected to ground through current source, one end of described 5th metal-oxide-semiconductor is also connected through the input of the 5th transmission gate with the 5th not gate, the output of described 5th not gate is connected to described master-slave flip-flop, the other end of described 5th metal-oxide-semiconductor is connected with the other end of described memristor, and is connected to described storage control module; One end of described 6th metal-oxide-semiconductor is connected with one end of described memristor, and is connected to described storage control module, and the other end of described 6th metal-oxide-semiconductor is connected to ground.
CN201520505946.3U 2015-07-14 2015-07-14 A kind of scan flip-flop circuit based on Hewlett-Packard's memristor Expired - Fee Related CN204707104U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104980129A (en) * 2015-07-14 2015-10-14 福州大学 HP memristor-based scan flip-flop circuit and design method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104980129A (en) * 2015-07-14 2015-10-14 福州大学 HP memristor-based scan flip-flop circuit and design method thereof
CN104980129B (en) * 2015-07-14 2018-04-13 福州大学 A kind of scan flip-flop circuit and its design method based on Hewlett-Packard's memristor

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