CN104979381B - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
- Publication number
- CN104979381B CN104979381B CN201410128143.0A CN201410128143A CN104979381B CN 104979381 B CN104979381 B CN 104979381B CN 201410128143 A CN201410128143 A CN 201410128143A CN 104979381 B CN104979381 B CN 104979381B
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- groove
- substrate
- lining
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor device of present invention offer and its manufacturing method, the semiconductor device include：Substrate has the first conductive type, and includes：Body region has the first conductive type；Source area is formed in body region；Drift region, has the second conductive type and neighbouring body region, wherein the first conductive type are different from the second conductive type；And drain region, it is formed in drift region；Groove is formed in the substrate between body region and drift region；Gate dielectric, adjacent trenches；Lining is inside lining in groove and is abutted with gate dielectric；And gate electrode, it is formed on gate dielectric, and extend into groove.The present invention also provides the manufacturing method of this semiconductor device.A kind of semiconductor device provided by the invention and its manufacturing method can make semiconductor device have lower conducting resistance and can maintain the breakdown voltage numerical value of semiconductor device simultaneously.
Description
Technical field
The invention relates to semiconductor devices, and in particular to a kind of with channel grid electrode and extremely low
The semiconductor device and its manufacturing method of conducting resistance.
Background technology
Due to the increase to high yield device demand, two or more semiconductor devices are integrated in one chip.It is double
Polar transistor-complementary metal oxide semiconductor-lateral diffusion metal oxide semiconductor (Bipolar-CMOS-
LDMOS, BCD) it has been widely used in device integration.Bipolar transistor-complementary metal oxide semiconductor-horizontal proliferation
Metal oxide semiconductor techniques are by bipolar transistor, complementary metal oxide semiconductor (Complementary
Metal-oxide-semiconductor, CMOS) and lateral diffusion metal oxide semiconductor (Laterally diffused
Metal-oxide-semiconductor, LDMOS) Technology Integration is in one chip.In the complementary gold of bipolar transistor-
Belong in oxide semiconductor-lateral diffusion metal oxide semiconductor device, bipolar transistor is to drive high current, mutually
Benefit formula metal-oxide semiconductor (MOS) is provided for the low power consumption of digital circuit, and lateral diffusion metal oxide semiconductor fills
It sets and is provided for high voltage processing capacity.
Lateral diffusion metal oxide semiconductor device is widely used in various applications.Conducting resistance is to influence laterally to expand
An important factor for power consumption of dispersed metallic oxide semiconductor devices, resistance value are directly proportional to the power consumption of device.Due to
Increase to power saving and electronic performance demand, manufacturer continuously search for reducing lateral diffusion metal oxide semiconductor dress
The method of the electric leakage and conducting resistance set.However, the reduction of conducting resistance directly influences high closed state breakdown voltage (High
off-state breakdown voltage).Specifically, the reduction of conducting resistance can lead to high closed state breakdown voltage
Substantially reduce.Therefore, when traditional lateral diffusion metal oxide semiconductor device provides high closed state breakdown voltage,
It can not provide low on-resistance.
Lateral diffusion metal oxide semiconductor device includes drift region and body region.When the doping concentration of drift region improves
When, the conducting resistance of traditional lateral diffusion metal oxide semiconductor device can reduce.However, the raising of drift doping concentration
Also resulting in the high closed state breakdown voltage of lateral diffusion metal oxide semiconductor device reduces.
Therefore, industry need a kind of semiconductor for the improvement not having breakdown voltage related defects but with low on-resistance
Device and its manufacturing method.
Invention content
The technical problem to be solved in the present invention is to provide a kind of semiconductor device and its manufacturing methods, can make semiconductor device
The breakdown voltage numerical value of semiconductor device with lower conducting resistance and can be maintained simultaneously.
The present invention provides a kind of semiconductor device, including：Substrate has the first conductive type, and the substrate includes having the
The body region of one conductivity type, and the source area that is formed in body region, and the drift with the second conductive type and neighbouring body region
Area is moved, wherein the first conductive type is different from the second conductive type；The semiconductor device further includes：Drain region is formed in drift region；
Groove is formed in the substrate between body region and drift region；Gate dielectric, adjacent trenches；Lining, be inside lining in groove and with
Gate dielectric abuts；And gate electrode, it is formed on gate dielectric, and extend into groove.
The present invention separately provides a kind of semiconductor device, including：Substrate has the first conductive type, and has body region；Drift
Extension area pair has the second conductive type, and a upper surface in autonomous agent area extends in body region, wherein the first conductive type and the
Two conductivity types are different；Source area, is formed among the one of the drift extension area pair and a drain region, is formed in the drift and prolongs
Stretch area pair it is another among；Groove is formed in above-mentioned drift extension area among one of them, and extends into and prolong positioned at the drift
Stretch the body region part between area pair；Gate dielectric, adjacent trenches；Lining is inside lining in groove and is abutted with gate dielectric；
And gate electrode, it is formed on gate dielectric, and extend into groove.
The present invention provides a kind of manufacturing method of semiconductor device again, including：Substrate is provided, there is the first conductive type；Shape
At body region in substrate, and body region has the first conductive type；Drift region is formed in substrate, drift region has the second conduction
Type and neighbouring body region, wherein the first conductive type are different from the second conductive type；Shallow trench isolation is formed in body region and drift region
Between substrate in；Dielectric layer is formed in substrate；Shallow trench isolation and part of dielectric layer are removed to be respectively formed groove and neighbour
The gate dielectric of nearly groove；It is formed in lining and is lining in groove and is abutted with gate dielectric；Gate electrode is formed in grid to be situated between
In electric layer and extend into groove；And source area is in body region and drain region is in drift region for formation.
The present invention separately provides a kind of manufacturing method of semiconductor device, including：Substrate is provided, there is the first conductive type；Shape
At body region in the substrate, and the body region has the first conductive type；Drift extension area is formed in the body region, being somebody's turn to do
Extension area drift about to the second conductive type, wherein the first conductive type is different from the second conductive type；Form shallow trench isolation
In above-mentioned drift extension area to one of among, wherein the shallow trench isolation extends between the drift extension area pair
Body region part；Dielectric layer is formed in the substrate；The shallow trench isolation and the part dielectric layer are removed to be respectively formed one
Groove and one adjacent to the groove gate dielectric；It is formed in lining and is lining in the groove and is abutted with the gate dielectric；It is formed
Gate electrode is on the gate dielectric and extending into the groove；And formed source area in the drift extension area pair one it
In and drain region in the drift extension area pair it is another among.
Semiconductor device provided by the invention and its manufacturing method make semiconductor device have the grid being formed in groove
Electrode.The gate electrode for extending into groove provides shorter electric current spacing, make semiconductor device have lower conducting resistance and
The breakdown voltage numerical value of semiconductor device can be maintained simultaneously.
Description of the drawings
Fig. 1 is the sectional view of conventional semiconductor device；
Fig. 2A -2J be the embodiment of the present invention semiconductor device in its manufacturing process the sectional view in each stage or on regard
Figure；
Fig. 3 A-3J be other embodiments of the present invention semiconductor device in its manufacturing process the sectional view in each stage or on
View.
Symbol description：
20 patterned mask layers
30 patterned mask layers
40 patterned mask layers
100 semiconductor devices
110 substrates
112 body regions
114 drift regions
130 shallow trench isolations
150 source areas
160 drain regions
170 gate dielectrics
180 gate electrodes
200 semiconductor devices
210 substrates
212 body regions
214 drift regions
230,230a, 230b isolation structure
232 grooves
240 dielectric layers
241 gate dielectrics
241a side walls
250 linings
260 gate electrodes
260a ladders
262 recess portions
270 source areas
280 drain regions
300 ' semiconductor devices
300 doping steps
310 substrates
312 body regions
314a, 314b drift extension area pair
330,330a, 330b isolation structure
332 grooves
340 dielectric layers
341 gate dielectrics
341a side walls
350 linings
360 gate electrodes
360a ladders
362 recess portions
370 source areas
380 drain regions
400 doping steps
500 etch steps
P spacing
Specific implementation mode
For the features and advantages of the present invention can be clearer and more comprehensible, it is cited below particularly go out preferred embodiment, and coordinate institute's attached drawing
Formula is described in detail below.
It elaborates below for the semiconductor device of the present invention.It is to be understood that narration below provides many not
Same embodiment or example, to implement the different patterns of the present invention.Specific element and arrangement mode as described below are to the greatest extent letter
Single description present invention.Certainly, these are only illustrating and the restriction of non-present invention.In addition, may use in different embodiments
The label or mark repeated.These repeat, only for simply clearly narration is of the invention, not representing the different embodiments discussed
And/or there is any relevance between structure.Furthermore when address a first material layer be located in a second material layer or on
When, including situation that first material layer and second material layer are in direct contact.Alternatively, being also separated with one or more other materials between possibility
The situation of layer may be not directly contacted between first material layer and second material layer in this case.
Referring to Fig. 1, which is the sectional view of existing semiconductor device 100.This semiconductor device 100 includes body region 112
And drift region 114 is formed in substrate 110.Substrate 110 further includes multiple shallow trench isolations (Shallow trench
Isolation it) 130 is formed in wherein.In conventional semiconductor device 100, shallow trench isolation 130 is filling for example, silica
The groove of dielectric material.Other general elements are also incorporated herein in semiconductor device 100, such as source area 150, drain region
160, gate dielectric 170 and gate electrode 180.It is noted that conducting resistance (On-resistance, Ron) direct direct ratio
In the spacing P of this semiconductor device.
The present invention is by above-mentioned spacing is shortened in the case where not damaging breakdown voltage, to provide with the electric conduction reduced
The semiconductor device of the improvement of resistance.
Fig. 2A -2J be the embodiment of the present invention semiconductor device in its manufacturing process the sectional view in each stage or on regard
Figure, wherein Fig. 2A -2C show to form the body region and drift region of semiconductor device 200.Referring to Fig. 2A, provide with the first conduction
The substrate 210 of type.Substrate 210 can based on silicon base, silicon-on-insulator substrate or other similar substrates.In some realities
It applies in example, the first conductive type of substrate 210 can be p-type, such as substrate 210 can be boron doped substrate.In other embodiments,
The first conductive type of substrate 210 can be N-type, such as substrate 210 can be the substrate of phosphorus or arsenic doping.Substrate 210 also can be other
Any suitable substrate, such as compound semiconductor substrate, multi-layer substrate or other similar substrates.
Referring to Fig. 2 B, multiple isolation structures 230,230a and 230b are formed.In one embodiment, isolation structure 230,230a
And 230b can be shallow trench isolation.The technique for being conventionally formed shallow trench isolation can be used to be formed for shallow trench isolation 230, herein no longer
This technique is described in detail.This technique may include：It (is, for example, silica (SiO to sequentially form the first insulating layerx)) and the second insulation
Layer (is, for example, silicon nitride (SiNx)) in substrate 210.Then, this first and second insulating layer of selective etch and substrate 210
To form a groove in substrate 210.Lining of the growth one rich in nitrogen (is, for example, silicon oxynitride (SixOyNz)) in this groove
On surface or side wall, then, to be, for example, deposition step deposition gap filling material (such as the silica of chemical vapor deposition
Or boron-phosphorosilicate glass) on the surface of substrate 210, wherein this gap packing material inserts this groove.Then this gap is filled
Material carries out annealing steps, and by the conventional method of for example, chemical mechanical grinding that the planarization of substrate 210 is extra to remove
Gap filling material, make the upper surface flush of the gap filling material part and substrate in groove.It should be noted that above-mentioned work
Skill is only used for for example, the present invention should not be as limit.
Referring to Fig. 2 C, after isolation structure 230,230a and 230b, patterned mask layer 20 is formed in substrate 210.
This patterned mask layer 20 exposes scheduled drift region.This patterned mask layer 20 can be photoresist layer or hard mask layer, this is hard
Mask layer can be silicon nitride, silicon oxynitride or other similar materials.Step 300 is doped there will be the second conductive type
Admixture selective doping enters semiconductor base 210 to define drift region 214.This second conductive type is different from the first conductive type.In
After drift region 214 is formed, patterned mask layer 20 is removed.
With reference to Fig. 2 D, after drift region 214 is formed, patterned mask layer 30 is formed in substrate 210 and exposing scheduled
Body region.This patterned mask layer 30 can be photoresist layer or hard mask layer, this hard mask layer can be silicon nitride, silicon oxynitride or
Other similar materials.After the formation of patterned mask layer 30, step 400 is doped there will be the admixture of the first conductive type
Selective doping enters semiconductor base 210 to define body region 212.In some embodiments, the doping concentration of substrate 210 is higher than
The doping concentration of body region 212.For example, when body region 212 is p-type, substrate 210 can be heavily doped P-type (P+).In body region
After 212 form, patterned mask layer 30 is removed.
After body region 212 and drift region 214 are formed, dielectric layer 240 is formed in substrate 210, as shown in Figure 2 E.Dielectric
Layer 240 may include silica, silicon nitride, silicon oxynitride, high K dielectric matter (High-k dielectric), Qi Tashi
Cooperation is the dielectric material or combinations of the above of gate dielectric.High K dielectric matter may include metal oxide, such as
The oxidation of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu
Object or above-mentioned mixture.This dielectric layer 240 can be formed by the usual step of this field, such as atomic layer deposition, chemical gaseous phase
Deposition, physical vapour deposition (PVD), thermal oxidation method, ultraviolet-ozone oxidizing process (UV-Ozone oxidation) or above-mentioned group
It closes.The thickness of this dielectric layer 240 can be about 2000 angstroms to about 10000 angstroms.
With reference to Fig. 2 F, step 500 is performed etching using patterned mask layer 40 as mask with remove isolation structure 230 in
Groove 232 is formed between body region 212 and drift region 214, this etching step 500 also removes part of dielectric layer 240 to form neighbour
The gate dielectric 241 of nearly groove 232.This gate dielectric 241 at least can have inclined side wall 241a on one side.It should be appreciated that
Although Fig. 2 F show that inclined side wall, side wall 241a can be vertical side wall or other any suitable shapes.Etching step
Rapid 500 can be dry etching, wet etching or other similar etch steps.This patterned mask layer 40 can be photoresist layer or cover firmly
Film layer, this hard mask layer can be silicon nitride, silicon oxynitride or other similar materials.After etch step 500, patterning is removed
Mask layer 40.
With reference to Fig. 2 G, is formed in lining 250 and be lining in groove 232 and abutted with gate dielectric 241.Lining 250 can also cover
The upper surface for the substrate that lid gate dielectric 241 exposes.In one embodiment, lining 250 can be by oxidation step by substrate 210
It aoxidizes and is formed, such as can be by thermal oxidation method, ultraviolet-ozone oxidizing process or other similar steps.In another embodiment
In, lining 250 can be formed by deposition step, such as chemical vapor deposition, physical vapour deposition (PVD) or other similar steps.This
Lining 250 is thin than gate dielectric 241.In some embodiments, the thickness of lining 250 can be about 100-500 angstroms.
With reference to Fig. 2 H, gate electrode 260 is formed on gate dielectric 241 and part lining 250.This gate electrode 260
Extend at least partially into groove 232.The material of this gate electrode 260 may include metal, polysilicon, tungsten silicide (WSi2) or on
The combination stated.Formed gate electrode 260 method can be low-pressure chemical vapor deposition, plasma auxiliary chemical vapor deposition,
Other any suitable steps or combinations of the above.Gate electrode 260 can have ladder 260a, this ladder 260a is by grid
Caused by the difference in height of dielectric layer 241 and lining 250.In one embodiment, gate electrode 260 can compliance be formed in groove
In, therefore gate electrode 260 can be with the recess portion 262 of respective grooves 232.In another embodiment, gate electrode 260 can be complete
It fills up groove 232 and can have flat upper surface, as shown in figure 2i.
With reference to Fig. 2 J, source area 270 is formed in body region 212, and forms drain region 280 in drift region 214.Source electrode
Area 270 and drain region 280 can be formed by doping step commonly used in the art, such as ion implanting step.
Can be formed the element of the conventional semiconductor device of for example, interlayer dielectric layer or source/drain electrodes (not shown) with
Complete semiconductor device 200.The forming method of this element is the existing step of this field, therefore does not describe herein.
Semiconductor device 200 provided by the invention has the gate electrode 260 being formed in groove 232.The half of the present invention
Conductor device at least has the following advantages that compared to conventional semiconductor device.First, extend into the gate electrode of groove 232
260 provide shorter electric current spacing P (as shown in fig. 2j), and semiconductor device 200 is made to have lower conducting resistance (Ron).The
Two, due to the design of gate electrode 260, breakdown voltage can be maintained while reducing the conducting resistance of semiconductor device 200
It is horizontal.
It is to be understood that although the semiconductor device 200 being painted in schema on gate electrode only have a groove,
According to the design needs, as long as this semiconductor device can provide shorter spacing, there can be more than one groove on gate electrode.
Fig. 3 A-3J be the embodiment of the present invention semiconductor device 300 ' in its manufacturing method the sectional view in each stage or on
View, wherein Fig. 3 A-3C show to form the body region of semiconductor device 300 and drift extension area pair.Referring to Fig. 3 A, providing has
The substrate 310 of the first conductive type.Substrate 310 can based on silicon base, silicon-on-insulator substrate or other similar substrates.
In some embodiments, the first conductive type of substrate 310 can be p-type, such as substrate 310 can be boron doped substrate.Other
In embodiment, the first conductive type of substrate 310 can be N-type, such as substrate 310 can be the substrate of phosphorus or arsenic doping.Substrate 310 is also
Can be other any suitable substrates, such as compound semiconductor substrate or multi-layer substrate.
Referring to Fig. 3 B, multiple isolation structures 330,330a and 330b are formed.In one embodiment, isolation structure 330,330a
And 330b can be shallow trench isolation.The technique for being conventionally formed shallow trench isolation can be used to be formed for shallow trench isolation 330, herein no longer
This technique is described in detail.This technique may include：It (is, for example, silica (SiO to sequentially form the first insulating layerx)) and the second insulation
Layer (is, for example, silicon nitride (SiNx)) in substrate 310.Then, this first and second insulating layer of selective etch and substrate 310
To form a groove in substrate 310.Lining of the growth one rich in nitrogen (is, for example, silicon oxynitride (SixOyNz)) in this groove
On surface or side wall, then, to be, for example, deposition step deposition gap filling material (such as the silica of chemical vapor deposition
Or boron-phosphorosilicate glass) on the surface of substrate 310, wherein this gap packing material inserts this groove.Then this gap is filled
Material carries out annealing steps, and by the conventional method of for example, chemical mechanical grinding that the planarization of substrate 310 is extra to remove
Gap filling material, make the upper surface flush of the gap filling material part and substrate in groove.It should be noted that above-mentioned work
Skill is only used for for example, the present invention should not be as limit.
Referring to Fig. 3 C, patterned mask layer 20 is formed in substrate 310.This patterned mask layer 20 exposes scheduled extension
Area.This patterned mask layer 20 can be photoresist layer or hard mask layer, this hard mask layer can be silicon nitride, silicon oxynitride or other
Similar material.Be doped step 300 with will have the admixture selective doping of the second conductive type enter semiconductor base 310 with
Definition drift extension area is to 314a and 314b.This second conductive type is different from the first conductive type.In drift extension area to 314a and
After 314b is formed, patterned mask layer 20 is removed.Portions of isolation structure 330 may extend into drift extension area 314b.
Step 400 is doped will have first to lead after drift extension area forms 314a and 314b with reference to Fig. 3 D
The admixture (selectivity) of electric type is doped into the fate of semiconductor base 310 to define body region 312.In some embodiments,
The doping concentration of substrate 310 is higher than the doping concentration of body region 312.For example, when body region 312 is p-type, substrate 310 can be
Heavily doped P-type (P+).
After step shown in Fig. 3 D, dielectric layer 340 is formed in substrate 310, as shown in Figure 2 E.Dielectric layer 340 can wrap
It includes silica, silicon nitride, silicon oxynitride, high K dielectric matter (high-k dielectric), other be suitable as grid
The dielectric material or combinations of the above of dielectric layer.High K dielectric matter may include metal oxide, for example, Li, Be, Mg,
The oxide of Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu are above-mentioned
Mixture.This dielectric layer 340 can be formed by the usual step of this field, such as atomic layer deposition, chemical vapor deposition, physics gas
Mutually deposition, thermal oxidation method, ultraviolet-ozone oxidizing process (UV-Ozone oxidation) or combinations of the above.This dielectric layer
340 thickness can be about 3000 angstroms to about 10000 angstroms.
With reference to Fig. 3 F, step 500 is performed etching using patterned mask layer 40 as mask to remove isolation structure 330 with shape
At groove 332, this etching step 500 also removes part of dielectric layer 340 to form the gate dielectric 341 of adjacent trenches 332.This
Gate dielectric 341 at least can have inclined sidewall 34 1a on one side.It is to be understood that although Fig. 2 F show inclined side
Wall, sidewall 34 1a can be vertical side wall or other any suitable shapes.Etch step 500 can be dry etching, wet etching or
Other similar etch steps.This patterned mask layer 40 can be photoresist layer or hard mask layer, this hard mask layer can be nitridation
Silicon, silicon oxynitride or other similar materials.After etch step 500, patterned mask layer 40 is removed.
With reference to Fig. 3 G, is formed in lining 350 and be lining in groove 332 and abutted with gate dielectric 341.Lining 350 can also cover
The upper surface for the substrate that lid gate dielectric 341 exposes.In one embodiment, lining 350 can be by oxidation step by substrate 310
It aoxidizes and is formed, such as can be by thermal oxidation method, ultraviolet-ozone oxidizing process or other similar steps.In another embodiment
In, lining 350 can be formed by deposition step, such as chemical vapor deposition, physical vapour deposition (PVD) or other similar steps.This
Lining 350 is thin than gate dielectric 341.In some embodiments, the thickness of lining 350 can be about 100-500 angstroms.
With reference to Fig. 3 H, gate electrode 360 is formed on gate dielectric 341 and part lining 350.This gate electrode 360
Extend at least partially into groove 332.The material of this gate electrode 360 may include metal, polysilicon, tungsten silicide (WSi2) or on
The combination stated.Formed gate electrode 360 method can be low-pressure chemical vapor deposition, plasma auxiliary chemical vapor deposition,
Other any suitable steps or combinations of the above.Gate electrode 360 can have ladder 360a, this ladder 360a is by grid
Caused by the difference in height of dielectric layer 341 and lining 350.In one embodiment, gate electrode 360 can compliance be formed in groove
In, therefore gate electrode 360 can be with the recess portion 362 of respective grooves 332.In another embodiment, gate electrode 360 can be complete
It fills up groove 332 and can have flat upper surface, as shown in fig. 31.
With reference to Fig. 3 J, source area 370 is formed in the extension area 314b that drifts about, and forms drain region 380 in drift extension area
In 314a.Source area 370 and drain region 380 can be formed by doping step commonly used in the art, such as ion implanting step
Suddenly.
Can be formed the element of the conventional semiconductor device of for example, interlayer dielectric layer or source/drain electrodes (not shown) with
Complete semiconductor device 300.The forming method of this element is the existing step of this field, therefore does not describe herein.
Double-diffusion semiconductor device 300 provided by the invention has the gate electrode 360 being formed in groove 332.Extend
The gate electrode 360 for entering groove provides shorter electric current spacing P, make semiconductor device have lower conducting resistance (Ron) and
The breakdown voltage numerical value of semiconductor device can be maintained simultaneously.
It is to be understood that although the semiconductor device being painted in schema on gate electrode only have a groove, root
It is needed according to design, as long as this semiconductor device can provide shorter spacing, can have more than one groove on gate electrode.
It is to be understood that although the embodiment of the present invention only discloses specific semiconductor device, the extension of the present invention
The gate electrode for entering isolation structure is equally applicable for other semiconductor devices, such as metal oxide semiconductcor field effect transistor
(MOSFET), enhance vague and general type metal oxide semiconductor (Enhancement depletion metal-oxide
Semiconductor, EDMOS) etc..
Although the embodiment of the present invention and its advantage are disclosed above, it will be appreciated that any technical field
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when can change, substitute with retouching.In addition, this hair
Bright protection domain be not necessarily limited by technique in specification in the specific embodiment, machine, manufacture, material composition, device,
Method and step, any those of ordinary skill in the art can understand existing or future from disclosure of the present invention
Technique, machine, manufacture, material composition, device, method and the step developed, as long as can be here in the embodiment
Implement more or less the same function or the more or less the same result of acquisition all can be used according to the invention.Therefore, protection scope of the present invention packet
Include above-mentioned technique, machine, manufacture, material composition, device, method and step.In addition, each claim constitutes other implementation
Example, and protection scope of the present invention also includes the combination of each claim and embodiment.
Claims (24)
1. a kind of semiconductor device, which is characterized in that the semiconductor device includes：
One substrate has a first conductive type, and includes：
One body region has the first conductive type；
Source region is formed in the body region；
One drift region has a second conductive type and the neighbouring body region, the wherein the first conductive type and the second conductive type is not
Together；And
One drain region is formed in the drift region；
One groove is formed in the substrate between the body region and the drift region；
One gate dielectric, the neighbouring groove, the bottom surface of the gate dielectric are located on the upper surface of the substrate；
One lining is inside lining in the groove and is abutted with the gate dielectric；And
One gate electrode is formed on the gate dielectric, and extends into the groove, and wherein the gate electrode has because of the grid
A ladder caused by difference in height between dielectric layer and the lining.
2. semiconductor device as described in claim 1, which is characterized in that the lining is thinner than the gate dielectric.
3. semiconductor device as claimed in claim 2, which is characterized in that the thickness of the lining is 100-500 angstroms.
4. semiconductor device as claimed in claim 2, which is characterized in that the thickness of the gate dielectric is 2000-10000
Angstrom.
5. semiconductor device as described in claim 1, which is characterized in that the gate electrode is depressed at the groove.
6. semiconductor device as described in claim 1, which is characterized in that the gate electrode is fully filled with the groove, and is formed
One flat upper surfaces are at the groove.
7. semiconductor device as described in claim 1, which is characterized in that the gate electrode includes metal, polysilicon, metallic silicon
Compound or combinations of the above.
8. a kind of semiconductor device, which is characterized in that the semiconductor device includes：
One substrate has a first conductive type, and has a body region；
One drift extension area pair, has a second conductive type, and extend in the body region from a upper surface of the body region,
In the first conductive type it is different from the second conductive type；
Source region, is formed among the one of the drift extension area pair and a drain region, is formed in the drift extension area pair
Among another；
One groove is formed in above-mentioned drift extension area among one of them, and extends between the drift extension area pair
Body region part；
One gate dielectric, the neighbouring groove, the bottom surface of the gate dielectric are located on the upper surface of the substrate；
One lining is inside lining in the groove and is abutted with the gate dielectric；And
One gate electrode is formed on the gate dielectric, and extends into the groove, and wherein the gate electrode has because of the grid
A ladder caused by difference in height between dielectric layer and the lining.
9. semiconductor device as claimed in claim 8, which is characterized in that the lining is thinner than the gate dielectric.
10. semiconductor device as claimed in claim 9, which is characterized in that the thickness of the lining is 100-500 angstroms.
11. semiconductor device as claimed in claim 9, which is characterized in that the thickness of the gate dielectric is 2000-10000
Angstrom.
12. semiconductor device as claimed in claim 8, which is characterized in that the gate electrode is depressed at the groove.
13. semiconductor device as claimed in claim 8, which is characterized in that the gate electrode is fully filled with the groove, and is formed
One flat upper surfaces are at the groove.
14. semiconductor device as claimed in claim 8, which is characterized in that the gate electrode includes metal, polysilicon, metal
Silicide or combinations of the above.
15. a kind of manufacturing method of semiconductor device, which is characterized in that the manufacturing method includes：
One substrate is provided, there is a first conductive type；
A body region is formed in the substrate, and the body region has the first conductive type；
A drift region is formed in the substrate, which has a second conductive type and the neighbouring body region, wherein this first
Conductivity type is different from the second conductive type；
It is formed in the substrate of a shallow trench isolation between the body region and the drift region；
A dielectric layer is formed in the substrate；
Remove the shallow trench isolation and part the dielectric layer be respectively formed a groove and one adjacent to the groove gate dielectric,
Wherein the bottom surface of the gate dielectric is located on the upper surface of the substrate；
It is formed in a lining and is lining in the groove and is abutted with the gate dielectric；
A gate electrode is formed on the gate dielectric and extending into the groove, wherein the gate electrode has because the grid is situated between
A ladder caused by difference in height between electric layer and the lining；And
Source region is in the body region and a drain region is in the drift region for formation.
16. the manufacturing method of semiconductor device as claimed in claim 15, which is characterized in that the lining is than the gate dielectric
It is thin.
17. the manufacturing method of semiconductor device as claimed in claim 15, which is characterized in that the gate electrode is depressed in the ditch
At slot.
18. the manufacturing method of semiconductor device as claimed in claim 15, which is characterized in that the gate electrode is fully filled with this
Groove, and a flat upper surfaces are formed at the groove.
19. the manufacturing method of semiconductor device as claimed in claim 15, which is characterized in that the gate electrode include metal,
Polysilicon, metal silicide or combinations of the above.
20. a kind of manufacturing method of semiconductor device, which is characterized in that the manufacturing method includes：
One substrate is provided, there is a first conductive type；
A body region is formed in the substrate, and the body region has the first conductive type；
A drift extension area is formed in the body region, the drift extension area to having a second conductive type, wherein this first
Conductivity type is different from the second conductive type；
Formed a shallow trench isolation in above-mentioned drift extension area to one of among, wherein the shallow trench isolation extends into position
Body region part between the drift extension area pair；
A dielectric layer is formed in the substrate；
Remove the shallow trench isolation and part the dielectric layer be respectively formed a groove and one adjacent to the groove gate dielectric,
Wherein the bottom surface of the gate dielectric is located on the upper surface of the substrate；
It is formed in a lining and is lining in the groove and is abutted with the gate dielectric；
A gate electrode is formed on the gate dielectric and extending into the groove, wherein the gate electrode has because the grid is situated between
A ladder caused by difference in height between electric layer and the lining；And
Formed source region among the one of the drift extension area pair and a drain region in the drift extension area pair it is another it
In.
21. the manufacturing method of semiconductor device as claimed in claim 20, which is characterized in that the lining is than the gate dielectric
It is thin.
22. the manufacturing method of semiconductor device as claimed in claim 20, which is characterized in that the gate electrode is depressed in the ditch
At slot.
23. the manufacturing method of semiconductor device as claimed in claim 20, which is characterized in that the gate electrode is fully filled with this
Groove, and a flat upper surfaces are formed at the groove.
24. the manufacturing method of semiconductor device as claimed in claim 20, which is characterized in that the gate electrode include metal,
Polysilicon, metal silicide or combinations of the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410128143.0A CN104979381B (en) | 2014-04-01 | 2014-04-01 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410128143.0A CN104979381B (en) | 2014-04-01 | 2014-04-01 | Semiconductor device and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104979381A CN104979381A (en) | 2015-10-14 |
| CN104979381B true CN104979381B (en) | 2018-07-13 |
Family
ID=54275721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410128143.0A Active CN104979381B (en) | 2014-04-01 | 2014-04-01 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104979381B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113838906B (en) * | 2020-06-23 | 2024-01-09 | 芯恩（青岛）集成电路有限公司 | LDMOS transistor and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1797786A (en) * | 2004-11-29 | 2006-07-05 | 台湾积体电路制造股份有限公司 | Semiconductor element and method for producing the same |
| CN101752365A (en) * | 2008-12-04 | 2010-06-23 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4590884B2 (en) * | 2003-06-13 | 2010-12-01 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| JP2009302450A (en) * | 2008-06-17 | 2009-12-24 | Sharp Corp | Semiconductor device and its manufacturing method |
| KR20110079021A (en) * | 2009-12-31 | 2011-07-07 | 주식회사 동부하이텍 | Semiconductor device method for manufacturing the same |
-
2014
- 2014-04-01 CN CN201410128143.0A patent/CN104979381B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1797786A (en) * | 2004-11-29 | 2006-07-05 | 台湾积体电路制造股份有限公司 | Semiconductor element and method for producing the same |
| CN101752365A (en) * | 2008-12-04 | 2010-06-23 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104979381A (en) | 2015-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6106310B2 (en) | Hybrid active field gap extended drain MOS transistor | |
| TWI495106B (en) | Fin field effect transistors and methods for fabricating the same | |
| US9076816B2 (en) | Method and device for self-aligned contact on a non-recessed metal gate | |
| US9012988B2 (en) | Semiconductor device with a step gate dielectric structure | |
| US10217640B2 (en) | Methods of fabricating semiconductor devices | |
| CN107516668B (en) | Semiconductor device and method for manufacturing the same | |
| JP2006344836A (en) | Semiconductor apparatus and manufacturing method thereof | |
| TW201338053A (en) | Semiconductor structure and method for fabricating the same | |
| US11799014B2 (en) | Gate structure and methods thereof | |
| US11996481B2 (en) | Liner for a bi-layer gate helmet and the fabrication thereof | |
| KR102090772B1 (en) | Gate structure and methods thereof | |
| KR20200036716A (en) | Semiconductor structure with staggered selective growth | |
| JP5275056B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| US9299616B1 (en) | Integrated circuits with separate workfunction material layers and methods for fabricating the same | |
| US9130033B2 (en) | Semiconductor device and method for fabricating the same | |
| TW201535734A (en) | Semiconductor device and method of manufacturing the same | |
| CN104979381B (en) | Semiconductor device and its manufacturing method | |
| JP2010123660A (en) | Insulated gate-type semiconductor device, and manufacturing method thereof | |
| CN103578953B (en) | The method that semiconductor integrated circuit manufactures | |
| JP2011054872A (en) | Semiconductor device and method of manufacturing the same | |
| CN113097301B (en) | Semiconductor structure and forming method thereof | |
| TWI517263B (en) | Semiconductor device and method for forming the same | |
| JP5830111B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN106033731A (en) | Semiconductor element and manufacture method for the same | |
| TWI549299B (en) | Semiconductor device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |