JP2011054872A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that strikes a balance between control of a work function and thinned EOT, the device using a metal electrode/High-k film structure as a gate structure. <P>SOLUTION: On an area where an n-channel MIS transistor is formed in a semiconductor substrate 101, there are sequentially formed a first high-dielectric constant insulating film 202, an aluminum-containing film 203, a lantern-containing film 204, and a second high-dielectric constant insulating film 205. After that, a gate electrode is formed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The technology disclosed in this specification relates to a semiconductor device, and more particularly, to a semiconductor device having a high dielectric constant gate insulating film and a manufacturing method thereof.

As MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) increase in speed, miniaturization of transistors is progressing for scaling of a constant electric field. MOSFETs include an n-channel MOSFET (hereinafter abbreviated as “NMOS”) that controls current on / off by electron movement, and a p-channel that controls current on / off by hole movement. There are two transistors of type MOSFET (hereinafter abbreviated as “PMOS”). The performance of the MOSFET can be expressed by the current driving capability Gm, and is proportional to the mobility μ, the gate width W, and the capacitance (gate capacitance) Cox of the capacitor composed of the gate electrode, the gate insulating film, and the silicon substrate. On the other hand, it is inversely proportional to the gate length L. Therefore, the speeding up of the MOSFET is reduced by reducing the thickness of the gate insulating film composed of silicon oxide film (SiO ₂ ) and silicon oxynitride film (SiON), and the length of the gate electrode composed of polysilicon. This is achieved by reducing the gate length.

  However, there are the following problems in realizing high performance of the MOSFET.

First, when the thickness of the gate insulating film is reduced to 2 nm or less, the tunnel leakage current directly increases and the insulation resistance when the gate voltage is applied significantly deteriorates, so the power consumption of the MOSFET increases, resulting in higher performance. In addition, it is difficult to achieve low power consumption. Therefore, the relationship that the gate capacitance Cox is proportional to the relative permittivity (ε) and inversely proportional to the thickness (d) of the gate insulating film (Cox = ε0 · ε · (S / d) (ε0: relative permittivity of vacuum) , S: gate area)), the relative dielectric constant of the gate insulating film material is higher than that of the conventional silicon oxide film (ε: 3.9) and silicon oxynitride film (ε: 3.9-7). By using a large high dielectric constant insulating film (High-k film), a tunnel leakage current is directly suppressed by increasing a physical film thickness while maintaining an effective gate capacitance. As candidates for the High-k film, a hafnium oxide film (HfO ₂ ), a zirconium oxide film (ZrO ₂ ), alumina (Al ₂ O ₃ ), silicates and aluminates thereof, rare earth oxides, and the like are attracting attention. Among these candidates, the HfO ₂ film and the HfSiO film have a relatively high relative dielectric constant, a band gap of 5 eV or more, and a high electron barrier height with respect to the silicon substrate. The most influential.

Next, when a conventional polysilicon electrode is used as the gate electrode, the influence of the depletion layer becomes obvious. Therefore, even if the gate insulating film is thinned, the polysilicon electrode has a depletion layer capacitance, so that EOT ( (Equivalent Oxide Thickness) Thinning cannot be performed efficiently. On the other hand, the work function of the polysilicon electrode was controllable by ion implantation of impurities such as boron and phosphorus and activation by heat treatment. Specifically, by implanting boron into polysilicon in a polysilicon electrode / SiO ₂ gate insulating film structure, the work function can be increased from 4.65 eV to 5.15 eV in a non-doped state, so that NMOS and Control of both threshold voltages of PMOS was possible. However, in the polysilicon electrode / High-k gate insulating film structure, the threshold voltage rises due to the lowering of the effective work function of the PMOS due to the influence of Fermi level pinning, and the low voltage operation becomes difficult. Therefore, as a gate electrode material, replacement of a polysilicon electrode with a metal electrode that can ignore the influence of the depletion layer and has little influence of Fermi level pinning is being attempted. As candidates for metal gate electrode materials, nitrides of titanium and tantalum have been studied in consideration of work function values and processing characteristics such as dry etching and wet etching.

When a metal gate electrode is used, the work function inherent to the metal contained in the metal gate electrode becomes dominant, so that it is difficult to control the work function by ion implantation. Therefore, in order to control each of the NMOS and PMOS to a desired threshold voltage, the metal electrode / High-k It has been studied to control the work function by inserting a cap layer such as La ₂ O ₃ , Al ₂ O ₃ and MgO at the gate insulating film interface. Thus, as a next-generation gate structure, a metal electrode / Cap layer / High-k film structure is dominant (see, for example, Patent Document 1).

JP 2007-324594 A

  As described above, a metal electrode / Cap layer / High-k film structure has become a promising next-generation gate structure. Currently, as a High-k film, an HfSiO film having very good thermal stability ( A TiN / HfSiON structure using a TiN film that can be easily gated as a metal electrode has been studied.

By the way, in order to realize a low voltage operation, an effective work function (eWF) at the band edge is required in both PMOS and NMOS. For example, in NMOS, eWF = about 4.2 eV or less, PMOS Then, it is desirable to achieve eWF = about 5.0 eV or more. Therefore, in order to control the effective work function, a metal electrode / Cap layer / High-k film structure has been studied. Specifically, in the PMOS, the effective work function is controlled by inserting an Al ₂ O ₃ film as a Cap layer at the metal electrode / High-k film interface. Further, in NMOS, a La ₂ O ₃ film is inserted as a Cap layer at the metal electrode / High-k film interface, or heat treatment is performed after the La ₂ O ₃ film is inserted into the High-k film. La atoms are diffused, thereby controlling the effective work function.

However, when an HfSiON film is used as the High-k film, the relative dielectric constant of the High-k film is relatively low, up to about 13, so that further EOT thinning is necessary to improve the transistor performance. Yes. Therefore, as a high-k gate insulating film, an HfO ₂ film having a high relative dielectric constant of up to about 25 is being considered instead of the HfSiO film.

However, when the HfO ₂ film is used, the effect of the Fermi level pinning and the fixed charge of the HfO ₂ film is larger than that of the HfSiO film, so that the effective work function is more difficult to control as compared with the HfSiO film. Specifically, in the conventional technique in which an Al ₂ O ₃ film is deposited as a Cap layer on an HfO ₂ film as a gate structure for PMOS, eWF is saturated at about 4.8 eV, and the eWF is further improved. It is difficult. On the other hand, in the conventional technique in which heat treatment is performed after inserting a La ₂ O ₃ film at the metal electrode / High-k film interface as a gate structure for NMOS, it is difficult for La atoms to diffuse in the HfO ₂ film. It is difficult to make eWF smaller than about 4.3 eV by the heat treatment of technology (about 600 ° C.). In addition, NMOS has a problem that channel mobility deteriorates when La atoms diffuse to the interface between the gate insulating film and the silicon substrate.

In addition, when an HfO ₂ film is used, oxygen atoms easily permeate through the gate insulating film, so that the HfO ₂ film / silicon substrate interface is formed by heat treatment in the film deposition process and diffusion process (impurity activation annealing process). For example, a low dielectric constant layer such as a SiO ₂ film is formed, making it difficult to reduce the EOT film thickness.

  In view of the above, an object of the present invention is to achieve both work function control and EOT thinning in a semiconductor device using a metal electrode / high-k film structure as a gate structure.

  In order to achieve the above object, a semiconductor device according to the present invention includes an n-channel MIS transistor having a first gate electrode formed on a semiconductor substrate via a first gate insulating film, The gate insulating film includes a first high dielectric constant insulating film containing lanthanum and aluminum.

  According to the semiconductor device of the present invention, since the High-k gate insulating film of the n-channel MIS transistor contains lanthanum (La) and aluminum (Al), the La distribution and the Al distribution in the High-k gate insulating film are appropriately set. By controlling, it is possible to easily control the effective work function while suppressing an increase in EOT as compared with a conventional semiconductor device. In addition, since diffusion of La atoms having a large atomic radius to the semiconductor substrate side can be suppressed by Al atoms having a small atomic radius, deterioration in channel mobility can be suppressed. Therefore, it is possible to realize high functionality and low power consumption of the n-channel MIS transistor.

  In the semiconductor device according to the present invention, the peak position of the lanthanum concentration in the first high dielectric constant insulating film is closer to the first gate electrode than the peak position of the aluminum concentration in the first high dielectric constant insulating film. May be. In this way, the diffusion of La atoms having a large atomic radius to the semiconductor substrate side can be reliably suppressed by Al atoms having a small atomic radius, so that the deterioration of channel mobility can be further suppressed.

  In the semiconductor device according to the present invention, the first gate insulating film may have an interface layer formed between the first high dielectric constant insulating film and the semiconductor substrate.

  In the semiconductor device according to the present invention, the first high dielectric constant insulating film may include at least one of hafnium and zirconium.

  In the semiconductor device according to the present invention, the first high dielectric constant insulating film may contain magnesium instead of lanthanum.

  In the semiconductor device according to the present invention, the first high dielectric constant insulating film may contain yttrium instead of aluminum.

  In the semiconductor device according to the present invention, the first gate electrode may have a layer made of titanium nitride or tantalum nitride in contact with the first high dielectric constant insulating film. In this case, titanium or tantalum may diffuse into the first high dielectric constant insulating film.

  In the semiconductor device according to the present invention, at least a portion of the semiconductor substrate in contact with the first gate insulating film may be made of silicon, germanium, or silicon germanium. In this case, silicon or germanium may diffuse into the first high dielectric constant insulating film.

  The semiconductor device according to the present invention further includes a p-channel MIS transistor having a second gate electrode formed on the semiconductor substrate via a second gate insulating film, wherein the second gate insulating film is made of aluminum. A second high dielectric constant insulating film may be included. In this case, since the high-k gate insulating film of the p-channel MIS transistor contains aluminum (Al), the Al distribution in the high-k gate insulating film is appropriately controlled, so that it can be compared with the conventional semiconductor device. Thus, it is possible to easily control the effective work function while suppressing an increase in EOT. Therefore, it is possible to realize high functionality and low power consumption of the p-channel MIS transistor. The second high dielectric constant insulating film does not substantially contain lanthanum. The relative dielectric constant of the first gate insulating film may be larger than the relative dielectric constant of the second gate insulating film.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a step (a) of forming a first gate insulating film on an n-channel MIS transistor formation region in a semiconductor substrate; A step (b) of forming a first gate electrode, wherein the step (a) includes a first high dielectric constant insulating layer, an aluminum-containing layer, a lanthanum-containing layer, and a first gate insulating film. And a step of sequentially forming a high dielectric constant insulating layer.

According to the method for manufacturing a semiconductor device of the present invention, a first high dielectric constant insulating layer, an aluminum-containing layer, a lanthanum-containing layer, and a second high dielectric constant insulating layer are sequentially formed as a gate insulating film of an n-channel MIS transistor. To do. For this reason, by appropriately controlling the La distribution and the Al distribution in the gate insulating film, it is possible to easily control the effective work function while suppressing an increase in EOT as compared with the conventional semiconductor device. Specifically, since the lanthanum-containing layer is sandwiched between the high dielectric constant insulating layers from above and below, lanthanum (La) atoms are easily diffused in the high dielectric constant insulating layer, so that the effective work function can be easily controlled. In addition, since the second high dielectric constant insulating layer is formed above the aluminum-containing layer and the lanthanum-containing layer, oxygen atoms in the second high dielectric constant insulating layer are transmitted through the gate insulating film toward the substrate. Since this can be prevented, a situation in which a low dielectric constant layer such as a SiO ₂ film is formed at the gate insulating film / substrate interface can be avoided, thereby suppressing an increase in EOT. Furthermore, since the aluminum-containing layer is formed below the lanthanum-containing layer, diffusion of La atoms having a large atomic radius to the semiconductor substrate side can be suppressed by aluminum (Al) atoms having a small atomic radius. Therefore, deterioration of channel mobility can be suppressed. Therefore, it is possible to realize high functionality and low power consumption of the n-channel MIS transistor.

  Note that Al atoms and La atoms contained in the aluminum-containing layer and the lanthanum-containing layer respectively diffuse into the upper and lower high dielectric constant insulating layers by the subsequent heat treatment. As a result, in the final structure of the device, a gate insulating film (High-k The aluminum-containing layer and the lanthanum-containing layer do not remain in the gate insulating film. That is, as a gate insulating film of the n-channel MIS transistor, a high-k film having aluminum and lanthanum distribution is formed in the film.

In the method for manufacturing a semiconductor device according to the present invention, the step (a) includes a step of forming a second gate insulating film on the p-channel MIS transistor formation region in the semiconductor substrate, and the step (b) , Forming a second gate electrode on the second gate insulating film, wherein the step (a) includes forming the first high dielectric constant insulating layer as the second gate insulating film, A step of sequentially forming an aluminum-containing layer and the second high dielectric constant insulating layer may be included. Here, the lanthanum-containing layer is not formed. In this way, by appropriately controlling the Al distribution in the gate insulating film of the n-channel MIS transistor, it is possible to easily control the effective work function while suppressing an increase in EOT as compared with the conventional semiconductor device. be able to. Specifically, since the aluminum-containing layer is sandwiched between the high dielectric constant insulating layers from above and below, aluminum (Al) atoms are easily diffused in the high dielectric constant insulating layer, so that the effective work function can be easily controlled. In addition, since the second high dielectric constant insulating layer is formed on the upper side of the aluminum-containing layer, oxygen atoms in the second high dielectric constant insulating layer can be prevented from passing through the gate insulating film in the substrate direction. Therefore, it is possible to avoid a situation in which a low dielectric constant layer such as a SiO ₂ film is formed at the gate insulating film / substrate interface, thereby suppressing an increase in EOT. Therefore, it is possible to realize high functionality and low power consumption of the p-channel MIS transistor.

  Al atoms contained in the aluminum-containing layer diffuse into the upper and lower high dielectric constant insulating layers in the subsequent heat treatment, and as a result, in the final structure of the device, the gate insulating film (High-k gate insulating film) contains aluminum. There is no layer left. That is, as a gate insulating film of the p-channel MIS transistor, a high-k film having aluminum distribution is formed in the film.

  In the method for manufacturing a semiconductor device according to the present invention, the step (a) may include a step of forming an interface layer on the semiconductor substrate before forming the first high dielectric constant insulating layer. .

  In the method for manufacturing a semiconductor device according to the present invention, the step (a) may include a step of performing a heat treatment at a temperature of 600 ° C. or higher and 700 ° C. or lower after forming the lanthanum-containing layer. In this case, La atoms are more easily diffused in the high dielectric constant insulating layer, so that the effective work function can be more easily controlled.

  In the method of manufacturing a semiconductor device according to the present invention, in the step (a), the second high dielectric constant insulating layer may be formed before the lanthanum-containing layer. In this case, when the step (a) includes a step of performing a heat treatment at a temperature of 700 ° C. or more and 1000 ° C. or less after forming the lanthanum-containing layer, La atoms diffuse more in the high dielectric constant insulating layer. This makes it easier to control the effective work function.

In the method for manufacturing a semiconductor device according to the present invention, the first high dielectric constant insulating layer and the second high dielectric constant insulating layer include a first gas containing hafnium and a first oxidizing agent containing oxygen. May be formed. In this case, the first gas, TDMAHf (tetradimethylaminotitanium hafnium), HfCl ₄ (hafnium tetrachloride), TEMAHf (tetrakis ethylmethylamino hafnium) and Hf (MMP) ₄ (tetrakis (l-methoxy-2-methyl -2-propoxy) hafnium) containing at least one substance selected from the group consisting of H ₂ O, O ₂ and O _3. May be.

  According to the present invention, in a semiconductor device using a metal electrode / high-k film structure as a gate structure, it is possible to achieve both work function control and EOT thinning. Electricity can be realized.

FIG. 1 is a sectional view of a schematic configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing each step of a method for forming an NMOS gate structure in the semiconductor device according to the first embodiment of the present invention. FIGS. 3A to 3C are diagrams showing a cross-sectional configuration in the case where the formation position of the La-containing layer in the gate insulating film structure is changed. FIG. 4 is a diagram showing the results of examining the relationship between EOT and eWF for each of the gate insulating film structures shown in FIGS. FIGS. 5A and 5B are diagrams showing a cross-sectional configuration in the case where the formation position of the Al-containing layer in the gate insulating film structure is changed. FIG. 6 is a diagram showing the results of examining the relationship between EOT and eWF for each of the gate insulating film structures shown in FIGS. 5 (a) and 5 (b). 7A to 7F are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 8A to 8E are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIGS. 9A to 9F are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention. FIGS. 10A to 10E are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  1 is a cross-sectional view of a schematic configuration of a semiconductor device according to a first embodiment of the present invention, specifically, a semiconductor device including a complementary MOSFET (hereinafter abbreviated as “CMOS”) having an NMOS and a PMOS. FIG.

  As shown in FIG. 1, in the semiconductor device of the present embodiment, an n-type well region 102 and a p-type well region 103 are provided on a semiconductor substrate 101 made of, for example, silicon, germanium, silicon germanium, or the like. A PMOS 105 is provided on the type well region 102, and an NMOS 106 is provided on the p type well region 103. Each of the n-type well region 102 and the p-type well region 103 is surrounded by an element isolation layer 104 made of, for example, a silicon oxide film, so that the n-type well region 102 and the p-type well region 103 are mutually connected. Electrically separated. The element isolation layer 104 has, for example, an STI (Shallow Trench Isolation) structure.

  On the p-type well region 103 where the NMOS 106 is provided, a first metal electrode composed of a metal-containing layer such as a TiN film or a TaN film, for example, via a first gate insulating film 115 made of a High-k material. A film 116 is formed. In the present embodiment, the first gate insulating film 115 includes, for example, a hafnium oxide film (High-k film) containing lanthanum and aluminum. Here, an interface layer (which becomes a part of the first gate insulating film 115) may be formed between the high-k film and the semiconductor substrate 101. Further, the High-k film may include other High-k materials such as zirconium, for example, instead of or together with hafnium. The High-k film may contain magnesium instead of lanthanum. Further, the High-k film may contain yttrium instead of aluminum.

  As shown in FIG. 1, a first polysilicon electrode film 117 made of polysilicon containing an n-type impurity such as phosphorus or arsenic is formed on the first metal electrode film 116. That is, the gate electrode of the NMOS 106 is composed of the first metal electrode film 116 and the first polysilicon electrode film 117. Here, on the side surface of the gate electrode of the NMOS 106, a first sidewall spacer 118 made of, for example, a silicon oxide film or a silicon nitride film is formed.

  Further, an n-type extension layer 114 containing an n-type impurity is formed in the p-type well region 103 immediately below the first sidewall spacer 118. Further, in the region located on both sides of the first sidewall spacer 118 when viewed from the first metal electrode film 116 and the first polysilicon electrode film 117 in the p-type well region 103, the n-type extension layer 114. An n-type source / drain region 113 containing an n-type impurity at a higher concentration is formed in contact with the n-type extension layer 114.

  Although not shown, the surface portion of the n-type source / drain region 113 and the surface portion of the first polysilicon electrode film 117 are, for example, nickel silicide (NiSi) or nickel platinum silicide (NiPtSi). A silicide layer made of may be formed. The n-type source / drain region 113 and the n-type extension layer 114 may be provided in a carbon-doped Si epitaxial layer containing, for example, about 1 atomic% to 3 atomic% of carbon (C).

  On the other hand, as shown in FIG. 1, a metal-containing layer such as a TiN film or a TaN film is formed on the n-type well region 102 where the PMOS 105 is provided via a second gate insulating film 109 made of a high-k material. A second metal electrode film 110 composed of is formed. In the present embodiment, the second gate insulating film 109 has, for example, a hafnium oxide film (High-k film) containing aluminum. Here, the relative dielectric constant of the High-k film constituting the first gate insulating film 115 of the NMOS 106 may be larger than the relative dielectric constant of the High-k film. Further, an interface layer (which becomes a part of the second gate insulating film 109) may be formed between the high-k film and the semiconductor substrate 101. Further, the High-k film may include other High-k materials such as zirconium, for example, instead of or together with hafnium. Further, the High-k film may contain yttrium instead of aluminum.

  On the second metal electrode film 110, a second polysilicon electrode film 111 made of polysilicon containing a p-type impurity such as boron is formed. That is, the gate electrode of the PMOS 105 is composed of the second metal electrode film 110 and the second polysilicon electrode film 111. Here, a second sidewall spacer 112 made of, for example, a silicon oxide film or a silicon nitride film is formed on the side surface of the gate electrode of the PMOS 105.

  A p-type extension layer 108 containing a p-type impurity is formed in the n-type well region 102 immediately below the second sidewall spacer 112. Further, in the n-type well region 102, a region located on both sides of the second sidewall spacer 112 when viewed from the second metal electrode film 110 and the second polysilicon electrode film 111 is formed in the p-type extension layer 108. A p-type source / drain region 107 containing a higher concentration of p-type impurities is formed in contact with the p-type extension layer 108.

  Although not shown in the drawings, the surface portion of the p-type source / drain region 107 and the surface portion of the second polysilicon electrode film 111 are each made of nickel silicide (NiSi) or nickel platinum silicide (NiPtSi), for example. A silicide layer made of may be formed. The p-type source / drain region 107 and the p-type extension layer 108 may be provided with a SiGe epitaxial layer containing, for example, about 10 atomic% to 40 atomic% of germanium (Ge).

  Further, in the present embodiment, the semiconductor device including the CMOS having the NMOS and the PMOS is targeted, but instead, the semiconductor device including either the NMOS or the PMOS of the present embodiment is also targeted. Good. Further, an n-channel MIS (Metal Insulator Semiconductor) transistor having substantially the same gate structure may be used instead of the NMOS. Further, a p-channel MIS transistor having substantially the same gate structure may be used instead of the PMOS.

  Hereinafter, a method for forming the gate structure of the NMOS 106 in the semiconductor device of this embodiment shown in FIG. 1 will be described with reference to FIGS.

First, as shown in FIG. 2A, a silicon oxide film (for example, a film thickness of 1.5 nm or less (specifically, a film thickness of 0.9 nm) is formed on a semiconductor substrate 101 (p-type well region 103 of the NMOS 106). An interface layer 201 made of SiO ₂ ) or a silicon oxynitride film (SiON) is formed. At this time, it is preferable to form the interface layer 201 at a processing temperature of 700 ° C. to 1000 ° C. using a gas such as O ₂ , N ₂ O, or NO. In the case of forming the SiO ₂ film, in the SiO ₂ film, it may be a Si-H bonds in addition to the SiO bond. Further, when forming the SiON film, nitriding treatment is performed by nitrogen-containing plasma irradiation, and then high-temperature heat treatment is performed in an oxygen or nitrogen atmosphere in a temperature range of, for example, 800 ° C. to 1100 ° C. for film densification. Is desirable.

Next, as shown in FIG. 2B, a first HfO ₂ film 202 having a film thickness of, for example, about 2 nm or less is formed on the interface layer 201. As a method for forming the first HfO ₂ film 202, for example, atomic layer deposition (ALD) that enables HfO ₂ film formation at the atomic level by alternately supplying a gas containing Hf metal material and an oxidant alternately. : Atomic Layer Deposition) method may be used. At this time, as the Hf metal material containing gas, TDMAHf (tetradimethylaminotitanium hafnium), HfCl ₄ (hafnium tetrachloride), TEMAHf (tetrakis ethylmethylamino hafnium) and Hf (MMP) ₄ (tetrakis (1- methoxy-2 It is preferable to include at least one substance selected from -methyl-2-propoxy) hafnium). The oxidizing agent preferably contains at least one substance selected from water (H ₂ O), oxygen (O ₂ ) and ozone (O ₃ ).

Next, as shown in FIG. 2C, an Al-containing layer 203 made of, for example, Al oxide (AlOx) or aluminum (Al) and having a thickness of about 1 nm or less is formed on the first HfO ₂ film 202. . Subsequently, as shown in FIG. 2D, a La-containing layer 204 made of, for example, La oxide (LaOx) or lanthanum (La) and having a thickness of about 2 nm or less is formed on the Al-containing layer 203. In the present embodiment, after the formation of the La-containing layer 204, a step of diffusing La atoms in the La-containing layer 204 to the substrate side by heat treatment may be performed. In this case, the heat treatment temperature is preferably about 600 ° C to 1000 ° C. In addition, after diffusing La atoms by heat treatment, a process of removing the excess La-containing layer 204 may be performed by cleaning using, for example, a chemical solution mainly containing HCl.

Next, as shown in FIG. 2E, a _second HfO ₂ film 205 having a thickness of about 2 nm or less is formed on the La-containing layer 204, for example. As a method for forming the second HfO ₂ film 205, a method similar to the method for forming the first HfO ₂ film 202 may be used. After that, as shown in FIG. 2F, a first metal electrode film 116 made of a work function determining metal material, for example, TiN is formed on the second HfO ₂ film 205, and then the first metal is formed. A first polysilicon electrode film 117 containing an n-type impurity such as phosphorus or arsenic is formed on the electrode film 116. Here, as the material of the first metal electrode film 116, for example, TiAlN, TaN, TaC, or TaCN may be used in addition to TiN. Further, instead of the first polysilicon electrode film 117, another semiconductor film containing an n-type impurity may be formed.

A feature of the present embodiment is that a first HfO ₂ film 202, an Al-containing layer 203, a La-containing layer 204, and a second HfO ₂ film 205 are sequentially formed as a first gate insulating film 115 (see FIG. 1) of the NMOS 106. Is to form. That is, a structure in which the Al-containing layer 203 and the La-containing layer 204 are sandwiched between the first HfO ₂ film 202 and the second HfO ₂ film 205 is formed. For this reason, Al atoms and La atoms respectively contained in the Al-containing layer 203 and the La-containing layer 204 are diffused into the first HfO ₂ film 202 and the second HfO ₂ film 205 in the subsequent heat treatment. In the final structure, the Al-containing layer 203 and the La-containing layer 204 do not remain in the first gate insulating film 115 (more precisely, the High-k film portion excluding the interface layer 201). That is, as the first gate insulating film 115 of the NMOS 106, a hafnium-containing high-k film having aluminum and lanthanum distribution (concentration profile) is formed in the film. Here, when the La-containing layer 204 is formed on the Al-containing layer 203 as in this embodiment, the peak position of the lanthanum concentration in the first gate insulating film 115 (hafnium-containing High-k film) is It is closer to the gate electrode (first metal electrode film 116) than the peak position of the aluminum concentration.

According to the present embodiment, by appropriately controlling the La distribution and the Al distribution in the first gate insulating film 115 of the NMOS 106, the effective work function is suppressed while suppressing an increase in EOT as compared with the conventional semiconductor device. Control can be easily performed. Specifically, since the La-containing layer is sandwiched between the HfO ₂ films 202 and 205 from above and below, La atoms are easily diffused in the HfO ₂ films 202 and 205, so that the effective work function can be easily controlled. Further, since the second HfO ₂ film 205 is formed above the Al-containing layer 203 and the La-containing layer 204, oxygen atoms in the second HfO ₂ film 205 are transmitted through the gate insulating film in the substrate direction. Since this can be prevented, a situation in which a low dielectric constant layer such as a SiO ₂ film is formed at the gate insulating film / substrate interface can be avoided, thereby suppressing an increase in EOT. Furthermore, since the Al-containing layer 203 is formed below the La-containing layer 204, diffusion of La atoms having a large atomic radius to the substrate side can be suppressed by Al atoms having a small atomic radius. Mobility deterioration can be suppressed. Therefore, higher functionality and lower power consumption of the NMOS 106 can be realized.

In the present embodiment, instead of the first HfO ₂ film 202 and the second HfO ₂ film 205, another hafnium-containing insulating layer such as an HfSiO film or an HfSiON film may be formed.

As described above, the present embodiment easily controls the effective work function while suppressing the increase in EOT by adjusting the formation positions of the Al-containing layer and the La-containing layer in the HfO ₂ film. However, the effects of the present embodiment will be described in detail below in comparison with the comparative example.

  3A to 3C show cross-sectional configurations when the position where the La-containing layer is formed in the gate insulating film structure is changed.

First, the structure (first comparative example) shown in FIG. 3A is formed as follows. First, an interface layer 201 having a thickness of 1.5 nm or less (for example, a SiO ₂ film having a thickness of 0.9 nm) is formed on the semiconductor substrate 101, and then an HfO ₂ film 202 having a thickness of 4 nm or less is formed on the interface layer 201. (For example, an HfO ₂ film having a thickness of 2.0 nm) is formed. Thereafter, a La-containing layer 204 having a thickness of 2 nm or less (for example, a La ₂ O ₃ film having a thickness of 2.0 nm) is formed on the HfO ₂ film 202, and then a heat treatment at 600 ° C. to 700 ° C. is performed to form the La-containing layer. La atoms in 204 are diffused into the HfO ₂ film 202. After the diffusion of La atoms, the excessive La-containing layer 204 is removed by cleaning with a chemical solution containing HCl as a main component.

  Next, the structure shown in FIG. 3B (second comparative example) is basically the same structure as the structure shown in FIG. 3A (first comparative example). The method of forming the structure shown is different in that the heat treatment temperature after the formation of the La-containing layer 204 is a high temperature heat treatment at 700 ° C. to 1000 ° C., for example, a heat treatment at 800 ° C.

Next, the structure shown in FIG. 3C (corresponding to the gate insulating film structure of the NMOS 106 of this embodiment (however, for comparison with each comparative example, an Al-containing layer is not formed)) is as follows. Thus formed. First, an interface layer 201 having a thickness of 1.5 nm or less (for example, a SiO ₂ film having a thickness of 0.9 nm) is formed on the semiconductor substrate 101, and then a first HfO having a thickness of 2 nm or less is formed on the interface layer 201. _Two films 202 (for example, a 1.0 nm-thickness HfO ₂ film) are formed, and then a La-containing layer 204 (for example, a 0.5 nm-thickness film having a thickness of 0.5 nm) is formed on the first HfO ₂ film 202 (La ₂ O ₃ film) is formed, and then a second HfO ₂ film 205 (for example, a 1.0 nm-thick HfO ₂ film) having a thickness of 2 nm or less is formed on the La-containing layer 204.

FIG. 4 shows the equivalent silicon oxide film thickness (EOT) and effective work for each of the three gate insulating film structures in which the HfO ₂ film and the La-containing layer are stacked as shown in FIGS. It is a figure which shows the result of having investigated the relationship with a function (eWF). When the effective work function is controlled by the La-containing layer as the NMOS, it is desirable to lower the effective work function while suppressing an increase in EOT as compared with a structure without the La-containing layer. Here, EOT (silicon oxide film equivalent film thickness) is the film thickness of the insulating film obtained by calculating back from the gate capacitance, assuming that the material of the gate insulating film is silicon oxide.

As shown in FIG. 4, according to the structure shown in FIG. 3 (a), there is no increase in EOT compared to a structure without a La-containing layer (HfO ₂ / IL (without LaO) (where IL is an interface layer)). However, eWF is only low from about 4.6 eV to about 4.3 eV. That is, it can be seen that eWF modulation has a limit of 4.3 eV. On the other hand, according to the structure shown in FIG. 3B, although EOT is slightly increased, 4.0 eV can be achieved by eWF modulation. Further, according to the structure shown in FIG. 3C, 4.1 eV can be achieved by eWF modulation without an increase in EOT. From the above results, it was found that eWF can be efficiently controlled without an increase in EOT by using the structure shown in FIGS. 3B and 3C, in particular, the structure shown in FIG.

  FIGS. 5A and 5B show cross-sectional configurations in the case where the formation position of the Al-containing layer in the gate insulating film structure is changed.

First, the structure (third comparative example) shown in FIG. 5A is formed as follows. First, an interface layer 201 having a thickness of 1.5 nm or less (for example, a SiO ₂ film having a thickness of 0.9 nm) is formed on the semiconductor substrate 101, and then an HfO ₂ film 202 having a thickness of 4 nm or less is formed on the interface layer 201. (For example, an HfO ₂ film having a thickness of 2.0 nm) is formed, and then an Al-containing layer 203 having a thickness of 1 nm or less (for example, two types of Al having a thickness of 0.5 nm and 1.0 nm) is formed on the HfO ₂ film 202. ₂ O ₃ film).

Next, the structure shown in FIG. 5B (corresponding to the gate insulating film structure of the PMOS 105 of this embodiment) is formed as follows. First, an interface layer 201 having a thickness of 1.5 nm or less (for example, a SiO ₂ film having a thickness of 0.9 nm) is formed on the semiconductor substrate 101, and then a first HfO having a thickness of 2 nm or less is formed on the interface layer 201. _Two films 202 (for example, a 1.0 nm thick HfO ₂ film) are formed, and then an Al-containing layer 203 (for example, a 0.7 nm thick film thickness) having a film thickness of 1.0 nm or less is formed on the first HfO ₂ film 202. After forming the Al ₂ O ₃ film, a second HfO ₂ film 205 (for example, a 1.0 nm-thick HfO ₂ film) having a thickness of 2 nm or less is formed on the Al-containing layer 203.

FIG. 6 shows the results of examining the relationship between EOT and eWF for each of the two gate insulating film structures in which the HfO ₂ film and the Al-containing layer shown in FIGS. 5A and 5B are stacked. FIG. When controlling the effective work function with an Al-containing layer as a PMOS, it is desirable to increase the effective work function while suppressing an increase in EOT as compared with a structure without an Al-containing layer.

As shown in FIG. 6, according to the structure shown in FIG. 5A, eWF increases as the thickness of the Al-containing layer increases, but when the thickness of the Al-containing layer becomes about 1.0 nm, eWF = It can be seen that saturation tends to occur at about 4.8 eV (see the solid line in FIG. 6), where the ● on the left corresponds to the case where the film thickness of the Al-containing layer is 0.5 nm, and the ● on the right indicates the Al-containing layer. This corresponds to the case where the film thickness is about 1.0 nm). Further, as the thickness of the Al-containing layer is increased, EOT is remarkably increased as compared with a structure without an Al-containing layer (HfO ₂ / IL (without AlO) (IL is an interface layer)). In contrast, according to the structure shown in FIG. 5B in which an Al-containing layer is inserted in the middle of the HfO ₂ film, eWF = 4.85 eV or more can be achieved, and the increase in EOT is about 0.1 nm. Is suppressed. From the above results, it was found that the structure shown in FIG. 5B is optimal as a structure capable of obtaining a high eWF value while suppressing an increase in EOT.

  As described above, the gate insulating film structure capable of efficiently controlling the effective work function while suppressing the increase in EOT in both the NMOS and PMOS in the CMOS is shown in FIGS. 3B and 3C for the NMOS. Preferably, the structure shown in FIG. 3C is used, and the structure shown in FIG. 5B is preferably used for the PMOS. Further, in the NMOS gate insulating film structure, it is desirable to further insert an Al-containing layer in order to suppress diffusion of La atoms. In this case, the increase in EOT caused by the addition of Al is offset by the increase in dielectric constant due to the addition of La. Further, the increase in eWF due to Al addition can be suppressed by increasing the amount of La addition.

  A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings.

  FIGS. 7A to 7F and FIGS. 8A to 8E show a semiconductor device according to the first embodiment of the present invention, specifically, a semiconductor including a CMOS having an NMOS and a PMOS. It is sectional drawing which shows each process of the manufacturing method of an apparatus.

First, as shown in FIG. 7A, an element isolation layer 104 is formed on, for example, an STI method on a semiconductor substrate 101 made of, for example, silicon, thereby forming an active region (NMOS region) formed on the semiconductor substrate 101. A p-type well region 103) and an active region (n-type well region 102) formed in the semiconductor substrate 101 in the PMOS region are partitioned. Thereafter, on the semiconductor substrate 101 including the NMOS region and the PMOS region, for example, from a silicon oxide film (SiO ₂ ) or a silicon oxynitride film (SiON) having a film thickness of 1.5 nm or less (specifically, a film thickness of 0.9 nm). An interface layer 201 is formed. At this time, it is preferable to form the interface layer 201 at a processing temperature of 700 ° C. to 1000 ° C. using a gas such as O ₂ , N ₂ O, or NO. In addition, when forming a SiON film, it is desirable to perform nitriding treatment by nitrogen-containing plasma irradiation, and then perform high-temperature heat treatment in an oxygen or nitrogen atmosphere in a temperature range of, for example, 800 ° C. to 1100 ° C. for film densification. .

Next, as shown in FIG. 7B, a first HfO ₂ film 202 having a film thickness of about 2 nm or less is formed on the interface layer 201, for example. As a method for forming the first HfO ₂ film 202, for example, atomic layer deposition (ALD) that enables HfO ₂ film formation at the atomic level by alternately supplying a gas containing Hf metal material and an oxidant alternately. ) Method may be used. At this time, as the Hf metal material containing gas, TDMAHf (tetradimethylaminotitanium hafnium), HfCl ₄ (hafnium tetrachloride), TEMAHf (tetrakis ethylmethylamino hafnium) and Hf (MMP) ₄ (tetrakis (1- methoxy-2 It is preferable to include at least one substance selected from -methyl-2-propoxy) hafnium). The oxidizing agent preferably contains at least one substance selected from water (H ₂ O), oxygen (O ₂ ) and ozone (O ₃ ). Further, for example, nitrogen atoms may be added to the first HfO ₂ film 202 by a process using plasma made of a nitrogen-containing gas.

Next, as shown in FIG. 7C, an Al-containing layer 203 made of, for example, Al oxide (AlOx) or aluminum (Al) having a thickness of about 1 nm or less is formed on the first HfO ₂ film 202. .

Next, as shown in FIG. 7D, a hard mask film 301 made of, for example, a TiN film having a thickness of about 10 nm is formed on the Al-containing layer 203. Here, the hard mask film 301 may be formed by, for example, an ALD method using a TiCl ₄ gas and an NH ₃ gas or a PVD (Physical Vapor Deposition) method.

Next, although not shown, after applying a resist so as to cover the entire surface of the hard mask film 301, a resist pattern that covers only the PMOS region is formed by opening the resist in the NMOS region by lithography. Thereafter, using the resist pattern as a mask, as shown in FIG. 7E, the hard mask film 301 in the NMOS region is selectively removed by wet etching using, for example, a chemical solution mainly composed of H ₂ O _2. .

Next, as shown in FIG. 7F, for example, from La oxide (LaOx) or lanthanum (La) so as to cover the entire surface of the Al-containing layer 203 in the NMOS region and the entire surface of the hard mask film 301 in the PMOS region. A La-containing layer 204 having a thickness of about 2 nm or less is formed. Here, after the formation of the La-containing layer 204, for example, by performing a heat treatment at about 600 ° C. to 1000 ° C. (preferably about 600 ° C. to 700 ° C.), the La atoms in the La-containing layer 204 and the Al-containing layer 203 Al atoms may be diffused into the first HfO ₂ film 202 in the NMOS region and Al atoms in the Al-containing layer 203 may be diffused into the first HfO ₂ film 202 in the PMOS region.

  Next, as shown in FIG. 8A, the excess La-containing layer 204 on the hard mask film 301 in the PMOS region is removed by wet etching using, for example, a chemical solution mainly composed of HCl.

Next, as shown in FIG. 8B, the hard mask film 301 in the PMOS region is removed, for example, by wet etching using a chemical solution mainly composed of H ₂ O ₂ .

Next, as shown in FIG. 8C, a second HfO ₂ film 205 having a thickness of, for example, about 2 nm or less is formed on the La-containing layer 204 in the NMOS region and the Al-containing layer 203 in the PMOS region. As a method for forming the second HfO ₂ film 205, a method similar to the method for forming the first HfO ₂ film 202 described above may be used.

Next, as shown in FIG. 8D, a metal electrode film 302 having a film thickness of about 15 nm made of a metal material for work function determination, for example, TiN, is formed on the second HfO ₂ film 205. Thereafter, although not shown, a polysilicon electrode film containing impurities may be formed on the metal electrode film 302.

  Next, as shown in FIG. 8E, gate patterning is performed in each of the NMOS region and the PMOS region using a photolithography technique and an etching technique. Thereafter, although not shown in the figure, NMOS and PMOS are completed by forming sidewall spacers, extension layers, source / drain regions, and the like.

According to the method of the present embodiment described above, the first HfO ₂ film 202, the Al-containing layer 203, the La-containing layer 204, and the second HfO ₂ film 205 are sequentially formed as the NMOS gate insulating film. For this reason, by appropriately controlling the La distribution and the Al distribution in the gate insulating film, it is possible to easily control the effective work function while suppressing an increase in EOT as compared with the conventional semiconductor device. Specifically, since the La-containing layer 204 is sandwiched between the HfO ₂ films 202 and 205 from above and below in the NMOS region, lanthanum (La) atoms are easily diffused in the HfO ₂ films 202 and 205, so that the effective work function of Control becomes easy. Further, since the second HfO ₂ film 205 is formed above the Al-containing layer 203 and the La-containing layer 204, oxygen atoms in the second HfO ₂ film 205 are transmitted through the gate insulating film in the substrate direction. Since this can be prevented, a situation in which a low dielectric constant layer such as a SiO ₂ film is formed at the gate insulating film / substrate interface can be avoided, thereby suppressing an increase in EOT. Furthermore, since the Al-containing layer 203 is formed below the La-containing layer 204, the diffusion of La atoms having a large atomic radius to the semiconductor substrate side can be suppressed by aluminum (Al) atoms having a small atomic radius. Therefore, deterioration of channel mobility can be suppressed. Therefore, higher functionality and lower power consumption of the NMOS can be realized.

In the NMOS region, Al atoms and La atoms contained in the Al-containing layer 203 and the La-containing layer 204 are converted into the first HfO ₂ film 202 and the second film by heat treatment during the above-described process or subsequent processes, respectively. As a result of diffusion into the HfO ₂ film 205, the Al-containing layer 203 and the La-containing layer 204 do not remain in the gate insulating film (exactly, the High-k film portion excluding the interface layer 201) in the final structure of the device. That is, a hafnium-containing high-k film having an aluminum and lanthanum distribution (concentration profile) is formed as an NMOS gate insulating film.

In addition, according to the method of this embodiment, by appropriately controlling the Al distribution in the PMOS gate insulating film, it is easy to control the effective work function while suppressing an increase in EOT as compared with the conventional semiconductor device. Can be done. Specifically, since the Al-containing layer 203 is sandwiched between the HfO ₂ films 202 and 205 from the upper and lower sides in the PMOS region, aluminum (Al) atoms are easily diffused in the HfO ₂ films 202 and 205. Control becomes easy. In addition, since the second HfO ₂ film 205 is formed on the upper side of the Al-containing layer 203, oxygen atoms in the second HfO ₂ film 205 can be prevented from passing through the gate insulating film in the substrate direction. A situation where a low dielectric constant layer such as a SiO ₂ film is formed at the gate insulating film / substrate interface can be avoided, thereby suppressing an increase in EOT. Therefore, higher functionality and lower power consumption of the PMOS can be realized.

In the PMOS region, Al atoms contained in the Al-containing layer 203 are diffused into the first HfO ₂ film 202 and the second HfO ₂ film 205 by heat treatment during the above-described process or subsequent processes. As a result, in the final structure of the device, the Al-containing layer 203 does not remain in the gate insulating film (more precisely, the High-k film portion excluding the interface layer 201). That is, a hafnium-containing high-k film having an aluminum distribution (concentration profile) is formed as a PMOS gate insulating film.

In the method of this embodiment, another high dielectric constant insulating film may be formed instead of the first HfO ₂ film 202 and the second HfO ₂ film 205.

  In the method of this embodiment, a magnesium-containing layer may be formed instead of the La-containing layer 204.

  In the method of this embodiment, an yttrium-containing layer may be formed instead of the Al-containing layer 203.

(Modification of the first embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a modification of the first embodiment of the present invention will be described with reference to the drawings.

  FIGS. 9A to 9F and FIGS. 10A to 10E show a semiconductor device according to a modification of the first embodiment of the present invention, specifically, a CMOS having an NMOS and a PMOS. It is sectional drawing which shows each process of the manufacturing method of the provided semiconductor device. 9 (a) to 9 (f) and FIGS. 10 (a) to (e), the first embodiment shown in FIGS. 7 (a) to (f) and FIGS. The same components are denoted by the same reference numerals, and redundant description is omitted.

The difference between this modification and the first embodiment is as follows. That is, in the first embodiment, after forming the Al-containing layer 203 in the step shown in FIG. 7C, the hard mask film 301 is formed in the step shown in FIG. After forming the La-containing layer 204 in the step shown in FIG. 8C, the second HfO ₂ film 205 was formed in the step shown in FIG. On the other hand, in this modification, the second HfO ₂ film 205 is formed following the formation of the Al-containing layer 203, and then the hard mask film 301 is formed, and then the La-containing layer 204 is formed.

  Specifically, in the present modification, first, as in the step shown in FIG. 7A of the first embodiment, the element isolation layer 104 is formed on the semiconductor substrate 101 as shown in FIG. After dividing the active region (p-type well region 103) formed in the semiconductor substrate 101 in the NMOS region and the active region (n-type well region 102) formed in the semiconductor substrate 101 in the PMOS region, the NMOS region An interface layer 201 is formed on the semiconductor substrate 101 including the PMOS region.

Next, similarly to the process shown in FIG. 7B of the first embodiment, a first HfO ₂ film 202 is formed on the interface layer 201 as shown in FIG. 9B.

Next, as shown in FIG. 9C, an Al-containing layer 203 is formed on the first HfO ₂ film 202 as in the step shown in FIG. 7C of the first embodiment.

Next, as shown in FIG. 9D, a second HfO ₂ film 205 is formed on the Al-containing layer 203.

Next, after forming a hard mask film 301 on the second HfO ₂ film 205 as shown in FIG. 9E, the hard mask film 301 in the NMOS region is selected as shown in FIG. 9F. To remove.

Next, as shown in FIG. 10A, a La-containing layer 204 is formed so as to cover the entire surface of the second HfO ₂ film 205 in the NMOS region and the entire surface of the hard mask film 301 in the PMOS region. Here, after the formation of the La-containing layer 204, for example, by performing a heat treatment at about 700 ° C. to 1000 ° C., the La atoms in the La-containing layer 204 and the Al atoms in the Al-containing layer 203 are changed to the first HfO in the NMOS region. it may be diffused into the first HfO ₂ film 202 and the second HfO ₂ film 205 in the PMOS region of the Al atoms in the Al-containing layer 203 causes diffuse into ₂ film 202 and the second HfO ₂ film 205 .

  Next, as shown in FIG. 10B, the excessive La-containing layer 204 on the hard mask film 301 in the PMOS region is removed by wet etching using, for example, a chemical solution mainly composed of HCl.

Next, as shown in FIG. 10C, the hard mask film 301 in the PMOS region is removed, for example, by wet etching using a chemical solution containing H ₂ O ₂ as a main component.

Next, as shown in FIG. 10D, a metal electrode film 302 is formed on the second HfO ₂ film 205. Thereafter, although not shown, a polysilicon electrode film containing impurities may be formed on the metal electrode film 302.

  Next, as shown in FIG. 10E, gate patterning is performed in each of the NMOS region and the PMOS region using a photolithography technique and an etching technique. Thereafter, although not shown in the figure, NMOS and PMOS are completed by forming sidewall spacers, extension layers, source / drain regions, and the like.

  According to the method of this modification described above, the same effect as that of the first embodiment can be obtained.

  The semiconductor device and the manufacturing method thereof according to the present invention are preferably used for various electronic devices using a semiconductor integrated circuit.

101 Semiconductor substrate 102 n-type well region 103 p-type well region 104 element isolation layer 105 PMOS
106 NMOS
107 p-type source / drain region 108 p-type extension layer 109 second gate insulating film 110 second metal electrode film 111 second polysilicon electrode film 112 second sidewall spacer 113 n-type source / drain region 114 n Type extension layer 115 first gate insulating film 116 first metal electrode film 117 first polysilicon electrode film 118 first sidewall spacer 201 interface layer 202 first HfO ₂ film 203 Al-containing layer 204 La-containing layer 205 Second HfO ₂ film 301 Hard mask film 302 Metal electrode film

Claims (18)

An n-channel MIS transistor having a first gate electrode formed on a semiconductor substrate via a first gate insulating film;
The semiconductor device according to claim 1, wherein the first gate insulating film includes a first high dielectric constant insulating film containing lanthanum and aluminum. The semiconductor device according to claim 1,
The semiconductor device characterized in that the peak position of the lanthanum concentration in the first high dielectric constant insulating film is closer to the first gate electrode than the peak position of the aluminum concentration in the first high dielectric constant insulating film. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the first gate insulating film has an interface layer formed between the first high dielectric constant insulating film and the semiconductor substrate. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the first high dielectric constant insulating film contains at least one of hafnium and zirconium. The semiconductor device according to any one of claims 1 to 4,
The first high dielectric constant insulating film includes magnesium instead of lanthanum. The semiconductor device according to any one of claims 1 to 5,
The semiconductor device according to claim 1, wherein the first high dielectric constant insulating film contains yttrium instead of aluminum. The semiconductor device according to any one of claims 1 to 6,
The semiconductor device, wherein the first gate electrode has a layer made of titanium nitride or tantalum nitride in contact with the first high dielectric constant insulating film. In the semiconductor device according to claim 1,
2. A semiconductor device according to claim 1, wherein at least a portion of the semiconductor substrate in contact with the first gate insulating film is made of silicon, germanium, or silicon germanium. The semiconductor device according to any one of claims 1 to 8,
A p-channel MIS transistor having a second gate electrode formed on the semiconductor substrate via a second gate insulating film;
The semiconductor device, wherein the second gate insulating film has a second high dielectric constant insulating film containing aluminum. The semiconductor device according to claim 9.
The semiconductor device according to claim 1, wherein a relative dielectric constant of the first gate insulating film is larger than a relative dielectric constant of the second gate insulating film. A step (a) of forming a first gate insulating film on an n-channel MIS transistor formation region in a semiconductor substrate;
And (b) forming a first gate electrode on the first gate insulating film,
The step (a) includes a step of sequentially forming a first high dielectric constant insulating layer, an aluminum containing layer, a lanthanum containing layer, and a second high dielectric constant insulating layer as the first gate insulating film. A method of manufacturing a semiconductor device. The semiconductor device according to claim 11,
The step (a) includes a step of forming a second gate insulating film on the p-channel MIS transistor formation region in the semiconductor substrate,
The step (b) includes a step of forming a second gate electrode on the second gate insulating film,
The step (a) includes a step of sequentially forming the first high dielectric constant insulating layer, the aluminum-containing layer, and the second high dielectric constant insulating layer as the second gate insulating film. A method for manufacturing a semiconductor device. The semiconductor device according to claim 11 or 12,
The method (a) includes a step of forming an interface layer on the semiconductor substrate before forming the first high dielectric constant insulating layer. The semiconductor device according to any one of claims 11 to 13,
The step (a) includes a step of performing a heat treatment at a temperature of 600 ° C. or higher and 700 ° C. or lower after forming the lanthanum-containing layer. The semiconductor device according to any one of claims 11 to 13,
In the step (a), the second high dielectric constant insulating layer is formed before the lanthanum-containing layer. The semiconductor device according to claim 15,
The step (a) includes a step of performing a heat treatment at a temperature of 700 ° C. or higher and 1000 ° C. or lower after forming the lanthanum-containing layer. In the manufacturing method of the semiconductor device of any one of Claims 11-16,
The first high dielectric constant insulating layer and the second high dielectric constant insulating layer are formed using a first gas containing hafnium and a first oxidizing agent containing oxygen. Device manufacturing method. In the manufacturing method of the semiconductor device according to claim 17,
It said first gas, TDMAHf (tetradimethylaminotitanium hafnium), HfCl ₄ (hafnium tetrachloride), TEMAHf (tetrakis ethylmethylamino hafnium) and Hf (MMP) ₄ (tetrakis (l-methoxy-2-methyl-2- Including at least one substance selected from propoxy) hafnium),
The method of manufacturing a semiconductor device, wherein the first oxidizing agent includes at least one substance selected from H ₂ O, O _2, and O ₃ .

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