CN104979207A - Manufacturing method of MOS transistor - Google Patents
Manufacturing method of MOS transistor Download PDFInfo
- Publication number
- CN104979207A CN104979207A CN201410136566.7A CN201410136566A CN104979207A CN 104979207 A CN104979207 A CN 104979207A CN 201410136566 A CN201410136566 A CN 201410136566A CN 104979207 A CN104979207 A CN 104979207A
- Authority
- CN
- China
- Prior art keywords
- side wall
- material layer
- semiconductor material
- substrate
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
A manufacturing method of an MOS transistor comprises the steps of providing a substrate, forming at least two discrete grids on the substrate, and forming the first side walls around the grids; forming a groove in the substrate between the two adjacent first side walls; forming a first semiconductor material in the groove; forming the second side walls around the first side walls after the first semiconductor material is formed in the groove; carrying out the ion implantation on the first semiconductor material to form a source and a drain by taking the second side walls as masks. The MOS transistor formed by the method of the present invention is high in performance.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to the manufacture method of MOS transistor.
Background technology
In existing semiconductor device fabrication process, because stress can change energy gap and the carrier mobility of silicon materials, the performance therefore improving MOS transistor by stress becomes more and more conventional means.Particularly, by suitable proof stress, charge carrier (electronics in nmos pass transistor, the hole in PMOS transistor) mobility can be improved, and then improve drive current, greatly improve the performance of MOS transistor with this.For PMOS transistor, embedded silicon germanium technologies (Embedded SiGeTechnology) can be adopted to produce compression with the channel region at transistor, and then improve carrier mobility.So-called embedded silicon germanium technologies refers to and needs to be formed embedding silicon germanium material in the region of source electrode and drain electrode in Semiconductor substrate, utilizes the lattice mismatch between silicon and SiGe (SiGe) to produce compression to channel region.
Fig. 1 to Fig. 4 is the cross-sectional view of the manufacture method of existing embedded silicon germanium technologies PMOS transistor, specific as follows, with reference to figure 1, Semiconductor substrate 10 is provided, described Semiconductor substrate 10 forms at least two grid structures 11, and shown grid structure 11 comprises formation gate dielectric layer 111 over the substrate 10 and the gate electrode 112 be formed on gate dielectric layer 111.Formation side wall 12 around grid structure 11.With reference to figure 2, with side wall 12 for mask, etch semiconductor substrates 10, adopts on the substrate of the method for isotropic dry etching between two side walls 12 and forms bowl-shape groove 13.With reference to figure 3, the bowl-shape groove 13 of wet etching forms sigma connected in star 14.With reference to figure 4, after forming sigma connected in star 14, in sigma connected in star 14, fill full silicon germanium material 15.Then, ion implantation is carried out to silicon germanium material 15 and form source electrode and drain electrode.
But the performance of the PMOS transistor utilizing prior art to be formed is bad.
Summary of the invention
The problem that the present invention solves is that the performance of the PMOS transistor utilizing prior art to be formed is bad.
For solving the problem, the invention provides a kind of manufacture method of MOS transistor, comprising:
Substrate is provided, forms at least two discrete grids over the substrate, around described grid, form the first side wall;
Groove is formed in substrate between adjacent two described first side walls;
The first semi-conducting material is formed in described groove;
Form the first semi-conducting material in described groove after, formation second side wall around described first side wall;
With described second side wall for mask, ion implantation is carried out to the first semi-conducting material, form source electrode and drain electrode.
Optionally, described groove is sigma connected in star, and the ion of described ion implantation is boron ion.
Optionally, the step forming groove in the substrate between adjacent two described first side walls comprises:
Adopt the substrate between adjacent two described first side walls of isotropic dry etch, form bowl-shape groove;
Adopt the bowl-shape groove of wet etching, form sigma connected in star.
Optionally, the end face of described first semi-conducting material is equal with described substrate surface.
Optionally, described first semi-conducting material is SiGe.
Optionally, form the method for the second side wall around described first side wall after, also comprise the following steps:
Described first semi-conducting material is formed the second semiconductor material layer or the 3rd semiconductor material layer.
Optionally, described second semi-conducting material and the first semi-conducting material are same material.
Optionally, described first semi-conducting material forms the second semiconductor material layer, described second semiconductor material layer is also formed the 3rd semiconductor material layer.
Optionally, the material of described 3rd semiconductor material layer is silicon.
Optionally, described first side wall is identical with the material of the second side wall.
Compared with prior art, technical scheme of the present invention has the following advantages:
Around grid structure, first form the first side wall, the thickness of the first side wall be less than the second side wall of the first side wall and follow-up formation thickness and.Wherein, the first side wall in technical solution of the present invention and the thickness of the second side wall and equal side wall thicknesses of the prior art.Therefore, the distance between two adjacent the first side walls is larger than the distance between adjacent two the second side walls, and that is, the distance between two adjacent the first side walls is larger than the distance between two side walls adjacent in prior art.The transverse width of the groove defined by the first side wall is greater than the transverse width of sigma connected in star of the prior art.Like this, when the recessed sidewall portions nearest from raceway groove is identical with prior art with the vertical range of substrate surface, the technical program can make to reduce much from the horizontal range between the nearest recessed sidewall portions of raceway groove and grid structure.Therefore, the first semiconductor material layer formed in groove can apply maximum stress to the raceway groove under grid structure, and the degree applying maximum stress is large more than prior art, thus the carrier mobility of the MOS transistor of follow-up formation can be improved, carry out the performance of the MOS transistor improving follow-up formation.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the cross-sectional view of the manufacture method of existing embedded silicon germanium technologies PMOS transistor;
Fig. 5 to Figure 10 is the cross-sectional view of the manufacture method of MOS transistor in the specific embodiment of the invention.
Embodiment
Through finding and research, the reason that the performance of the PMOS transistor utilizing prior art to be formed is bad is as follows:
With reference to figure 2, adopt on the substrate of the method for anisotropic dry etch between adjacent two side walls 12 and form bowl-shape groove 13.Then, with reference to figure 3, wet etching is carried out to bowl-shape groove 13, form sigma connected in star 14.Horizontal distance W between raceway groove below the tip 141 of sigma connected in star 14 formed and grid structure 11 is too large, the maximum stress that the SiGe pair pmos transistor formed in sigma connected in star 14 is produced adds on the raceway groove below less than grid structure 11, therefore, the stress that the SiGe pair pmos transistor formed in sigma connected in star 14 produces is inadequate, thus be unfavorable for the carrier mobility improving PMOS transistor, and then affect the performance of PMOS transistor.
In order to solve the problems of the technologies described above, the method of isotropic dry etch can be adopted to increase the transverse width of bowl-shape groove 13, thus the horizontal distance W reduced between the raceway groove below the tip 141 of sigma connected in star 14 and grid structure 11, and then improve the performance of PMOS transistor of follow-up formation.But effect is bad, reason is as follows: formed in the process of bowl-shape groove 13, and isotropic dry etch all can etch substrate 10 with vertical direction in the horizontal direction.Therefore, while increasing the transverse width of bowl-shape groove 13, longitudinal width of bowl-shape groove 13 too increases.That is, in order to reduce the horizontal distance W between the raceway groove below the tip 141 of sigma connected in star 14 and grid structure 11, vertical range H between the tip 141 of sigma connected in star and substrate surface also can increase, like this, the maximum stress that the SiGe formed in sigma connected in star 14 can be made equally to produce cannot add on the raceway groove below grid structure 11.Therefore, the stress that this SiGe produces the PMOS transistor of follow-up formation is also inadequate, and then can affect the performance of PMOS transistor.
In order to better solve the problems of the technologies described above, the invention provides a kind of manufacture method of MOS transistor, adopt method of the present invention can improve the performance of MOS transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
First, with reference to figure 5, provide substrate 20, described substrate 20 is formed at least two discrete grid structures 21, the grid 212 that described grid structure 21 comprises gate dielectric layer 211 and is positioned on gate dielectric layer 211, forms the first side wall 22 around described grid structure 21.
The material of described Semiconductor substrate 20 can be monocrystalline silicon (monocrystalline) substrate, also can be silicon-on-insulator (silicon on insulator) substrate.Certainly, it also can be other backing material well-known to those skilled in the art.
Be formed with gate dielectric layer 211 on a substrate 20, the material of gate dielectric layer 211 is silica.Gate dielectric layer 211 is formed grid 212, and the material of grid 212 is polysilicon.The method forming grid structure 21 is specially:
On a substrate 20 deposit one deck gate dielectric material layer (not shown), on gate dielectric material layer deposition of gate material layer (not shown), gate material layers is formed patterned mask layer (not shown), the material of mask layer can be the hard mask material such as photoresist or silicon nitride, silicon oxynitride, boron nitride, titanium nitride, tantalum nitride, also can be photoresist upper, hard mask material under combination mask layer, combination mask layer can provide better pattern to control.With described patterned mask layer for mask etching gate material layers and gate dielectric material layer, form gate dielectric layer 211 and grid 212.
After forming grid structure 21, formation first side wall 22 around grid structure 21.In the present embodiment, the material of the first side wall 22 is silicon nitride.Concrete manufacture method is as follows:
The method of chemical vapor deposition (CVD) is adopted to form the first spacer material layer at the end face of the sidewall of grid structure 21, the top of patterned mask layer and substrate 20.Then, the method for carving is adopted back to etch the first spacer material layer, formation first side wall 22 around grid structure 21.The depositing temperature of chemical vapour deposition (CVD) is 100 ~ 900 DEG C.In the present embodiment, returning the thickness carving the first side wall 22 formed is 5 ~ 200A, and the thickness of the first side wall is less than the thickness of side wall of the prior art.First side wall 22 is for defining the distance between the raceway groove below the tip of the sigma connected in star of follow-up formation and grid structure 21.The thickness of the first side wall 22 is too large or too little, all can affect the first semiconductor material layer in the sigma connected in star of follow-up formation and apply effect to the stress of raceway groove.
In other embodiments, the method forming the first spacer material layer can also be physical vaporous deposition (Physical Vapor Deposition, PVD), furnace oxidation method (Furnace), atom deposition method (AtomicLayer Deposition, and molecule pack epitaxy (Molecular Beam Epitaxy, MBE) ALD).
Then, with reference to figure 6, in the substrate 20 between adjacent two described first side walls 22, bowl-shape groove 23 is formed.
The method etching of isotropic dry etch is adopted to form bowl-shape groove 23.Wherein, etching gas comprises hydrogen bromide and chlorine.Concrete technology is as follows: the flow of hydrogen bromide is 200 ~ 800sccm, and the flow of chlorine is 20 ~ 100sccm, and the flow of inert gas is 50 ~ 1000sccm, and the pressure of etching cavity is 2 ~ 200mTorr, and etch period is 15 ~ 60s.
Then, with reference to figure 7, adopt the method for wet etching to corrode bowl-shape groove 23, form sigma connected in star 24.
Be specially: bowl-shape groove 23 is exposed to TMAH(Tetramethyl Ammonium Hydroxied, tetramethyl aqua ammonia) in the aqueous solution, TMAH aqueous corrosion substrate 20.The concentration of volume percent forming region formation sigma connected in star 24, the TMAH aqueous solution of bowl-shape groove 23 is in the substrate 20 2% ~ 20%, and temperature is 20 ~ 80 DEG C, and the time is 100 ~ 500s.
In other embodiments, wet etching agent also can be other hydroxyl alkaline solution, also belongs within protection scope of the present invention.
Then, with reference to figure 8, in described sigma connected in star 24, the first semiconductor material layer 25 is formed.
In the present embodiment, when MOS transistor is PMOS transistor, the first semiconductor material layer 25 is SiGe (SiGe) material, and silicon germanium material can introduce the compression that between silicon and SiGe, lattice mismatch is formed, thus improves the performance of PMOS transistor;
In the present embodiment, the formation process of described first semiconductor material layer 25 is chemical vapor deposition method.Concrete technology is as follows: silicon source gas is SiH
4or SiH
2cl
2, germanium source gas is GeH
4, carrier gas is hydrogen.The flow of silicon source gas and germanium source gas is 1 ~ 1000sccm, and the flow of described carrier gas is 0.1 ~ 50slm, and temperature is 500 ~ 800 DEG C, and pressure is 1 ~ 100Torr.
In other embodiments, the manufacture method of the first semiconductor material layer 25 also can be ALD, MBE.
In the present embodiment, the first semiconductor material layer 25 end face needs equal with substrate 20 end face.If the end face of the first semiconductor material layer 25 is higher than the end face of substrate 20, the distance of the first semiconductor material layer 25 and the first side wall is very near, and the thinner thickness of the first side wall 22, the maximum stress that first semiconductor material layer 25 produces can be added on grid structure 21, thus can affect the performance of the MOS transistor of follow-up formation; If the first semiconductor material layer 25 end face is lower than the end face of substrate 20, the maximum stress that the first semiconductor material layer 25 produces adds inside the raceway groove below less than grid structure 21, equally also can affect the performance of the MOS transistor of follow-up formation.
Then, with reference to figure 9, form the first semiconductor material layer 25 in described sigma connected in star 24 after, formation second side wall 26 around described first side wall 22.
The material of the second side wall 26 is identical with the material of the first side wall 22.In the present embodiment, it is also silicon nitride.
The concrete manufacture method of the second side wall 26 is as follows: adopt the method for chemical vapor deposition (CVD) to form the second spacer material layer at the end face of the sidewall of the first side wall 22, the top of patterned mask layer and substrate 20.Then, the method for carving is adopted back to etch the second spacer material layer, then formation second side wall 26 around the first side wall 22.The depositing temperature of chemical vapour deposition (CVD) is 100 ~ 900 DEG C.In the present embodiment, returning the thickness carving the second side wall 26 formed is 5 ~ 200 dusts.First side wall 22 and the thickness of the second side wall 26 and with side wall 12(of the prior art with reference to figure 4) thickness identical, therefore, the thickness of the second side wall depends on the thickness of the first side wall 22.If the second side wall is too thick or too thin, the second semiconductor material layer of follow-up formation also can be affected to the effect of the raceway groove stress application under grid structure.
In other embodiments, the method forming the second spacer material layer can also be physical vaporous deposition (Physical Vapor Deposition, PVD), furnace oxidation method (Furnace), atom deposition method (AtomicLayer Deposition, and molecule pack epitaxy (Molecular Beam Epitaxy, MBE) ALD).
Then, with reference to Figure 10, after forming the second side wall 26, the second semiconductor material layer 27 is formed on the surface of the first semiconductor material layer 25.
In the present embodiment, the second semiconductor material layer 27 is identical with the material of the first semiconductor material layer 25, is also SiGe.The method forming the second semiconductor material layer 27 is chemical vapour deposition (CVD).Concrete technology condition is as follows: depositing temperature is 400 ~ 800 DEG C, and deposit thickness is 5 ~ 10nm.In other embodiments, the method forming the second semiconductor material layer also can be furnace oxidation method, atom deposition method and molecule pack epitaxy.
Why form the second semiconductor material layer 27, reason is as follows: in actual process, needs the end face of the first semiconductor material layer 25 equal with substrate 20 end face.But from microcosmic, by the restriction of actual process, the end face of the first semiconductor material layer 25 of formation is can not be absolutely equal with substrate 20 end face, and that is, the end face of the first semiconductor material layer 25 can not be absolutely smooth.Lower than the applying maximum stress that the first semiconductor material layer 25 part of substrate 20 end face can not be just right to the raceway groove below grid structure 21, thus affect the performance of the semiconductor device of follow-up formation.If form the second semiconductor material layer 27, second semiconductor material layer 27 can make up the part of the first semiconductor material layer 25 end face lower than substrate 20 end face on the first semiconductor material layer 25.That is, the second semiconductor material layer 27 can work with the first semiconductor material layer 25 1, the applying maximum stress just right to the raceway groove below grid structure 21, thus obtains performance preferably MOS transistor.
If the thickness of the second semiconductor material layer 27 is too little, the applying maximum stress that the raceway groove below the second semiconductor material layer 27 pairs grid structure 21 can not be just right, thus affect the performance of the MOS transistor of follow-up formation.If the thickness of the second semiconductor material layer 27 is too large, increases contact resistance, affect the speed of service of subsequent device.
Certainly, in other embodiments, the first semiconductor material layer is not formed the second semiconductor material layer and belong to protection scope of the present invention yet.
Then, continue, with reference to Figure 10, the second semiconductor material layer 27 to form the 3rd semiconductor material layer 28.
In the present embodiment, the 3rd semiconductor material layer 28 is silicon layer.The method forming silicon layer is also chemical vapour deposition (CVD).In other embodiments, also can be furnace oxidation method, atom deposition method and molecule pack epitaxy.The thickness of silicon layer is 15 ~ 20nm.
3rd semiconductor material layer 28 then, carries out ion implantation to the first semiconductor material layer 25 to the 3rd semiconductor material layer 28 after being formed, and forms source electrode and drain electrode.
In the present embodiment, the ion of described ion implantation is boron ion, and the transistor of formation is PMOS transistor.The method of concrete formation source electrode and drain electrode knows technology for those skilled in the art, does not repeat at this.
It should be noted that, in the forming step of follow-up MOS transistor, need to form conductive plunger on source electrode and drain electrode, in order to reduce the contact resistance between conductive plunger and source electrode, drain electrode, metal silicide layer can be formed at the end face of source electrode and drain electrode, like this, be formed with the source electrode of metal silicide and drain electrode when being electrically connected with contact plunger, the contact resistance between conductive plunger and source electrode, drain electrode can be reduced.The 3rd semiconductor material layer 28 in the present embodiment is just used to formation metal silicide layer.But, in the present embodiment, utilize silicon minimum to the contact resistance forming metal silicide layer, thus be conducive to the performance of the PMOS transistor improving follow-up formation.
If the 3rd semiconductor material layer is too thin, subsequent metal silicide will exhaust this layer, and consume lower floor's stress silicon germanium layer, thus affect stress applying effect, affect carrier mobility, reduce device performance.If the 3rd semiconductor material layer is too thick, then increases contact resistance, affect device speed.
In other embodiments, the second semiconductor material layer is not formed the 3rd material layer, directly utilize the second semiconductor material layer to be applicable to the present invention to the method forming metal silicide yet.The performance of the PMOS transistor that the metal silicide that just performance of the PMOS transistor of formation does not utilize silicon to be formed is formed is good.
In the present embodiment, around grid structure, first form the first side wall, the thickness of the first side wall be less than the second side wall of the first side wall and follow-up formation thickness and.Wherein, the first side wall and the second side wall thickness and equal side wall thicknesses of the prior art.Therefore, the distance between two adjacent the first side walls is larger than the distance between adjacent two the second side walls, and that is, the distance between two adjacent the first side walls is larger than the distance between two side walls adjacent in prior art.The transverse width T2 of the bowl-shape groove defined by the first side wall is greater than the transverse width T1 of bowl-shape groove of the prior art.When the sigma connected in star formed vertical range that is most advanced and sophisticated and substrate surface is same as the prior art, the horizontal range between sigma connected in star tip and grid structure can be reduced a lot.Therefore, the first semiconductor material layer formed in sigma connected in star can be just right to the raceway groove under grid structure applying maximum stress, and the degree applying maximum stress is large more than prior art, thus the carrier mobility of the PMOS transistor of follow-up formation can be improved, carry out the performance of the PMOS transistor improving follow-up formation.
Moreover, the second semiconductor material layer that first semiconductor material layer is formed can with the first material layer acting in conjunction, the maximum stress of common applying can both add on the raceway groove below grid structure, thus improve the carrier mobility of the PMOS transistor of follow-up formation further, and then the performance of the PMOS transistor of the follow-up formation of raising further.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a manufacture method for MOS transistor, is characterized in that, comprising:
Substrate is provided, forms at least two discrete grids over the substrate, around described grid, form the first side wall;
Groove is formed in substrate between adjacent two described first side walls;
The first semi-conducting material is formed in described groove;
Form the first semi-conducting material in described groove after, formation second side wall around described first side wall;
With described second side wall for mask, ion implantation is carried out to the first semi-conducting material, form source electrode and drain electrode.
2. manufacture method as claimed in claim 1, it is characterized in that, described groove is sigma connected in star, and the ion of described ion implantation is boron ion.
3. manufacture method as claimed in claim 2, it is characterized in that, the step forming groove in the substrate between adjacent two described first side walls comprises:
Adopt the substrate between adjacent two described first side walls of isotropic dry etch, form bowl-shape groove;
Adopt the bowl-shape groove of wet etching, form sigma connected in star.
4. manufacture method as claimed in claim 1, it is characterized in that, the end face of described first semi-conducting material is equal with described substrate surface.
5. manufacture method as claimed in claim 2, it is characterized in that, described first semi-conducting material is SiGe.
6. manufacture method as claimed in claim 1, is characterized in that, after forming the method for the second side wall, also comprise the following steps: around described first side wall
Described first semi-conducting material is formed the second semiconductor material layer or the 3rd semiconductor material layer.
7. manufacture method as claimed in claim 6, it is characterized in that, described second semi-conducting material and the first semi-conducting material are same material.
8. manufacture method as claimed in claim 6, is characterized in that, described first semi-conducting material forms the second semiconductor material layer, described second semiconductor material layer is also formed the 3rd semiconductor material layer.
9. manufacture method as claimed in claim 6, it is characterized in that, the material of described 3rd semiconductor material layer is silicon.
10. manufacture method as claimed in claim 1, it is characterized in that, described first side wall is identical with the material of the second side wall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410136566.7A CN104979207B (en) | 2014-04-04 | 2014-04-04 | The production method of MOS transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410136566.7A CN104979207B (en) | 2014-04-04 | 2014-04-04 | The production method of MOS transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104979207A true CN104979207A (en) | 2015-10-14 |
| CN104979207B CN104979207B (en) | 2019-04-26 |
Family
ID=54275605
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410136566.7A Active CN104979207B (en) | 2014-04-04 | 2014-04-04 | The production method of MOS transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104979207B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08255903A (en) * | 1995-03-15 | 1996-10-01 | Seiko Epson Corp | Semiconductor device and fabrication thereof |
| CN101578690A (en) * | 2006-11-21 | 2009-11-11 | 先进微装置公司 | Stress enhanced MOS transistor and methods for its fabrication |
| CN103681324A (en) * | 2012-08-30 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for MOS (Metal Oxide Semiconductor) transistor |
-
2014
- 2014-04-04 CN CN201410136566.7A patent/CN104979207B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08255903A (en) * | 1995-03-15 | 1996-10-01 | Seiko Epson Corp | Semiconductor device and fabrication thereof |
| CN101578690A (en) * | 2006-11-21 | 2009-11-11 | 先进微装置公司 | Stress enhanced MOS transistor and methods for its fabrication |
| CN103681324A (en) * | 2012-08-30 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for MOS (Metal Oxide Semiconductor) transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104979207B (en) | 2019-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10361201B2 (en) | Semiconductor structure and device formed using selective epitaxial process | |
| CN101027770B (en) | Integrated circuit with metal gate electrode and method for manufacturing metal gate electrode | |
| CN105470132A (en) | Fin field-effect transistor formation method | |
| CN104733312A (en) | Fin-type field effect transistor forming method | |
| CN104900521B (en) | Fin formula field effect transistor and forming method thereof | |
| CN103871968A (en) | Manufacturing method of MOS (metal oxide semiconductor) transistor | |
| CN104616979A (en) | Forming method of semiconductor device | |
| CN105280492A (en) | Method for forming semiconductor structure | |
| CN104752216B (en) | The forming method of transistor | |
| CN103000499B (en) | A kind of germanium silicon boron outer layer growth method | |
| CN105529265A (en) | MOS transistor and MOS transistor manufacturing method | |
| CN102856179B (en) | The formation method of semiconductor device | |
| CN103390558B (en) | The forming method of transistor | |
| CN103165416B (en) | For the manufacture method of hard mask of etching and preparation method thereof and MOS device | |
| CN102983104B (en) | The manufacture method of CMOS transistor | |
| CN102867749B (en) | Method for forming MOS (metal oxide semiconductor) transistor | |
| CN105448723A (en) | Semiconductor device and forming method thereof | |
| CN104979207A (en) | Manufacturing method of MOS transistor | |
| CN105448982B (en) | MOS transistor and preparation method thereof | |
| CN105632926B (en) | The forming method of fin formula field effect transistor | |
| CN104701149A (en) | Semiconductor device and forming method thereof | |
| CN103377898B (en) | The formation method of semiconductor device, the formation method of fin field effect pipe | |
| CN103094108B (en) | The manufacture method of semiconductor device | |
| CN104701166A (en) | Semiconductor component forming method | |
| CN106558499B (en) | The forming method of MOS transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |