CN104979003A - Latch enabling signal processing apparatus in data storage type flash memory - Google Patents
Latch enabling signal processing apparatus in data storage type flash memory Download PDFInfo
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- CN104979003A CN104979003A CN201510405944.1A CN201510405944A CN104979003A CN 104979003 A CN104979003 A CN 104979003A CN 201510405944 A CN201510405944 A CN 201510405944A CN 104979003 A CN104979003 A CN 104979003A
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Abstract
The present invention provides a latch enabling signal processing apparatus in a data storage type flash memory, which comprises a first phase inverter, a second phase inverter, a third phase inverter, a transmission gate, a NOR gate and an enabling phase inverter. The input end of the first phase inverter is connected with an external processor and the output end of the first phase inverter is connected with the input end of the transmission gate; the output end of the transmission gate is connected with the first input end of the NOR gate and the output end of the enabling phase inverter; the second input end of the NOR gate is switched into a chip resetting signal and the output end of the NOR gate is connected with the input end of the second phase inverter and the input end of the enabling phase inverter; the output end of the enabling phase inverter is connected with the first input end of the NOR gate and the output end of the transmission gate; and the output end of the second phase inverter is connected with the input end of the third phase inverter and the output end of the third phase inverter is connected with a state machine. In a positive feedback mode, ALE and CLE signals of a latch inside a chip overcome the defect of insufficient signal holding time, which is caused by reduction of a working voltage, of a chip transistor and meet the established standard of chip use.
Description
Technical field
The present invention relates to the technical field of storage operation, particularly relate to latch enable signal treating apparatus in a kind of data storage type flash memory.
Background technology
Along with the development of electronic product, also there is huge change in chip technology.Data storage type flash memory is as the one of flash memory FLASH, and the realization being solid-state large-capacity internal memory due to its internal nonlinearity macroelement pattern provides cheap effective solution.It is larger that data storage type flash memories has capacity, the advantages such as rewriting speed is fast, be applicable to the storage of mass data, thus in the industry cycle obtain and apply more and more widely, as embedded product comprises the USB flash disk etc. of digital camera, MP3 walkman memory card, compact.
But also there is certain deficiency in its application in data storage type flash memory.Because the operating voltage of electronic product is more and more lower, transistor in chip is caused under this low-pressure state, to cause the part signal retention time can not meet the written standards of chip use.
Summary of the invention
For above deficiency, the present invention proposes latch enable signal treating apparatus in a kind of data storage type flash memory, can make, when the signal retention time is not enough, to enable signal meet written standards by process.
In order to realize above technical scheme, the invention provides latch enable signal treating apparatus in a kind of data storage type flash memory, comprising, the first phase inverter, the second phase inverter, the 3rd phase inverter, transmission gate, rejection gate and enable phase inverter;
Wherein, described first inverter input is connected with ppu, and for receiving latch enable signal, the output terminal of described first phase inverter is connected with the input end of described transmission gate;
Described transmission gate includes the first control end and the second control end, respectively the negative signal of the inner write enable signal of access chip and chip internal write enable signal; The output terminal of described transmission gate is connected with the output terminal of the first input end of described rejection gate and described enable phase inverter;
Second input end access chip reset signal of described rejection gate, the output terminal of described rejection gate is connected with the input end of described second phase inverter and described enable inverter input;
Described enable phase inverter includes the first control end and the second control end, the negative signal of the inner write enable signal of access chip and chip internal write enable signal respectively, the output terminal of described enable phase inverter is connected with the output terminal of described rejection gate first input end and described transmission gate;
The output terminal of described second phase inverter is connected with the input end of described 3rd phase inverter, and the output terminal of described 3rd phase inverter is connected with state machine.
Further, described transmission gate first control end accesses described chip internal write enable signal, and described second control end accesses the negative signal of described chip internal write enable signal, for controlling opening and closing of described transmission gate.
Further, described enable phase inverter first control end accesses described chip internal write enable signal, described second control end accesses the negative signal of described chip internal write enable signal, for controlling opening and closing of described enable phase inverter, and then regulate the positive feedback between described enable phase inverter and described rejection gate.
Further, what the control end of described transmission gate and the control end of described enable phase inverter accessed is synchronous write enable signal.
Further, described latch enable signal comprises address latch enable signal or order latch enable signal.
The present invention, by adding transmission gate and positive feedback devices to original chip internal control circuit, pins chip internal latch enable signal.Make by the mode of positive feedback the latch enable signal being latched in chip internal, overcome chip transistor and cause the signal retention time not enough due to the reduction of operating voltage, meet the written standards that chip uses.
Accompanying drawing explanation
Fig. 1 is the structural drawing of the latch enable signal treating apparatus in a kind of data storage type flash memory of providing of the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not full content.
Latch enable signal treating apparatus structural drawing in a kind of data storage type flash memory that Fig. 1 provides for the embodiment of the present invention.As shown in Figure 1, the first phase inverter 101, second phase inverter 102, the 3rd phase inverter 103, transmission gate 104, rejection gate 105 and enable phase inverter 106 is comprised.Wherein, 1 is chip internal write enable signal, and 2 is the negative signal of chip internal write enable signal, and 3 is chip reset signal.
Wherein, the first phase inverter 101 input end is connected with ppu 100, and for receiving latch enable signal, the output terminal of the first phase inverter 101 is connected with the input end of transmission gate 104.
It should be noted that latch enable signal comprises address latch enable signal and order latch enable signal, two signals can be selected to send simultaneously or timesharing sends.
Transmission gate 104 includes the first control end and the second control end, respectively the negative signal 2 of the inner write enable signal 1 of access chip and chip internal write enable signal; The first input end of the output terminal AND OR NOT gate 105 of transmission gate 104 and the output terminal of enable phase inverter 106 are connected.
Here transmission gate 104 serves the effect of a switch.Here on-off action refers to, opening and closing of transmission gate is controlled by outside write enable signal.Inner write enable signal 1, second control end of the first control end access chip due to transmission gate 104 accesses the negative signal 2 of outside enable signal, and takes logical operation between two signals.When chip internal write enable signal is high level, transmission gate 104 is opened, and when chip internal write enable signal is low level, transmission gate 104 is closed.
When transmission gate 104 is in open mode, address latch enable signal or order latch enable signal just transfer to the first input end of rejection gate 105.
Second input end access chip reset signal 3 of rejection gate 105, the output terminal of rejection gate 105 is connected with the input end of the second phase inverter 102 and enable phase inverter 106 input end.
Described enable phase inverter 106 includes the first control end and the second control end, the negative signal 2 of the inner write enable signal 1 of access chip and chip internal write enable signal respectively, the output terminal of enable phase inverter 106 is connected with the output terminal of described rejection gate 105 first input end and enable phase inverter 106.
It should be noted that rejection gate 105 and enable phase inverter 106 constitute jointly the signal latch of a positive feedback.This latch by access chip reset signal 3, and carries out or non-logical operation with register enable signal, and this computing is stored in the register enable signal in latch before being intended to remove, and then provides storage space for this cycle register enable signal.
And enable phase inverter 106 is by the inner write enable signal 1 of the first control end access chip, the negative signal 2 of the inner write enable signal of the second control end access chip, whether register enable signal is latched for controlling positive feedback signal latch, when chip internal write enable signal is low level, register enable signal can output to the second phase inverter 102 by positive feed-back latch, when chip internal write enable signal is high level, register enable signal can be latched in positive feed-back latch inside.
The output terminal of described second phase inverter 102 is connected with the input end of described 3rd phase inverter 103, and the output terminal of described 3rd phase inverter 103 is connected with state machine 107.
Wherein, the second phase inverter 102 carries out shaping by the mode of connecting to the register enable signal exported with the 3rd phase inverter 103, and can play the effect increasing and drive.
In a kind of data storage type flash memory, the specific works process of latch enable signal treating apparatus is as follows:
Latch enable signal that ppu 100 sends (comprise one of address latch enable signal ALE and order latch enable signal CLE or all), be loaded into the input end of the first phase inverter 101, and export the reverse signal for corresponding latch enable signal.
No. 2, the negative letter of chip internal write enable signal 1 and chip internal write enable signal is loaded into the different control ends of transmission gate 104 and enable phase inverter 106 simultaneously.
Wherein, the negative signal 2 of chip internal write enable signal 1 and chip internal write enable signal is loaded into the first control end of transmission gate 104 and the second control end switch for controls transfer door 104, when chip internal write enable signal is high level, transmission gate 104 conducting; When chip internal write enable signal is low level, transmission gate 104 is closed.
The negative signal 2 of chip internal write enable signal 1 and chip internal write enable signal is loaded into the first control end of enable phase inverter 106 and the second control end is applied to the signal latch controlling the positive feedback be made up of rejection gate 105 and enable phase inverter 106.When chip internal write enable signal is high level, positive feed-back latch pins latch enable signal; When chip internal write enable signal is low level, latch enable signal is transferred to the second reverser by positive feed-back latch.
It can thus be appreciated that, when chip internal write enable signal is high level, transmission gate 104 conducting, positive feed-back latch pins latch enable signal, when chip internal write enable signal is low level, transmission gate 104 is closed, and the latch enable signal being latched in latch inside is released into the second phase inverter 102 by positive feed-back latch.
Second phase inverter 102 carries out shaping by the mode of connecting to the register enable signal exported with the 3rd phase inverter 103, and can play the effect increasing and drive.Through the latch enable signal of positive feed-back latch release carry out rectification by the second phase inverter 102 and the 3rd phase inverter 103 and drive increase after output in external state machine 107.
It is worth mentioning that, external state machine 107, for each collection signal in receiving chip inside, carries out processing and sends corresponding control command to each ingredient of chip internal.
The present embodiment employing rejection gate two ends add is with the phase inverter of enable control as positive feedback devices, for address latch enable signal in latch cicuit and order latch enable signal, by address latch enable signal and order latch enable signal in release positive feedback, overcome and cause the signal retention time not enough because operate outside voltage reduces, the shortcoming of chip written standards can not be met, and then improve chip operation reliability.
It should be noted that; the above is only the preferred embodiment of the present invention, it should be pointed out that for those skilled in the art; the equivalent variations made under the prerequisite of the design and principle that do not depart from the principle of the invention, amendment and combination, all should belong to protection scope of the present invention.
Claims (5)
1. a latch enable signal treating apparatus in data storage type flash memory, is characterized in that, comprises the first phase inverter, the second phase inverter, the 3rd phase inverter, transmission gate, rejection gate and enable phase inverter;
Wherein, described first inverter input is connected with ppu, and for receiving latch enable signal, the output terminal of described first phase inverter is connected with the input end of described transmission gate;
Described transmission gate includes the first control end and the second control end, respectively the negative signal of the inner write enable signal of access chip and chip internal write enable signal; The output terminal of described transmission gate is connected with the output terminal of the first input end of described rejection gate and described enable phase inverter;
Second input end access chip reset signal of described rejection gate, the output terminal of described rejection gate is connected with the input end of described second phase inverter and described enable inverter input;
Described enable phase inverter includes the first control end and the second control end, the negative signal of the inner write enable signal of access chip and chip internal write enable signal respectively, the output terminal of described enable phase inverter is connected with the output terminal of described rejection gate first input end and described transmission gate;
The output terminal of described second phase inverter is connected with the input end of described 3rd phase inverter, and the output terminal of described 3rd phase inverter is connected with state machine.
2. latch enable signal treating apparatus in data storage type flash memory according to claim 1, it is characterized in that, described transmission gate first control end accesses described chip internal write enable signal, described second control end accesses the negative signal of described chip internal write enable signal, for controlling opening and closing of described transmission gate.
3. latch enable treating apparatus in data storage type flash memory according to claim 1, it is characterized in that, described enable phase inverter first control end accesses described chip internal write enable signal, described second control end accesses the negative signal of described chip internal write enable signal, for controlling opening and closing of described enable phase inverter, and then regulate the positive feedback between described enable phase inverter and described rejection gate.
4. latch enable treating apparatus in the data storage type flash memory according to Claims 2 or 3, is characterized in that, what the control end of described transmission gate and the control end of described enable phase inverter accessed is synchronous write enable signal.
5. latch enable treating apparatus in data storage type flash memory according to claim 1, is characterized in that, described latch enable signal comprises address latch enable signal or order latch enable signal data storage type flash memory.
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| CN201510405944.1A CN104979003B (en) | 2015-07-10 | 2015-07-10 | A kind of latch enable signal processing unit in data storage type flash memory |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080117706A1 (en) * | 2006-11-16 | 2008-05-22 | Hynix Semiconductor Inc. | Semiconductor device |
| US20090190430A1 (en) * | 2008-01-30 | 2009-07-30 | Hee Bok Kang | Non-volatile latch circuit for restoring data after power interruption |
| CN204808883U (en) * | 2015-07-10 | 2015-11-25 | 北京兆易创新科技股份有限公司 | Latch enable signal processing apparatus in data storage type flash memory |
| CN106172611A (en) * | 2016-08-09 | 2016-12-07 | 洪霞 | For making the industrialized preparing process of wheaten food |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080117706A1 (en) * | 2006-11-16 | 2008-05-22 | Hynix Semiconductor Inc. | Semiconductor device |
| US20090190430A1 (en) * | 2008-01-30 | 2009-07-30 | Hee Bok Kang | Non-volatile latch circuit for restoring data after power interruption |
| CN204808883U (en) * | 2015-07-10 | 2015-11-25 | 北京兆易创新科技股份有限公司 | Latch enable signal processing apparatus in data storage type flash memory |
| CN106172611A (en) * | 2016-08-09 | 2016-12-07 | 洪霞 | For making the industrialized preparing process of wheaten food |
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