CN104979003B - A kind of latch enable signal processing unit in data storage type flash memory - Google Patents
A kind of latch enable signal processing unit in data storage type flash memory Download PDFInfo
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- CN104979003B CN104979003B CN201510405944.1A CN201510405944A CN104979003B CN 104979003 B CN104979003 B CN 104979003B CN 201510405944 A CN201510405944 A CN 201510405944A CN 104979003 B CN104979003 B CN 104979003B
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Abstract
The present invention provides latch enable signal processing units in a kind of data storage type flash memory, including, the first phase inverter, the second phase inverter, third phase inverter, transmission gate, nor gate and enabled phase inverter；First inverter input is connected with ppu, and output end is connected with transmission gate input terminal；It transmits gate output terminal AND OR NOT gate first input end and enabled inverter output is connected；Nor gate the second input terminal access chip reset signal, output end are connected with the second inverter input and enabled inverter input；Enabled inverter output AND OR NOT gate first input end and the transmission gate output terminal are connected；The output end of second phase inverter is connected with third inverter input, and third inverter output is connected with state machine.Make the ALE and CLE signal that are latched in chip interior by way of positive feedback, overcomes chip transistor since the reduction of operating voltage causes the signal retention time insufficient, meet the written standards that chip uses.
Description
Technical field
The present invention relates to the technical fields of storage operation, make more particularly to latch in a kind of data storage type flash memory
It can signal processing apparatus.
Background technique
With the continuous development of electronic products, also huge variation is occurring for chip technology.Data storage type flash memory is made
For one kind of flash memory FLASH, since its internal nonlinearity macroelement mode provides inexpensively for the realization of solid-state large-capacity memory
Effective solution scheme.Data storage type flash memories have many advantages, such as that capacity is larger, and rewriting speed is fast, are suitable for a large amount of numbers
According to storage, thus be in the industry cycle more and more widely used, as included digital camera, MP3 carry-on in embedded product
Listen the USB flash disk etc. of memory card, compact.
But there is also certain deficiencies in its application field for data storage type flash memory.Since the operating voltage of electronic product is got over
Come lower, causes in chip transistor work under this low-pressure state, causing the part signal retention time not to be able to satisfy chip makes
Written standards.
Summary of the invention
Against the above deficiency, the invention proposes latch enable signal processing unit in a kind of data storage type flash memory,
It enables to when signal retention time deficiency, enables signals to meet written standards by processing.
In order to realize above technical scheme, the present invention provides at latch enable signal in a kind of data storage type flash memory
Device is managed, including, the first phase inverter, the second phase inverter, third phase inverter, transmission gate, nor gate and enabled phase inverter；
Wherein, first inverter input is connected with ppu, described for receiving latch enable signal
The output end of first phase inverter is connected with the input terminal of the transmission gate；
The transmission gate includes the first control terminal and the second control terminal, is respectively connected to chip interior write enable signal and core
The negative signal of write enable signal inside piece；The first input end of the output end of the transmission gate and the nor gate and described enabled
The output end of phase inverter is connected；
Second input terminal access chip reset signal of the nor gate, the output end of the nor gate are anti-with described second
The input terminal of phase device and the enabled inverter input are connected；
The enabled phase inverter includes the first control terminal and the second control terminal, is respectively connected to chip interior write enable signal
And the negative signal of chip interior write enable signal, the output end of the enabled phase inverter and the nor gate first input end and institute
The output end for stating transmission gate is connected；
The output end of second phase inverter is connected with the input terminal of the third phase inverter, the third phase inverter it is defeated
Outlet is connected with state machine.
Further, first control terminal of transmission gate accesses the chip interior write enable signal, second control
The negative signal into the chip interior write enable signal is terminated, for controlling the opening and closing of the transmission gate.
Further, the first control terminal of enabled phase inverter access chip interior write enable signal, described second
Control terminal accesses the negative signal of the chip interior write enable signal, for controlling the opening and closing of the enabled phase inverter,
And then adjust the positive feedback between the enabled phase inverter and the nor gate.
Further, the control terminal of the transmission gate and the access of the control terminal of the enabled phase inverter are that synchronous write makes
It can signal.
Further, the latch enable signal includes address latch enable signal or the enabled letter of order latch
Number.
The present invention locks chip interior lock by the way that transmission gate and positive feedback devices is added to original chip interior control circuit
Storage enable signal.Make the latch enable signal for being latched in chip interior by way of positive feedback, overcomes chip crystal
Pipe meets the written standards that chip uses since the reduction of operating voltage causes the signal retention time insufficient.
Detailed description of the invention
Fig. 1 is the latch enable signal processing unit in a kind of data storage type flash memory provided in an embodiment of the present invention
Structure chart.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
In description, only some but not all contents related to the present invention are shown in the drawings.
Fig. 1 is the latch enable signal processing unit knot in a kind of data storage type flash memory provided in an embodiment of the present invention
Composition.As shown in Figure 1, including the first phase inverter 101, the second phase inverter 102, third phase inverter 103, transmission gate 104, nor gate
105 and enabled phase inverter 106.Wherein, 1 be chip interior write enable signal, 2 be chip interior write enable signal negative signal, 3
For chip reset signal.
Wherein, 101 input terminal of the first phase inverter is connected with ppu 100, for receiving latch enable signal, the
The output end of one phase inverter 101 is connected with the input terminal of transmission gate 104.
It is worth noting that, latch enable signal includes address latch enable signal and the enabled letter of order latch
Number, two signals can choose while send or timesharing is sent.
Transmission gate 104 includes the first control terminal and the second control terminal, is respectively connected to chip interior write enable signal 1 and core
The negative signal 2 of write enable signal inside piece；The first input end of the output end AND OR NOT gate 105 of transmission gate 104 and enabled reverse phase
The output end of device 106 is connected.
Here transmission gate 104 plays the role of a switch.Here on-off action refers to that transmission gate beats Push And Release
It closes and is controlled by external write enable signal.Due to write enable signal 1 inside the first control terminal access chip of transmission gate 104, the
Two control terminals access the negative signal 2 of external enable signal, and take logical operation between two signals.When chip interior write it is enabled
When signal is high level, transmission gate 104 is opened, and when chip interior write enable signal is low level, transmission gate 104 is closed.
When transmission gate 104 in the open state, address latch enable signal or order latch enable signal just pass
Transport to the first input end of nor gate 105.
Second input terminal access chip reset signal 3 of nor gate 105, the output end of nor gate 105 and the second phase inverter
102 input terminal and 106 input terminal of enabled phase inverter are connected.
The enabled phase inverter 106 includes the first control terminal and the second control terminal, be respectively connected to chip interior write it is enabled
The negative signal 2 of signal 1 and chip interior write enable signal, output end and the nor gate 105 first for enabling phase inverter 106 are defeated
The output end for entering end and enabled phase inverter 106 is connected.
It is worth noting that, nor gate 105 and enabled phase inverter 106 constitute jointly the signal latch of a positive feedback
Device.The latch is carried out with register enable signal or non-logical operation by access chip reset signal 3, the operation
It is intended to the register enable signal being stored in latch before removing, and then provides and deposits for this period register enable signal
Store up space.
And enabled phase inverter 106 passes through write enable signal 1 inside the first control terminal access chip, the access of the second control terminal
The negative signal 2 of chip interior write enable signal, for controlling whether positive feedback signal latch carries out register enable signal
It latches, when chip interior write enable signal is low level, register enable signal can be output to the by positive feed-back latch
Two phase inverters 102, when chip interior write enable signal is high level, register enable signal can be latched in positive feed-back latch
It is internal.
The output end of second phase inverter 102 is connected with the input terminal of the third phase inverter 103, the third reverse phase
The output end of device 103 is connected with state machine 107.
Wherein, the second phase inverter 102 with third phase inverter 103 by concatenated mode to the register enable signal of output
Shaping is carried out, and can also play the role of increasing driving.
The specific work process of latch enable signal processing unit is as follows in a kind of data storage type flash memory：
Ppu 100 issue latch enable signal (including address latch enable signal ALE and order latch
Device enable signal CLE one of both is whole), it is loaded into the input terminal of the first phase inverter 101, and export and latch to be corresponding
The reverse signal of device enable signal.
The negative letter 2 of chip interior write enable signal 1 and chip interior write enable signal be loaded into simultaneously transmission gate 104 and
The different control terminals of enabled phase inverter 106.
Wherein, the negative signal 2 of chip interior write enable signal 1 and chip interior write enable signal is loaded into transmission gate 104
The first control terminal and the second control terminal be used to control the switch of transmission gate 104, when chip interior write enable signal is high level
When, transmission gate 104 is connected；When chip interior write enable signal is low level, transmission gate 104 is closed.
The negative signal 2 of chip interior write enable signal 1 and chip interior write enable signal is loaded into enabled phase inverter 106
First control terminal and the second control terminal are applied to the signal for the positive feedback that control is made of nor gate 105 and enabled phase inverter 106
Latch.When chip interior write enable signal is high level, positive feed-back latch locks latch enable signal；When in chip
When portion's write enable signal is low level, latch enable signal is transmitted to the second reverser by positive feed-back latch.
It follows that transmission gate 104 is connected, and positive feed-back latch is lockked when chip interior write enable signal is high level
Latch enable signal, when chip interior write enable signal is low level, transmission gate 104 is closed, and positive feed-back latch will latch
Latch enable signal inside latch is discharged to the second phase inverter 102.
Second phase inverter 102 is carried out with third phase inverter 103 by register enable signal of the concatenated mode to output
Shaping, and can also play the role of increasing driving.Latch enable signal by positive feed-back latch release passes through the
Two phase inverters 102 are output in external state machine 107 after being rectified and being driven increase with third phase inverter 103.
It is noted that external state machine 107 respectively acquires signal for receiving chip interior, is handled and issued pair
Answer control command to each component part of chip interior.
Band, which is added, using nor gate both ends in the present embodiment makes the phase inverter that can control as positive feedback devices, for latching electricity
Address latch enable signal and order latch enable signal in road pass through address latch enable signal in release positive feedback
And order latch enable signal, it overcomes since the reduction of external operating voltage causes the signal retention time insufficient, is not able to satisfy
The shortcomings that chip written standards, and then improve chip operation reliability.
It is worth noting that, the above is only a preferred embodiment of the present invention, it is noted that for the art
Those of ordinary skill for, the equivalent variations made under the premise of not departing from the conceptions and principles of the principle of the invention, modification
With combination, it is within the scope of protection of the invention.
Claims (5)
1. latch enable signal processing unit in a kind of data storage type flash memory, which is characterized in that including the first phase inverter,
Two phase inverters, third phase inverter, transmission gate, nor gate and enabled phase inverter；
Wherein, first inverter input is connected with ppu, for receiving latch enable signal, described first
The output end of phase inverter is connected with the input terminal of the transmission gate；
The transmission gate includes the first control terminal and the second control terminal, is respectively connected in chip interior write enable signal and chip
The negative signal of portion's write enable signal；The first input end and the enabled reverse phase of the output end of the transmission gate and the nor gate
The output end of device is connected；
Second input terminal access chip reset signal of the nor gate, the output end of the nor gate and second phase inverter
Input terminal and the enabled inverter input be connected；
The enabled phase inverter includes the first control terminal and the second control terminal, is respectively connected to chip interior write enable signal and core
The negative signal of write enable signal, the output end of the enabled phase inverter and the nor gate first input end and the biography inside piece
The output end of defeated door is connected；
The output end of second phase inverter is connected with the input terminal of the third phase inverter, the output end of the third phase inverter
It is connected with state machine.
2. latch enable signal processing unit in data storage type flash memory according to claim 1, which is characterized in that institute
It states the first control terminal of transmission gate and accesses the chip interior write enable signal, second control terminal accesses the chip interior and writes
The negative signal of enable signal, for controlling the opening and closing of the transmission gate.
3. latch enable signal processing unit in data storage type flash memory according to claim 1, which is characterized in that institute
It states enabled the first control terminal of phase inverter and accesses the chip interior write enable signal, second control terminal accesses in the chip
The negative signal of portion's write enable signal for controlling the opening and closing of the enabled phase inverter, and then adjusts the enabled reverse phase
Positive feedback between device and the nor gate.
4. latch enable signal processing unit, feature exist in data storage type flash memory according to claim 2 or 3
In the control terminal access of the control terminal of the transmission gate and the enabled phase inverter is synchronous write enable signal.
5. latch enable signal processing unit in data storage type flash memory according to claim 1, which is characterized in that institute
Stating latch enable signal includes address latch enable signal or order latch enable signal data storage type flash memory.
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| CN204808883U (en) * | 2015-07-10 | 2015-11-25 | 北京兆易创新科技股份有限公司 | Latch enable signal processing apparatus in data storage type flash memory |
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| KR100915072B1 (en) * | 2008-01-30 | 2009-09-02 | 주식회사 하이닉스반도체 | Non-volatile latch circuit |
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