CN104965560A - High-precision and wide-current-range current mirror - Google Patents

Abstract

The invention provides a high-precision and wide-current-range current mirror. The high-precision and wide-current-range current mirror comprises a reference current input part, a current gear judgment and control logic and an image current output part. The reference current input part and the image current output part are connected with the current gear judgment and control logic. The high-precision and wide-current-range current mirror has the advantages that the current mirror capable of working in a linear area in a current gear switching mode is adopted, a current mirror circuit is improved, the VDS voltage precision is improved, accordingly, the current mirror image precision is improved, and the current mirror image range is widened.

Description

A kind of high-precision wide range of current current mirror

Technical field

The present invention relates to current mirror, particularly relate to a kind of high-precision wide range of current current mirror.

Background technology

In mimic channel, current mirror is often used to produce circuit bias electric current, load current and accurate reference current.As shown in Figure 1, current mirror used often adopts saturated pipe mirror image.Be operated in saturation region, and only consider that the source-drain current formula of the metal-oxide-semiconductor of first-order effects is such as formula shown in (1).Its μ of adjacent metal-oxide-semiconductor _n, C _oxbe all identical with VTH, known by formula (1), if VGS is identical, then the drain-source current ID of two metal-oxide-semiconductors only and W/L proportional.Electric current I 1 as shown in Figure 1 and I2 and Iref proportional.

But all there is second-order effect in metal-oxide-semiconductor, channel-length modulation.When voltage difference just between grid and leakage increases, actual inversion channel length reduces gradually.That is, when two the metal-oxide-semiconductor VGS being operated in saturation region are identical, but VDS is not identical, then in fact the inversion channel length of two metal-oxide-semiconductors is not identical, and source-drain current is not identical yet, and current mirror just exists deviation.For ensureing the mirror image precision of current mirror, need to make the metal-oxide-semiconductor drain-source voltage working in saturation region current mirror equal.So for improving current mirror precision, there is the current mirror circuit shown in Fig. 2.

But above-mentioned is all that the metal-oxide-semiconductor being operated in saturation region carries out current mirror.Metal-oxide-semiconductor is operated in the condition of saturation region such as formula shown in (3), must lower than VDS+VTH for working in saturation region VGS.Know that mirrored output current ID is larger by formula (2), required W/L is also larger, takies very large chip area.Simultaneously for guarantee works in saturation region, VDS voltage needs higher than VGS-VTH, so the current mirror circuit shown in Fig. 2 defines the drain electrode minimum voltage of current mirror outputs.Larger VDS voltage makes the current mirror working in saturation region have larger power consumption.If reduce VDS voltage, then to correspondingly reduce VGS voltage, and just need under identical source-drain current ID to increase W/L.And adopt the metal-oxide-semiconductor current mirror working in linear zone, shown in (4), VGS voltage is greater than VDS+VTH, and namely VDS can be very little.So the current mirror large to outgoing mirror image current adopts the current mirror working in linear zone can significantly reduce output power consumption.Simultaneously such as formula shown in (5), under identical source-drain current ID, VGS voltage increases can reduce W/L value, reduces chip area.But the metal-oxide-semiconductor current mirror working in linear zone needs the exact mirror image of the identical guarantee electric current of VDS voltage making metal-oxide-semiconductor.

$I_D=\frac{1}{2}{\mathrm{\μ}}_n{C}_{ox}\frac{W}{L}{(V_{GS}-V_{TH})}^2---\left(1\right)$

$I_D=\frac{1}{2}{\mathrm{\μ}}_n{C}_{ox}\frac{W}{L}{(V_{GS}-V_{TH})}^2\·(1+\mathrm{\λ}\·V_{DS})---\left(2\right)$

Metal-oxide-semiconductor is operated in the condition of saturation region:

V _GS<V _DS+V _TH(3)

Metal-oxide-semiconductor is operated in the condition of linear zone:

V _GS>V _DS+V _TH(4)

$I_D={\mathrm{\&mu;}}_n{C}_{ox}\frac{W}{L}\&lsqb;(V_{GS}-V_{TH})-\frac{1}{2}{V}_{DS}\&rsqb;V_{DS}---\left(5\right)$

And known by formula (2) and formula (5), no matter work in the current mirror of saturation region or linear zone, as long as ensure that VGS with VDS is identical, the then ratio direct proportionality of current mirror image ratio and breadth length ratio, if the input and output electric current difference of current mirror is larger, then the ratio value difference of breadth length ratio also can be comparatively large, and the larger MOS of size difference makes the coupling on domain be deteriorated, thus current mirror deterioration in accuracy.

The factor of influence working in its current mirror precision of current mirror of saturation region and linear zone is discussed below respectively.By formula (2) and formula (5) know determining source leakage current ID because have μ _n, C _ox, VTH, W/L, VGS, VDS.Wherein μ _nbe carrier mobility, determined by technique; C _oxbe the gate oxide capacitance of unit area, determined by technique; VTH is the threshold voltage of metal-oxide-semiconductor, is determined by technique, has slight change with L and underlayer voltage.W/L, VGS, VDS are circuit configuration values.μ _nand C _oxfactor is all identical to the influence degree of source-drain current ID for the current mirror of saturation region and linear zone, not by circuit design con-trol.Although it is not the influence factor of VTH is determined by technique, identical with the current mirror influence degree of linear zone to saturation region.Respectively VTH, VGS and VDS influence factor is discussed below.

VTH is on the impact of current mirror:

The metal-oxide-semiconductor source-drain current ID working in saturation region and linear zone obtains VTH differentiate respectively:

Saturation region formula: $\&part;I_D=-{\mathrm{\&mu;}}_n{C}_{ox}\frac{W}{L}(V_{GS}-V_{TH})\&part;V_{TH}---\left(6\right)$

Linear zone formula: $\&part;I_D=-{\mathrm{\&mu;}}_n{C}_{ox}\frac{W}{L}{V}_{DS}\&part;V_{TH}---\left(7\right)$

Accounting:

Saturation region: $\frac{\&part;I_D}{I_D}=\frac{\&part;V_{TH}}{\frac{1}{2}(V_{GS}-V_{TH})}=\frac{\&part;V_{TH}/V_{TH}}{\frac{1}{2}(\frac{V_{GS}}{V_{TH}}-1)}---\left(8\right)$

Linear zone: $\frac{\&part;I_D}{I_D}=\frac{\&part;V_{TH}}{(V_{GS}-V_{TH})-\frac{1}{2}{V}_{DS}}=\frac{\&part;V_{TH}/V_{TH}}{\left(\frac{V_{GS}}{V_{TH}}-1\right)-\frac{1}{2}\frac{V_{DS}}{V_{TH}}}---\left(9\right)$

Due to saturation region VGS-VTH<VDS, and at linear zone VGS-VTH>VDS.Therefore have:

Saturation region: $\frac{1}{2}(\frac{V_{GS}}{V_{TH}}-1)<\frac{1}{2}\frac{V_{DS}}{V_{TH}}---\left(10\right)$

Linear zone: $(\frac{V_{GS}}{V_{TH}}-1)>\frac{V_{DS}}{V_{TH}}\&DoubleRightArrow;(\frac{V_{GS}}{V_{TH}}-1)-\frac{1}{2}\frac{V_{DS}}{V_{TH}}>\frac{1}{2}\frac{V_{DS}}{V_{TH}}---\left(11\right)$

So, cause source-drain current ID accounting to change in linear zone VTH change and be less than the change causing electric current I D at saturation region VTH.

Although the VTH deviation of the NMOS of same chip is less, but still can there is deviation.So the current mirror being operated in linear zone can improve current precision.Particularly for the current mirror that current mirror ratio value is larger, the current mirror working in linear zone affects less by the VTH of technique.

VGS is on the impact of current mirror:

Formula (2) and formula (5) obtain VGS differentiate respectively:

Saturation region formula: $\&part;I_D={\mathrm{\&mu;}}_n{C}_{ox}\frac{W}{L}(V_{GS}-V_{TH})\&part;V_{GS}---\left(12\right)$

Linear zone formula: $\&part;I_D={\mathrm{\&mu;}}_n{C}_{ox}\frac{W}{L}{V}_{DS}\&part;V_{GS}---\left(13\right)$

Accounting:

Saturation region: $\frac{\&part;I_D}{I_D}=\frac{\&part;V_{GS}}{\frac{1}{2}(V_{GS}-V_{TH})}=\frac{\&part;V_{GS}/V_{GS}}{\frac{\frac{1}{2}(V_{GS}-V_{TH})}{V_{GS}}}---\left(14\right)$

Linear zone: $\frac{\&part;I_D}{I_D}=\frac{\&part;V_{GS}}{(V_{GS}-V_{TH})-\frac{1}{2}{V}_{DS}}=\frac{\&part;V_{GS}/V_{GS}}{\frac{(V_{GS}-V_{TH})-\frac{1}{2}{V}_{DS}}{V_{GS}}}---\left(15\right)$

Same by saturation region VGS-VTH<VDS, linear zone VGS-VTH>VDS formula obtains:

Saturation region: $\frac{1}{2}(V_{GS}-V_{TH})<\frac{1}{2}{V}_{DS}---\left(16\right)$

Linear zone: $(V_{GS}-V_{TH})-\frac{1}{2}{V}_{DS}>\frac{1}{2}{V}_{DS}---\left(17\right)$

So the current change quantity caused by the VGS change in voltage of linear zone is less than work in saturation region.And VGS voltage is higher, the current deviation caused by VGS deviation is less.Improve VGS and can improve current mirror precision.

The grid voltage that VGS voltage deviation appears at input and output pipe in current mirror does not directly connect but connects by OP buffering is rear, as shown in the figure.The positioned ground terminal voltage of NMOS tube unanimously also can cause the source voltage terminal of MOS different simultaneously, causes VGS in current mirror not identical.

VDS is on the impact of current mirror:

Saturation region:

$\frac{\&part;I_D}{I_D}=\mathrm{\&lambda;}\&CenterDot;\frac{\&part;V_{DS}}{V_{DS}}---\left(18\right)$

Linear zone: $\frac{\&part;I_D}{I_D}=\frac{(V_{GS}-V_{TH})-V_{DS}}{(V_{GS}-V_{TH})-\frac{1}{2}{V}_{DS}}\frac{\&part;V_{DS}}{{\&part;}_{DS}}=(1-\frac{1}{2\frac{(V_{GS}-V_{TH})}{V_{DS}}-1})\frac{\&part;V_{DS}}{V_{DS}}---\left(19\right)$

The channel-modulation parameter λ of saturation region is very little, and much smaller than 1, longer λ is less for raceway groove.

VGS-VTH>VDS in linear zone, wherein VGS is larger, and the coefficient in formula (19) is more close to 1.So:

$(1-\frac{1}{2\frac{(V_{GS}-V_{TH})}{V_{DS}}-1})>\mathrm{\&lambda;}\left(20\right)$

In sum, the current mirror that the current mirror precision working in the current mirror of saturation region works in linear zone relatively is more subject to the impact of VTH and VGS factor, is more subject to the impact of technique and domain coupling.And the impact of current mirror on technique and domain coupling working in linear zone is less, but larger by VDS voltage variations affect.So improving the top priority working in the current mirror precision of the current mirror of linear zone is ensure that the VDS voltage of current mirror input and output pipe is as far as possible equal.

Application number be 201010238706.3 Chinese patent " a kind of adaptive current mirror " propose a kind of current mirror method working in the automatic switchover electric current gear of linear zone, as shown in Figure 3, NM1-NM4 is current reference pipe, NM5-NM8, NM8-12 is respectively two groups of current mirror efferent ducts, adopt common gate to be connected between current reference pipe with current mirror efferent duct, and gear switch switch is placed on the drain interconnection of metal-oxide-semiconductor, as shown in the SW1-9 in Fig. 3.Current mirror adopts the metal-oxide-semiconductor working in linear zone to carry out current mirror, and the effect of AMP1-3 is the VDS voltage of the metal-oxide-semiconductor limiting NM1-NM12, allows it equal reference voltage Vref, realizes current mirror.μ when because being known same process by formula (4) _n, C _ox, VTH parameter is identical, circuit makes VGS with VDS of metal-oxide-semiconductor identical, then the ratio of the drain-source current of metal-oxide-semiconductor equals the ratio of breadth length ratio.Known by linear zone drain-source current formula (4) simultaneously, under VDS mono-stable condition, the VGS voltage response size of drain-source current ID (being Iref in circuit), by judging VGS voltage, judge the size of electric current, thus switch corresponding interrupteur SW 1-9 action, realize electric current gear switch.

This current mirror adopts the metal-oxide-semiconductor working in linear zone to carry out current mirror, the minimum voltage of current mirror outputs can be effectively reduced, current mirror precision can also be improved by switch current gear when larger current mirror image simultaneously, thus extend current mirror scope.But this current mirror is Shortcomings part still, be that the drain terminal that its gear switch interrupteur SW 1-9 is placed on MOS interconnects.Can be known by formula (4), be operated in the metal-oxide-semiconductor of linear zone, its drain-source current ID and VDS becomes second order relation, and its drain-source voltage of the metal-oxide-semiconductor VDS being namely operated in linear zone changes a bit, and its drain-source current ID has greatly changed.Because interrupteur SW exists internal resistance, when the switch is closed, electric current flows through switch and partially can produce pressure drop Δ V.If interrupteur SW impedance is R, then the VDS voltage on NM6 equals Vref-R* (I1+I2+I3).Vref is generally hundreds of mV, and I1+I2+I3 generally has tens mA, if interrupteur SW impedance R exists the impedance (NMOS tube area is about 50um*100um) of 1 ohm, the VDS voltage of NM6 is produced to the impact of tens mV (about 10%).Therefore the VDS voltage pole earth effect of interrupteur SW to NM6 the precision of output current.In addition in the IC of CMOS technology, interrupteur SW generally adopts metal-oxide-semiconductor to realize, if want, the internal resistance reducing interrupteur SW is to reduce the impact of output current precision, then need the metal-oxide-semiconductor area significantly increasing interrupteur SW, and the number of interrupteur SW more time, chip area shared by interrupteur SW is very big, even exceedes the chip area of circuit itself.So the current mirror in Fig. 3 have output current larger time mirror image low precision, and the shortcoming that chip area is large, causes this current mirroring circuit not have using value.

In the constant current driver circuit for LED that existing hyperchannel exports, the input current passing ratio current mirror that its output current size is produced by a plug-in resistance produces, and output current size and precision affect by proportional current mirror.And the current mirror output voltage being operated in saturation region in prior art requires higher, power consumption is comparatively large, and chip area is also larger.And be operated in the current mirror of linear zone, cause current precision to be lost due to VDS voltage deviation, the especially current mirror deterioration in accuracy of High-current output, so the current mirror being operated in linear zone keeps high-precision working range limited.And known by formula (5), current mirror such as W/L and VDS being operated in linear zone remains unchanged, then image current ID and VGS is directly proportional, and when namely ID becomes large, VGS also can become large.But VGS is maximum can only reach supply voltage VDD.Therefore make greatly VGS change greatly reduce close to the current mirror ability of current mirror during VDD greatly when ID becomes, current mirror ability accurately cannot be provided.Common solution adopts to switch W/L size, when ID is excessive, when making VGS close to VDD, increases the W/L value of current mirror, thus reduce VGS voltage, namely arrange current mirror gear.And the method increasing the W/L value of current mirror normally adopts the mode of MOS switch and accesses more metal-oxide-semiconductor.Therefore for meeting different output current demands, its usual way is that chip has electric current gear handoff functionality, can according to the size automatic switchover internal current mirror work number of output current, to ensure that output current can keep degree of precision.But existing automatic switchover current mirror technique still existing defects and needs is improved in place.For improving current mirror precision further, widening current mirror scope, reducing the chip area of circuit, propose the present invention.

Summary of the invention

For realizing lower output voltage, high current mirror precision, wide current mirror scope and as far as possible little chip area, the invention provides a kind of high-precision wide range of current current mirror, employing can the current mirror working in linear zone of electric current gear switch, by improving current mirroring circuit, improve VDS voltage accuracy, thus improve current mirror precision, widen current mirror scope.

The invention provides a kind of high-precision wide range of current current mirror, comprise reference current importation, electric current gear judges and steering logic, image current output; Described reference current importation, image current output judge to be connected with steering logic with described electric current gear respectively.

As a further improvement on the present invention, described reference current importation comprises current mirror transistor and operational amplifier A MP1, and wherein, described current mirror transistor comprises base transistor NM0 and redundancy transistor NM1, redundancy transistor NM2, redundancy transistor NM3, base transistor NM0 and redundancy transistor NM1, redundancy transistor NM2, the drain interconnection of redundancy transistor NM3 receives reference current Iref, base transistor NM0 and redundancy transistor NM1, redundancy transistor NM2, the Source interconnect ground connection of redundancy transistor NM3, the grid of redundancy transistor NM1 is provided with interrupteur SW 10, and the grid of redundancy transistor NM2 is provided with interrupteur SW 20, and the grid of redundancy transistor NM3 is provided with interrupteur SW 30, interrupteur SW 10, interrupteur SW 20, interrupteur SW 30 is by redundancy transistor NM1, redundancy transistor NM2, the grid of redundancy transistor NM3 switches ground connection or connects the grid of base transistor NM1, redundancy transistor NM1, redundancy transistor NM2, the switch controlling signal of redundancy transistor NM3 is followed successively by interrupteur SW ITCH1, interrupteur SW ITCH2, interrupteur SW ITCH3, the negative input termination reference voltage Vref of operational amplifier A MP1, the public drain terminal of the positive input termination current mirror transistor of operational amplifier A MP1, the grid of the output termination base transistor NM0 of operational amplifier A MP1, the effect of reference current importation is to provide VDS voltage and the VGS voltage of image current output.

As a further improvement on the present invention, described redundancy transistor NM1 judges to be connected with steering logic with described electric current gear by interrupteur SW ITCH1, described redundancy transistor NM2 judges to be connected with steering logic with described electric current gear by interrupteur SW ITCH2, and described redundancy transistor NM3 judges to be connected with steering logic with described electric current gear by interrupteur SW ITCH3.

As a further improvement on the present invention, the output terminal of described calculation amplifier AMP1 judges to be connected with steering logic with described electric current gear.

As a further improvement on the present invention, image current output comprises current switch part and current mirror part, current switch part comprises operational amplifier A MP2 and switching tube NM8, wherein current mirror part comprises base transistor NM4 and redundancy transistor NM5, redundancy transistor NM6, redundancy transistor NM7, base transistor NM4 and redundancy transistor NM5, redundancy transistor NM6, the drain interconnection of redundancy transistor NM7 receives the source electrode of switching tube NM8, base transistor NM4 and redundancy transistor NM5, redundancy transistor NM6, the Source interconnect ground connection of redundancy transistor NM7, the grid of redundancy transistor NM5 is provided with interrupteur SW 11, the grid of redundancy transistor NM6 is provided with interrupteur SW 21, the grid of redundancy transistor NM7 is provided with interrupteur SW 31, interrupteur SW 11, interrupteur SW 21, interrupteur SW 31 is by redundancy transistor NM5, redundancy transistor NM6, the grid of redundancy transistor NM7 switches ground connection or connects the grid of base transistor NM0, the grid of base transistor NM4 receives the grid of base transistor NM0, operational amplifier A MP2 positive input terminal receives the drain electrode of base transistor NM0, the source electrode of the negative input termination switching tube NM8 of operational amplifier A MP2, the output terminal of operational amplifier A MP2 receives the grid of switching tube NM8, the drain electrode of switching tube NM8 is received electric current and is exported Iout1, the effect of image current output be the VGS voltage and VDS voltage mirror that are formed on transistor according to the input current of reference current importation on base transistor NM4, redundancy transistor NM5, redundancy transistor NM6, redundancy transistor NM7, form output current Iout1.

As a further improvement on the present invention, described electric current gear judges to hold with the VG of steering logic the output terminal receiving operational amplifier A MP1,: described electric current gear judges that the output with steering logic connects the control end of interrupteur SW 10, interrupteur SW 11 through interrupteur SW ITCH1, described electric current gear judges that the output with steering logic connects the control end of interrupteur SW 20, interrupteur SW 21 through interrupteur SW ITCH2, and described electric current gear judges that the output with steering logic connects the control end of interrupteur SW 30, interrupteur SW 31 through interrupteur SW ITCH3.

As a further improvement on the present invention, described electric current gear judges to control according to the size of VG voltage the number opening redundancy transistor with steering logic, and then realizes the switching of electric current gear.

As a further improvement on the present invention, described electric current gear judges that comprising electric current gear with steering logic judges comparer COMP1, electric current gear judges comparer COMP2, logic gate device U1, logic gate device U2, logic gate device U3, logic gate device U4, logic gate device U5, logic gate device U6, logic gate device U7, logic gate device U8, logic gate device U9, logic gate device U10, logic gate device U11, logic gate device U12, logic gate device U13 and trigger D1, trigger D2, trigger D3, electric current gear judges the negative input termination reference voltage Vref h of comparer COMP1, electric current gear judges the grid of the positive input termination base transistor NM1 of comparer COMP1, and electric current gear judges that the output Vgh of comparer COMP1 receives logic gate device U7 respectively, logic gate device U10, the input end of logic gate device U13, electric current gear judges the negative input termination reference voltage Vref l of comparer COMP2, electric current gear judges the grid of the positive input termination base transistor of comparer COMP2, and electric current gear judges that the output Vgl of comparer COMP2 receives logic gate device U5 respectively, logic gate device U8, the input end of logic gate device U11.

As a further improvement on the present invention, the qb end of an input contact hair device D1 of described logic gate device U1, the q end of another input contact of described logic gate device U1 hair device D2; The qb end of an input contact hair device D2 of described logic gate device U2, the q end of another input contact hair device D3 of described logic gate device U2; The output of logic gate device U1, logic gate device U2 and reset signal REST receive the input end of logic gate device U3 respectively; The input end of logic gate device U4 is received in the output of logic gate device U3, and the reset terminal r of trigger D1, trigger D2 and trigger D3 is received in the output of logic gate device U4; Described logic gate device U5 two input ends, the output that electric current gear judges comparer COMP2 is received in an input, and another receives the q end of trigger D1; Three input ends of described logic gate device U6 are the output of logic gate device U5; The output of logic gate device U7 and the qb end of trigger D2, the d exported as trigger D1 holds; Logic gate device U8 two input ends are the q end that electric current gear judges comparer COMP2 output terminal and trigger D2; Logic gate device U10 input end is that the q end of trigger D1 and electric current gear judge the output terminal of comparer COMP1; Logic gate device U9 input end is the qb end of logic gate device U8 output terminal, logic gate device U10 output terminal and trigger D3, and the input d that logic gate device U9 outputs to trigger D2 holds; Logic gate device U11 two input end is the q end that electric current gear judges comparer COMP2 output terminal and trigger D3; Logic gate device U13 tri-input ends are the q end of trigger D2, the q end of trigger D1 and electric current gear judge the output terminal of comparer COMP1; Logic gate device U12 two is input as the output terminal of logic gate device U11 and logic gate device U13, and the D end of trigger D3 is received in the output of logic gate device U12; The r end of trigger D1, trigger D2, trigger D3 is connected to logic gate device U4 and exports; The CK of trigger D3 holds short circuit to be connected to clock signal clk, the q terminating logic gate device U6 of trigger D1 exports, the q terminating logic gate device U9 of trigger D2 exports, the q terminating logic gate device U12 of trigger D3 exports, and the qb end difference output current gear of trigger D1, trigger D2, trigger D3 judges and interrupteur SW ITCH1, the interrupteur SW ITCH2 of steering logic, interrupteur SW ITCH3 signal; Electric current gear judges it is the size according to Vg voltage with the effect of steering logic, VGH and VGL pulse is produced by comparing with Vrefh and Vrefl, produce interrupteur SW ITCH1, interrupteur SW ITCH2, interrupteur SW ITCH3 switching signal, control conducting and the cut-off of alternative transistor.

As a further improvement on the present invention, described image current output has two at least.

The invention has the beneficial effects as follows: by such scheme, adopting can the current mirror working in linear zone of electric current gear switch, by improving current mirroring circuit, improves VDS voltage accuracy, thus improves current mirror precision, widen current mirror scope.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of conventional current mirror in prior art.

Fig. 2 is conventional current mirror image circuit figure in prior art.

Fig. 3 is the circuit diagram of conventional current mirror in prior art.

Fig. 4 is the circuit diagram of a kind of high-precision wide range of current of the present invention current mirror.

Fig. 5 is the circuit diagram of a kind of high-precision wide range of current of the present invention current mirror.

Embodiment

Illustrate below in conjunction with accompanying drawing and embodiment the present invention is further described.

For realizing lower output voltage, high current mirror precision, wide current mirror scope and as far as possible little chip area, the present invention adopts can the current mirror working in linear zone of electric current gear switch, by improving current mirroring circuit, improve VDS voltage accuracy, thus improve current mirror precision, widen current mirror scope.

Embodiment 1.

If Fig. 4 is as shown, a kind of high-precision wide range of current current mirror, the current mirror of described switchable current gear comprises reference current importation I1, electric current gear judges and steering logic I3 and image current output I2.

As shown in Figure 4, reference current importation I1 comprises current mirror transistor and operational amplifier A MP1, and wherein current mirror transistor comprises base transistor NM0 and redundancy transistor NM1, redundancy transistor NM2, redundancy transistor NM3, base transistor NM0 and redundancy transistor NM1, redundancy transistor NM2, the drain interconnection of redundancy transistor NM3 receives reference current Iref, base transistor NM0 and redundancy transistor NM1, redundancy transistor NM2, the Source interconnect ground connection of redundancy transistor NM3, redundancy transistor NM1, redundancy transistor NM2, the grid of redundancy transistor NM3 is provided with interrupteur SW 10, interrupteur SW 20, interrupteur SW 30, SW10, interrupteur SW 20, interrupteur SW 30 will use transistor NM1 in certain sequence, redundancy transistor NM2, the grid of redundancy transistor NM3 switches ground connection or connects the grid of base transistor NM1, uses transistor NM1, redundancy transistor NM2, redundancy transistor NM3 switch controlling signal is followed successively by interrupteur SW ITCH1, interrupteur SW ITCH2, interrupteur SW ITCH3, the negative input termination reference voltage Vref of operational amplifier A MP1, the public drain terminal of positive input termination current mirror transistor, the output of operational amplifier A MP1 connects the grid of base transistor NM0.The effect of reference current importation is to provide VDS voltage and the VGS voltage of image current pipe.

As shown in Figure 4, image current output I2 is divided into current switch part I4 and current mirror part I5 current switch part I4 to form primarily of operational amplifier A MP2 and switching tube NM8, wherein, current mirror part I5 comprises base transistor NM4 and redundancy transistor NM5, redundancy transistor NM6, redundancy transistor NM7, interrupteur SW 11, interrupteur SW 21, interrupteur SW 31, base transistor NM4 and redundancy transistor NM5, redundancy transistor NM6, the drain interconnection of redundancy transistor NM7 receives the source electrode of switching tube NM8, base transistor NM4 and redundancy transistor NM5, redundancy transistor NM6, the Source interconnect ground connection of redundancy transistor NM7, redundancy transistor NM5, redundancy transistor NM6, the grid of redundancy transistor NM7 is provided with interrupteur SW 11, interrupteur SW 21, interrupteur SW 31, interrupteur SW 11, interrupteur SW 21, interrupteur SW 31 is in certain sequence by redundancy transistor NM5, redundancy transistor NM6, the grid of redundancy transistor NM7 switches ground connection or connects the grid of base transistor NM0, and the grid of base transistor NM4 receives the grid of base transistor NM0, the positive input terminal of operational amplifier A MP2 is received base transistor NM0 and is drained, the source electrode of the negative input termination switching tube NM8 of operational amplifier A MP2, the output terminal of operational amplifier A MP2 receives the grid of switch NM8, and the drain electrode of switch NM8 is received electric current and exported Iout1.The effect of image current output I2 is that VGS and the VDS voltage mirror formed on transistor according to the input current of reference current importation I1 arrives, on base transistor NM4 and redundancy transistor NM5, redundancy transistor NM6, redundancy transistor NM7, form output current Iout1.

As shown in Figure 4, electric current gear judges and steering logic I3, its effect is the number opening redundancy transistor according to the size of VG voltage, and then realize the switching of electric current gear, electric current gear judges to hold the output of receiving operational amplifier A MP1 with the VG of steering logic I3, output switch SWITCH1 connects the control end of interrupteur SW 10, interrupteur SW 11, and output switch SWITCH2 connects the control end of interrupteur SW 20, interrupteur SW 21, and output switch SWITCH3 connects the control end of interrupteur SW 30, interrupteur SW 31.

As shown in Figure 4, the main improvement of this technical scheme by the position of switching tube by controlling opening and closedown of drain voltage, change to and switch opening and closedown of grid voltage, to realize the done with high accuracy method of current mirror, this is because the realization of SW in the electronic circuit as shown in figure 3 is generally realized by transistor, because SW exists conducting resistance Rdson and the impact by big current, this can make VDS voltage can reduce gradually in the process of mirror image, VDS voltage is less simultaneously, make this pressure drop proportion larger, have a strong impact on current mirror precision, simultaneously in order to reduce conducting resistance, SW area occupied can be made larger, waste chip area, SW adopts the structure of series connection simultaneously, can along with the increase of progression, VDS declines more, precision is lower.In the mode that the present invention realizes, realized by the break-make of control gate voltage, grid does not have electric current process, SW pressure drop is lower, and pressure drop and conducting resistance have nothing to do, so SW area does not need to do greatly, save area, therefore adopt this programme both to save area, the current precision greatly improved again, progression can increase arbitrarily simultaneously, improves the width of range of current.

Embodiment 2.

If Fig. 5 is as shown, it is a kind of that high-precision wide range of current current mirror comprises reference current importation I1, electric current gear judges and steering logic I8 and several image current outputs I2, image current output I2 is preferably multiple, the present embodiment is described for two, be respectively, image current output I2 and image current output I20.

If Fig. 5 is as shown, reference current importation I1 comprises current mirror transistor and operational amplifier A MP1, and wherein current mirror transistor comprises base transistor NM1 and redundancy transistor NM2, redundancy transistor NM3, redundancy transistor NM4, base transistor NM1 and redundancy transistor NM2, redundancy transistor NM3, the drain interconnection of redundancy transistor NM4 receives reference current Iref, base transistor NM1 and redundancy transistor NM2, redundancy transistor NM3, the Source interconnect ground connection of redundancy transistor NM4, redundancy transistor NM2, redundancy transistor NM3, the grid of redundancy transistor NM4 is provided with interrupteur SW 10, interrupteur SW 20, interrupteur SW 30, interrupteur SW 10, interrupteur SW 20, interrupteur SW 30 is in certain sequence by redundancy transistor NM2, redundancy transistor NM3, the grid of redundancy transistor NM4 switches ground connection or connects the grid of base transistor NM1, redundancy transistor NM2, redundancy transistor NM3, redundancy transistor NM4 switch controlling signal is followed successively by interrupteur SW 1 (the qb end of D1), interrupteur SW 2 (the qb end of D2), interrupteur SW 3 (the qb end of D3).The negative input termination reference voltage Vref of operational amplifier A MP1, the public drain terminal of the positive input termination current mirror transistor of operational amplifier A MP1, the output of operational amplifier A MP1 connects the grid of base transistor NM1.The effect of this module be by the voltage of the clamped VDS of the characteristic of amplifier on Vref, force the drain electrode of input circuit unit and output circuit unit all crystals pipe have identical voltage and be operated in linear zone, produce gate bias voltage Vg according to the size of electric current I out simultaneously.

If Fig. 5 is as shown, electric current gear judges to comprise that two electric current gears judge comparer COMP1, electric current gear judges comparer COMP2, logic gate device U1, logic gate device U2, logic gate device U3, logic gate device U4, logic gate device U5, logic gate device U6, logic gate device U7, logic gate device U8, logic gate device U9, logic gate device U10, logic gate device U11, logic gate device U12, logic gate device U13 and trigger D1, trigger D2, trigger D3 with steering logic I8.

If Fig. 5 is as shown, electric current gear judges the negative input termination reference voltage Vref h of comparer COMP1, electric current gear judges the grid of the positive input termination base transistor NM1 of comparer COMP1, exports the input end that Vgh receives logic gate device U7, logic gate device U10, logic gate device U13 respectively.

If Fig. 5 is as shown, electric current gear judges the negative input termination reference voltage Vref l of comparer COMP2, electric current gear judges the grid of the positive input termination base transistor NM1 of comparer COMP2, exports the input end that Vgl receives logic gate device U5, logic gate device U8, logic gate device U11 respectively.

If Fig. 5 is as shown, the qb end of an input contact hair device D1 of logic gate device U1, the q end of another input contact hair device D2.The qb end of an input contact hair device D2 of logic gate device U2, the q end of another input contact hair device D3.

If Fig. 5 is as shown, the output of logic gate device U1, logic gate device U2 and reset signal REST receive the input end of logic gate device U3 respectively, the input end of logic gate device U4 is received in the output of logic gate device U3, and the reset terminal r of trigger D1, trigger D2 and trigger D3 is received in the output of logic gate device U4.

If Fig. 5 is as shown, logic gate device U5 two input ends, the output that electric current gear judges comparer COMP2 is received in an input, and a q receiving trigger D1 holds.

If Fig. 5 is as shown, three input ends of logic gate device U6 are the output of logic gate device U5, and the output of logic gate device U7 and the qb end of trigger D2, the d exported as trigger D1 holds.

If Fig. 5 is as shown, logic gate device U8 two input ends are the q end that electric current gear judges comparer COMP2 output terminal and trigger D2.

If Fig. 5 is as shown, logic gate device U10 input end is that the q end of trigger D1 and electric current gear judge the output terminal of comparer COMP1.

If Fig. 5 is as shown, logic gate device U9 input end is the qb end of logic gate device U8 output terminal, logic gate device U10 output terminal and trigger D3, and the input d outputting to trigger D2 holds.

If Fig. 5 is as shown, logic gate device U11 two input end is the q end that electric current gear judges comparer COMP2 output terminal and trigger D3.

If Fig. 5 is as shown, logic gate device U13 tri-input ends are the q end of trigger D2, the q end of trigger D1 and electric current gear judge the output terminal of comparer COMP1.

If Fig. 5 is as shown, logic gate device U12 two is input as the output terminal of logic gate device U11 and logic gate device U13, and the D end of trigger D3 is received in the output of logic gate device U12.

If Fig. 5 is as shown, the r end of trigger D1, trigger D2, trigger D3 is connected to logic gate device U4 and exports, the CK of trigger D3 holds short circuit to be connected to clock signal clk, the q terminating logic gate device U6 of trigger D1 exports, the q terminating logic gate device U9 of trigger D2 exports, the q terminating logic gate device U12 of trigger D3 exports, and it is interrupteur SW 1, interrupteur SW 2, interrupteur SW 3 signal that the qb end of trigger D1, trigger D2, trigger D3 exports this module respectively.The effect of this module is the size according to Vg voltage, produces VGH and VGL pulse by comparing with Vrefh and Vrefl, produces SW1, SW2, SW3 switching signal, controls conducting and the cut-off of alternative transistor.

If Fig. 5 is as shown, image current output I2 is divided into current switch part I4 and current mirror part I5, current switch part I4 forms primarily of operational amplifier A MP2 and switching tube NM13, wherein current mirror part I5 comprises base transistor NM5 and redundancy transistor NM6, redundancy transistor NM7, redundancy transistor NM8, interrupteur SW 11, interrupteur SW 21, interrupteur SW 31, base transistor NM5 and redundancy transistor NM6, redundancy transistor NM7, the drain interconnection of redundancy transistor NM8 receives the source electrode of switching tube NM13, base transistor NM5 and redundancy transistor NM6, redundancy transistor NM7, the Source interconnect ground connection of redundancy transistor NM8, redundancy transistor NM6, redundancy transistor NM7, the grid of redundancy transistor NM8 is provided with interrupteur SW 11, interrupteur SW 21, interrupteur SW 31, interrupteur SW 11, interrupteur SW 21, interrupteur SW 31 is in certain sequence by redundancy transistor NM6, redundancy transistor NM7, the grid of redundancy transistor NM8 switches ground connection or connects the grid of base transistor NM1.

If Fig. 5 is as shown, the grid of base transistor NM5 receives the grid of base transistor NM1; Operational amplifier A MP2 positive input terminal is received base transistor NM1 and is drained, the source electrode of operational amplifier A MP2 negative input termination switching tube NM13, and operational amplifier A MP2 output terminal receives the grid of switching tube NM13, and switching tube NM13 drain electrode is received electric current and exported Iout1.

If Fig. 5 is as shown, image current output I20 is another output of image current, be divided into current switch part I6 and current mirror part I7, current switch part I6 forms primarily of operational amplifier A MP3 and switching tube NM14, and wherein current mirror part I7 comprises base transistor NM9 and redundancy transistor NM10, redundancy transistor NM11, redundancy transistor NM12, interrupteur SW 12, interrupteur SW 22, interrupteur SW 32, base transistor NM9 and redundancy transistor NM10, redundancy transistor NM11, the drain interconnection of redundancy transistor NM12 receives the source electrode of switching tube NM14, base transistor NM9 and redundancy transistor NM10, redundancy transistor NM11, the Source interconnect ground connection of redundancy transistor NM12, redundancy transistor NM10, redundancy transistor NM11, the grid of redundancy transistor NM12 is provided with interrupteur SW 12, interrupteur SW 22, interrupteur SW 32, interrupteur SW 12, interrupteur SW 22, interrupteur SW 32 is in certain sequence by redundancy transistor NM10, redundancy transistor NM11, the grid of redundancy transistor NM12 switches ground connection or connects the grid of base transistor NM1, and the grid of base transistor NM9 receives the grid of base transistor NM1, operational amplifier A MP3 positive input terminal is received base transistor NM1 and is drained, and operational amplifier A MP3 negative terminal connects the source electrode of switching tube NM14, and operational amplifier A MP3 output terminal receives the grid of switching tube NM14, and switching tube NM14 drain electrode is received electric current and exported Iout2.The effect of image current output I2 and image current output I20 is image current output, and the mirror image realizing electric current according to electric current gear judges and steering logic I8 produces interrupteur SW 1, interrupteur SW 2, interrupteur SW 3 signal and VDS, VGS voltage exports.

As shown in Figure 5, circuital current mirror image pipe VDS voltage is by the mode of Vref and operational amplifier A MP1 by voltage clamping, and embedding firmly VDS voltage is at Vref, and make transistor be in linear zone, size of current is relevant with the size of VGS voltage.Assumed initial state is all switch ground connection, when Iref electric current is come in time, if Iref electric current is excessive, then Vg voltage can be very high, comparer COMP1 and electric current gear judge that comparer COMP2 exports high level to cause electric current gear to judge, at this time internal logic makes interrupteur SW 3 first reverse, at this time interrupteur SW 30, interrupteur SW 31, interrupteur SW 32 makes redundancy transistor grid connect Vg voltage, declined along with the access of redundancy transistor by the known Vg voltage of formula (5), if at this time Vg voltage is still very high, the basis then can reversed in interrupteur SW 3 continues interrupteur SW 2 is reversed, until Vg voltage stabilization is also opened in suitable value or interrupteur SW 1.

If Fig. 5 is as shown, if time Iref electric current is less, then Vg is less, VGH, VGL are low level, make interrupteur SW 1, interrupteur SW 2, interrupteur SW 3 be in steady state (SS), do not need to open too much redundancy transistor under this state.

If Fig. 5 is as shown, image current output is then according to number and the drain voltage of switch, and the mirror image that gate bias voltage size realizes electric current exports.

If Fig. 5 is as shown, the program has widened range of current greatly, and voltage detection module adjusts Vg voltage and switch number automatically, adopts grid-controlled method, improves current precision, save chip area.

A kind of high-precision wide range of current current mirror provided by the invention, by changing the control position of current mirror image tube, SW changes control gate voltage into realize the break-make of current mirror image tube by controlling to drain, eliminate the impact of SW conducting resistance, reduce the impact of VDS and VGS on electric current, further increase current mirror precision, widen current mirror scope, reduce the chip area of circuit.

Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should be considered as belonging to protection scope of the present invention.

Claims (10)

1. a high-precision wide range of current current mirror, is characterized in that: comprise reference current importation, electric current gear judges and steering logic, image current output; Described reference current importation, image current output judge to be connected with steering logic with described electric current gear respectively.

2. high-precision wide range of current current mirror according to claim 1, it is characterized in that: described reference current importation comprises current mirror transistor and operational amplifier A MP1, wherein, described current mirror transistor comprises base transistor NM0 and redundancy transistor NM1, redundancy transistor NM2, redundancy transistor NM3, base transistor NM0 and redundancy transistor NM1, redundancy transistor NM2, the drain interconnection of redundancy transistor NM3 receives reference current Iref, base transistor NM0 and redundancy transistor NM1, redundancy transistor NM2, the Source interconnect ground connection of redundancy transistor NM3, the grid of redundancy transistor NM1 is provided with interrupteur SW 10, the grid of redundancy transistor NM2 is provided with interrupteur SW 20, the grid of redundancy transistor NM3 is provided with interrupteur SW 30, interrupteur SW 10, interrupteur SW 20, interrupteur SW 30 is by redundancy transistor NM1, redundancy transistor NM2, the grid of redundancy transistor NM3 switches ground connection or connects the grid of base transistor NM1, redundancy transistor NM1, redundancy transistor NM2, the switch controlling signal of redundancy transistor NM3 is followed successively by interrupteur SW ITCH1, interrupteur SW ITCH2, interrupteur SW ITCH3, the negative input termination reference voltage Vref of operational amplifier A MP1, the public drain terminal of the positive input termination current mirror transistor of operational amplifier A MP1, the grid of the output termination base transistor NM0 of operational amplifier A MP1, the effect of reference current importation is to provide VDS voltage and the VGS voltage of image current output.

3. high-precision wide range of current current mirror according to claim 2, it is characterized in that: described redundancy transistor NM1 judges to be connected with steering logic with described electric current gear by interrupteur SW ITCH1, described redundancy transistor NM2 judges to be connected with steering logic with described electric current gear by interrupteur SW ITCH2, and described redundancy transistor NM3 judges to be connected with steering logic with described electric current gear by interrupteur SW ITCH3.

4. high-precision wide range of current current mirror according to claim 2, is characterized in that: the output terminal of described calculation amplifier AMP1 judges to be connected with steering logic with described electric current gear.

5. high-precision wide range of current current mirror according to claim 2, it is characterized in that: image current output comprises current switch part and current mirror part, current switch part comprises operational amplifier A MP2 and switching tube NM8, wherein current mirror part comprises base transistor NM4 and redundancy transistor NM5, redundancy transistor NM6, redundancy transistor NM7, base transistor NM4 and redundancy transistor NM5, redundancy transistor NM6, the drain interconnection of redundancy transistor NM7 receives the source electrode of switching tube NM8, base transistor NM4 and redundancy transistor NM5, redundancy transistor NM6, the Source interconnect ground connection of redundancy transistor NM7, the grid of redundancy transistor NM5 is provided with interrupteur SW 11, the grid of redundancy transistor NM6 is provided with interrupteur SW 21, the grid of redundancy transistor NM7 is provided with interrupteur SW 31, interrupteur SW 11, interrupteur SW 21, interrupteur SW 31 is by redundancy transistor NM5, redundancy transistor NM6, the grid of redundancy transistor NM7 switches ground connection or connects the grid of base transistor NM0, the grid of base transistor NM4 receives the grid of base transistor NM0, operational amplifier A MP2 positive input terminal receives the drain electrode of base transistor NM0, the source electrode of the negative input termination switching tube NM8 of operational amplifier A MP2, the output terminal of operational amplifier A MP2 receives the grid of switching tube NM8, the drain electrode of switching tube NM8 is received electric current and is exported Iout1, the effect of image current output be the VGS voltage and VDS voltage mirror that are formed on transistor according to the input current of reference current importation on base transistor NM4, redundancy transistor NM5, redundancy transistor NM6, redundancy transistor NM7, form output current Iout1.

6. high-precision wide range of current current mirror according to claim 5, it is characterized in that: described electric current gear judges to hold with the VG of steering logic the output terminal receiving operational amplifier A MP1,: described electric current gear judges that the output with steering logic connects the control end of interrupteur SW 10, interrupteur SW 11 through interrupteur SW ITCH1, described electric current gear judges that the output with steering logic connects the control end of interrupteur SW 20, interrupteur SW 21 through interrupteur SW ITCH2, and described electric current gear judges that the output with steering logic connects the control end of interrupteur SW 30, interrupteur SW 31 through interrupteur SW ITCH3.

7. high-precision wide range of current current mirror according to claim 6, is characterized in that: described electric current gear judges the number controlling to open redundancy transistor with steering logic according to the size of VG voltage, and then realizes the switching of electric current gear.

8. high-precision wide range of current current mirror according to claim 6, is characterized in that: described electric current gear judges that comprising electric current gear with steering logic judges comparer COMP1, electric current gear judges comparer COMP2, logic gate device U1, logic gate device U2, logic gate device U3, logic gate device U4, logic gate device U5, logic gate device U6, logic gate device U7, logic gate device U8, logic gate device U9, logic gate device U10, logic gate device U11, logic gate device U12, logic gate device U13 and trigger D1, trigger D2, trigger D3, electric current gear judges the negative input termination reference voltage Vref h of comparer COMP1, electric current gear judges the grid of the positive input termination base transistor NM1 of comparer COMP1, and electric current gear judges that the output Vgh of comparer COMP1 receives logic gate device U7 respectively, logic gate device U10, the input end of logic gate device U13, electric current gear judges the negative input termination reference voltage Vref l of comparer COMP2, electric current gear judges the grid of the positive input termination base transistor of comparer COMP2, and electric current gear judges that the output Vgl of comparer COMP2 receives logic gate device U5 respectively, logic gate device U8, the input end of logic gate device U11.

9. high-precision wide range of current current mirror according to claim 8, is characterized in that: the qb end of an input contact hair device D1 of described logic gate device U1, the q end of another input contact of described logic gate device U1 hair device D2; The qb end of an input contact hair device D2 of described logic gate device U2, the q end of another input contact hair device D3 of described logic gate device U2; The output of logic gate device U1, logic gate device U2 and reset signal REST receive the input end of logic gate device U3 respectively; The input end of logic gate device U4 is received in the output of logic gate device U3, and the reset terminal r of trigger D1, trigger D2 and trigger D3 is received in the output of logic gate device U4; Described logic gate device U5 two input ends, the output that electric current gear judges comparer COMP2 is received in an input, and another receives the q end of trigger D1; Three input ends of described logic gate device U6 are the output of logic gate device U5; The output of logic gate device U7 and the qb end of trigger D2, the d exported as trigger D1 holds; Logic gate device U8 two input ends are the q end that electric current gear judges comparer COMP2 output terminal and trigger D2; Logic gate device U10 input end is that the q end of trigger D1 and electric current gear judge the output terminal of comparer COMP1; Logic gate device U9 input end is the qb end of logic gate device U8 output terminal, logic gate device U10 output terminal and trigger D3, and the input d that logic gate device U9 outputs to trigger D2 holds; Logic gate device U11 two input end is the q end that electric current gear judges comparer COMP2 output terminal and trigger D3; Logic gate device U13 tri-input ends are the q end of trigger D2, the q end of trigger D1 and electric current gear judge the output terminal of comparer COMP1; Logic gate device U12 two is input as the output terminal of logic gate device U11 and logic gate device U13, and the D end of trigger D3 is received in the output of logic gate device U12; The r end of trigger D1, trigger D2, trigger D3 is connected to logic gate device U4 and exports; The CK of trigger D3 holds short circuit to be connected to clock signal clk, the q terminating logic gate device U6 of trigger D1 exports, the q terminating logic gate device U9 of trigger D2 exports, the q terminating logic gate device U12 of trigger D3 exports, and the qb end difference output current gear of trigger D1, trigger D2, trigger D3 judges and interrupteur SW ITCH1, the interrupteur SW ITCH2 of steering logic, interrupteur SW ITCH3 signal; Electric current gear judges it is the size according to Vg voltage with the effect of steering logic, VGH and VGL pulse is produced by comparing with Vrefh and Vrefl, produce interrupteur SW ITCH1, interrupteur SW ITCH2, interrupteur SW ITCH3 switching signal, control conducting and the cut-off of alternative transistor.

10. high-precision wide range of current current mirror according to claim 1, is characterized in that: described image current output has two at least.